1 /* $NetBSD: cycv_platform.c,v 1.18 2021/04/24 23:36:25 thorpej Exp $ */ 2 3 /* This file is in the public domain. */ 4 5 #include "arml2cc.h" 6 #include "opt_console.h" 7 #include "opt_multiprocessor.h" 8 9 #include <sys/cdefs.h> 10 __KERNEL_RCSID(0, "$NetBSD: cycv_platform.c,v 1.18 2021/04/24 23:36:25 thorpej Exp $"); 11 12 #define _ARM32_BUS_DMA_PRIVATE 13 #include <sys/param.h> 14 #include <sys/bus.h> 15 #include <sys/cpu.h> 16 #include <sys/device.h> 17 18 #include <uvm/uvm_extern.h> 19 20 #include <arm/arm32/machdep.h> 21 22 #include <arm/altera/cycv_reg.h> 23 #include <arm/altera/cycv_var.h> 24 #include <arm/cortex/a9tmr_var.h> 25 #include <arm/cortex/pl310_var.h> 26 #include <arm/cortex/scu_reg.h> 27 28 #include <arm/bootconfig.h> 29 #include <arm/cpufunc.h> 30 31 #include <arm/fdt/arm_fdtvar.h> 32 #include <dev/fdt/fdtvar.h> 33 #include <dev/ic/comreg.h> 34 35 void cycv_platform_early_putchar(char); 36 37 void __noasan 38 cycv_platform_early_putchar(char c) { 39 #ifdef CONSADDR 40 #define CONSADDR_VA (CONSADDR - CYCV_PERIPHERAL_BASE + CYCV_PERIPHERAL_VBASE) 41 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 42 (volatile uint32_t *) CONSADDR_VA : 43 (volatile uint32_t *) CONSADDR; 44 45 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 46 ; 47 48 uartaddr[com_data] = htole32(c); 49 #endif 50 } 51 52 static const struct pmap_devmap * 53 cycv_platform_devmap(void) { 54 static const struct pmap_devmap devmap[] = { 55 DEVMAP_ENTRY(CYCV_PERIPHERAL_VBASE, 56 CYCV_PERIPHERAL_BASE, 57 CYCV_PERIPHERAL_SIZE), 58 DEVMAP_ENTRY_END 59 }; 60 61 return devmap; 62 } 63 64 static void 65 cycv_platform_bootstrap(void) 66 { 67 bus_space_tag_t bst = &armv7_generic_bs_tag; 68 bus_space_handle_t bsh_l2c; 69 70 bus_space_map(bst, CYCV_L2CACHE_BASE, CYCV_L2CACHE_SIZE, 0, &bsh_l2c); 71 72 #if NARML2CC > 0 73 arml2cc_init(bst, bsh_l2c, 0); 74 #endif 75 76 arm_fdt_cpu_bootstrap(); 77 } 78 79 static int 80 cycv_mpstart(void) 81 { 82 int ret = 0; 83 84 #ifdef MULTIPROCESSOR 85 bus_space_tag_t bst = &armv7_generic_bs_tag; 86 bus_space_handle_t bsh_rst; 87 bus_space_handle_t bsh_scu; 88 89 bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh_rst); 90 bus_space_map(bst, CYCV_SCU_BASE, CYCV_SCU_SIZE, 0, &bsh_scu); 91 92 /* Enable Snoop Control Unit */ 93 bus_space_write_4(bst, bsh_scu, SCU_INV_ALL_REG, 0xff); 94 bus_space_write_4(bst, bsh_scu, SCU_CTL, 95 bus_space_read_4(bst, bsh_scu, SCU_CTL) | SCU_CTL_SCU_ENA); 96 97 const uint32_t startfunc = 98 (uint32_t) KERN_VTOPHYS((vaddr_t) cpu_mpstart); 99 100 /* 101 * We place a "LDR PC, =cpu_mpstart" at address 0 in order to bootstrap 102 * CPU 1. We can't use the similar feature of the Boot ROM because 103 * it was unmapped by u-boot in favor of the SDRAM. 104 */ 105 pmap_map_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, CYCV_SDRAM_BASE, 106 L1_S_SIZE, VM_PROT_READ|VM_PROT_WRITE, PMAP_NOCACHE); 107 108 /* 0: LDR PC, [PC, #0x18] -> loads address at 0x20 into PC */ 109 *(volatile uint32_t *) CYCV_SDRAM_VBASE = htole32(0xe59ff018); 110 *(volatile uint32_t *) (CYCV_SDRAM_VBASE + 0x20) = startfunc; 111 112 pmap_unmap_chunk(kernel_l1pt.pv_va, CYCV_SDRAM_VBASE, L1_S_SIZE); 113 114 bus_space_write_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST, 115 bus_space_read_4(bst, bsh_rst, CYCV_RSTMGR_MPUMODRST) & 116 ~CYCV_RSTMGR_MPUMODRST_CPU1); 117 118 /* Wait for secondary processor to start */ 119 int i; 120 for (i = 0x10000000; i > 0; i--) { 121 if (cpu_hatched_p(1)) 122 break; 123 } 124 if (i == 0) { 125 aprint_error("cpu%d: WARNING: AP failed to start\n", 1); 126 ret++; 127 } 128 #endif 129 130 return ret; 131 } 132 133 static void 134 cycv_platform_init_attach_args(struct fdt_attach_args *faa) { 135 faa->faa_bst = &armv7_generic_bs_tag; 136 faa->faa_dmat = &arm_generic_dma_tag; 137 } 138 139 static void 140 cycv_platform_device_register(device_t dev, void *aux) 141 { 142 prop_dictionary_t dict = device_properties(dev); 143 144 if (device_is_a(dev, "arma9tmr")) { 145 prop_dictionary_set_uint32(dict, "frequency", 146 cycv_clkmgr_early_get_mpu_clk() / 4); 147 } 148 } 149 150 static void 151 cycv_platform_reset(void) { 152 bus_space_tag_t bst = &armv7_generic_bs_tag; 153 bus_space_handle_t bsh; 154 uint32_t val; 155 156 bus_space_map(bst, CYCV_RSTMGR_BASE, CYCV_RSTMGR_SIZE, 0, &bsh); 157 val = bus_space_read_4(bst, bsh, CYCV_RSTMGR_CTRL); 158 bus_space_write_4(bst, bsh, CYCV_RSTMGR_CTRL, 159 val | CYCV_RSTMGR_CTRL_SWCOLDRSTREQ); 160 } 161 162 static u_int 163 cycv_platform_uart_freq(void) { 164 return cycv_clkmgr_early_get_l4_sp_clk(); 165 } 166 167 static const struct arm_platform cycv_platform = { 168 .ap_devmap = cycv_platform_devmap, 169 .ap_bootstrap = cycv_platform_bootstrap, 170 .ap_init_attach_args = cycv_platform_init_attach_args, 171 .ap_device_register = cycv_platform_device_register, 172 .ap_reset = cycv_platform_reset, 173 .ap_delay = a9tmr_delay, 174 .ap_uart_freq = cycv_platform_uart_freq, 175 .ap_mpstart = cycv_mpstart, 176 }; 177 178 ARM_PLATFORM(cycv, "altr,socfpga-cyclone5", &cycv_platform); 179