1 /* $NetBSD: acpipchb.c,v 1.20 2020/06/17 06:46:09 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill@invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: acpipchb.c,v 1.20 2020/06/17 06:46:09 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/queue.h> 42 #include <sys/mutex.h> 43 #include <sys/kmem.h> 44 #include <sys/cpu.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include <dev/acpi/acpivar.h> 53 #include <dev/acpi/acpi_pci.h> 54 #include <dev/acpi/acpi_mcfg.h> 55 56 #include <arm/acpi/acpi_pci_machdep.h> 57 58 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 59 60 #define ACPIPCHB_MAX_RANGES 64 /* XXX arbitrary limit */ 61 62 struct acpipchb_bus_range { 63 bus_addr_t min; 64 bus_addr_t max; 65 bus_addr_t offset; 66 }; 67 68 struct acpipchb_bus_space { 69 struct bus_space bs; 70 71 struct acpipchb_bus_range range[ACPIPCHB_MAX_RANGES]; 72 int nrange; 73 74 int (*map)(void *, bus_addr_t, bus_size_t, 75 int, bus_space_handle_t *); 76 77 int flags; 78 }; 79 80 struct acpipchb_softc { 81 device_t sc_dev; 82 83 bus_space_tag_t sc_memt; 84 85 ACPI_HANDLE sc_handle; 86 ACPI_INTEGER sc_bus; 87 88 struct acpipchb_bus_space sc_pcimem_bst; 89 struct acpipchb_bus_space sc_pciio_bst; 90 }; 91 92 static int acpipchb_match(device_t, cfdata_t, void *); 93 static void acpipchb_attach(device_t, device_t, void *); 94 95 static void acpipchb_setup_ranges(struct acpipchb_softc *, struct pcibus_attach_args *); 96 static void acpipchb_setup_quirks(struct acpipchb_softc *, struct pcibus_attach_args *); 97 98 CFATTACH_DECL_NEW(acpipchb, sizeof(struct acpipchb_softc), 99 acpipchb_match, acpipchb_attach, NULL, NULL); 100 101 static const char * const compatible[] = { 102 "PNP0A08", 103 NULL 104 }; 105 106 static int 107 acpipchb_match(device_t parent, cfdata_t cf, void *aux) 108 { 109 struct acpi_attach_args *aa = aux; 110 111 if (aa->aa_node->ad_type != ACPI_TYPE_DEVICE) 112 return 0; 113 114 return acpi_match_hid(aa->aa_node->ad_devinfo, compatible); 115 } 116 117 static void 118 acpipchb_attach(device_t parent, device_t self, void *aux) 119 { 120 struct acpipchb_softc * const sc = device_private(self); 121 struct acpi_attach_args *aa = aux; 122 struct pcibus_attach_args pba; 123 ACPI_INTEGER seg; 124 uint16_t bus_start; 125 126 sc->sc_dev = self; 127 sc->sc_memt = aa->aa_memt; 128 sc->sc_handle = aa->aa_node->ad_handle; 129 130 /* 131 * First try to derive the base bus number from _CRS. If that fails, 132 * try _BBN. If that fails too, assume bus 0. 133 */ 134 if (ACPI_SUCCESS(acpi_pcidev_pciroot_bus(sc->sc_handle, &bus_start))) { 135 sc->sc_bus = bus_start; 136 } else { 137 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_BBN", &sc->sc_bus))) 138 sc->sc_bus = 0; 139 } 140 141 if (ACPI_FAILURE(acpi_eval_integer(sc->sc_handle, "_SEG", &seg))) 142 seg = 0; 143 144 aprint_naive("\n"); 145 aprint_normal(": PCI Express Host Bridge\n"); 146 147 if (acpi_pci_ignore_boot_config(sc->sc_handle)) { 148 if (acpimcfg_configure_bus(self, aa->aa_pc, sc->sc_handle, sc->sc_bus, PCIHOST_CACHELINE_SIZE) != 0) 149 aprint_error_dev(self, "failed to configure bus\n"); 150 } 151 152 memset(&pba, 0, sizeof(pba)); 153 pba.pba_flags = aa->aa_pciflags & ~(PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY); 154 pba.pba_memt = 0; 155 pba.pba_iot = 0; 156 pba.pba_dmat = aa->aa_dmat; 157 #ifdef _PCI_HAVE_DMA64 158 pba.pba_dmat64 = aa->aa_dmat64; 159 #endif 160 pba.pba_pc = aa->aa_pc; 161 pba.pba_bus = sc->sc_bus; 162 163 acpipchb_setup_ranges(sc, &pba); 164 acpipchb_setup_quirks(sc, &pba); 165 166 config_found_ia(self, "pcibus", &pba, pcibusprint); 167 } 168 169 struct acpipchb_setup_ranges_args { 170 struct acpipchb_softc *sc; 171 struct pcibus_attach_args *pba; 172 }; 173 174 static int 175 acpipchb_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 176 bus_space_handle_t *bshp) 177 { 178 struct acpipchb_bus_space * const abs = t; 179 int i; 180 181 if (size == 0) 182 return ERANGE; 183 184 if ((abs->flags & PCI_FLAGS_IO_OKAY) != 0) { 185 /* Force strongly ordered mapping for all I/O space */ 186 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 187 } 188 189 for (i = 0; i < abs->nrange; i++) { 190 struct acpipchb_bus_range * const range = &abs->range[i]; 191 if (bpa >= range->min && bpa + size - 1 <= range->max) 192 return abs->map(t, bpa + range->offset, size, flag, bshp); 193 } 194 195 return ERANGE; 196 } 197 198 static ACPI_STATUS 199 acpipchb_setup_ranges_cb(ACPI_RESOURCE *res, void *ctx) 200 { 201 struct acpipchb_setup_ranges_args * const args = ctx; 202 struct acpipchb_softc * const sc = args->sc; 203 struct pcibus_attach_args *pba = args->pba; 204 struct acpipchb_bus_space *abs; 205 struct acpipchb_bus_range *range; 206 const char *range_type; 207 u_int pci_flags; 208 209 if (res->Type != ACPI_RESOURCE_TYPE_ADDRESS32 && 210 res->Type != ACPI_RESOURCE_TYPE_ADDRESS64) 211 return AE_OK; 212 213 switch (res->Data.Address.ResourceType) { 214 case ACPI_IO_RANGE: 215 abs = &sc->sc_pciio_bst; 216 range_type = "I/O"; 217 pci_flags = PCI_FLAGS_IO_OKAY; 218 break; 219 case ACPI_MEMORY_RANGE: 220 abs = &sc->sc_pcimem_bst; 221 range_type = "MEM"; 222 pci_flags = PCI_FLAGS_MEM_OKAY; 223 break; 224 default: 225 return AE_OK; 226 } 227 228 if (abs->nrange == ACPIPCHB_MAX_RANGES) { 229 aprint_error_dev(sc->sc_dev, 230 "maximum number of ranges reached, increase ACPIPCHB_MAX_RANGES\n"); 231 return AE_LIMIT; 232 } 233 234 range = &abs->range[abs->nrange]; 235 switch (res->Type) { 236 case ACPI_RESOURCE_TYPE_ADDRESS32: 237 range->min = res->Data.Address32.Address.Minimum; 238 range->max = res->Data.Address32.Address.Maximum; 239 range->offset = res->Data.Address32.Address.TranslationOffset; 240 break; 241 case ACPI_RESOURCE_TYPE_ADDRESS64: 242 range->min = res->Data.Address64.Address.Minimum; 243 range->max = res->Data.Address64.Address.Maximum; 244 range->offset = res->Data.Address64.Address.TranslationOffset; 245 break; 246 default: 247 return AE_OK; 248 } 249 abs->nrange++; 250 251 aprint_debug_dev(sc->sc_dev, "PCI %s [%#lx-%#lx] -> %#lx\n", range_type, range->min, range->max, range->offset); 252 253 if ((pba->pba_flags & pci_flags) == 0) { 254 abs->bs = *sc->sc_memt; 255 abs->bs.bs_cookie = abs; 256 abs->map = abs->bs.bs_map; 257 abs->flags = pci_flags; 258 abs->bs.bs_map = acpipchb_bus_space_map; 259 if ((pci_flags & PCI_FLAGS_IO_OKAY) != 0) 260 pba->pba_iot = &abs->bs; 261 else if ((pci_flags & PCI_FLAGS_MEM_OKAY) != 0) 262 pba->pba_memt = &abs->bs; 263 pba->pba_flags |= pci_flags; 264 } 265 266 return AE_OK; 267 } 268 269 static void 270 acpipchb_setup_ranges(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 271 { 272 struct acpipchb_setup_ranges_args args; 273 274 args.sc = sc; 275 args.pba = pba; 276 277 AcpiWalkResources(sc->sc_handle, "_CRS", acpipchb_setup_ranges_cb, &args); 278 } 279 280 static void 281 acpipchb_setup_quirks(struct acpipchb_softc *sc, struct pcibus_attach_args *pba) 282 { 283 struct arm32_pci_chipset *md_pc = (struct arm32_pci_chipset *)pba->pba_pc; 284 struct acpi_pci_context *ap = md_pc->pc_conf_v; 285 286 pba->pba_flags &= ~ap->ap_pciflags_clear; 287 } 288