1 /* $NetBSD: acpi_platform.c,v 1.32 2021/10/24 11:58:23 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jared McNeill <jmcneill@invisible.ca>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include "com.h" 33 #include "plcom.h" 34 #include "opt_efi.h" 35 #include "opt_multiprocessor.h" 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: acpi_platform.c,v 1.32 2021/10/24 11:58:23 jmcneill Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/cpu.h> 43 #include <sys/device.h> 44 #include <sys/termios.h> 45 #include <sys/kprintf.h> 46 47 #include <dev/fdt/fdtvar.h> 48 #include <arm/fdt/arm_fdtvar.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <machine/bootconfig.h> 53 #include <arm/cpufunc.h> 54 #include <arm/locore.h> 55 56 #include <arm/cortex/gtmr_var.h> 57 58 #include <arm/arm/smccc.h> 59 #include <arm/arm/psci.h> 60 #include <arm/fdt/psci_fdtvar.h> 61 62 #include <evbarm/fdt/platform.h> 63 64 #include <evbarm/dev/plcomreg.h> 65 #include <evbarm/dev/plcomvar.h> 66 #include <dev/ic/ns16550reg.h> 67 #include <dev/ic/comreg.h> 68 #include <dev/ic/comvar.h> 69 70 #if NCOM > 0 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pucvar.h> 74 #endif 75 76 #ifdef EFI_RUNTIME 77 #include <arm/arm/efi_runtime.h> 78 #endif 79 80 #include <dev/acpi/acpireg.h> 81 #include <dev/acpi/acpivar.h> 82 #include <arm/acpi/acpi_table.h> 83 84 #include <libfdt.h> 85 86 #define ACPI_DBG2_16550_GAS 0x0012 87 88 #define SPCR_BAUD_DEFAULT 0 89 #define SPCR_BAUD_9600 3 90 #define SPCR_BAUD_19200 4 91 #define SPCR_BAUD_57600 6 92 #define SPCR_BAUD_115200 7 93 94 static const struct acpi_spcr_baud_rate { 95 uint8_t id; 96 int baud_rate; 97 } acpi_spcr_baud_rates[] = { 98 /* 99 * SPCR_BAUD_DEFAULT means: 100 * "As is, operating system relies on the current configuration 101 * of serial port until the full featured driver will be 102 * initialized." 103 * 104 * We don't currently have a good way of telling the UART driver 105 * to detect the currently configured baud rate, so just pick 106 * something sensible here. 107 * 108 * In the past we have tried baud_rate values of 0 and -1, but 109 * these cause problems with the com(4) driver. 110 */ 111 { SPCR_BAUD_DEFAULT, 115200 }, 112 { SPCR_BAUD_9600, 9600 }, 113 { SPCR_BAUD_19200, 19200 }, 114 { SPCR_BAUD_57600, 57600 }, 115 { SPCR_BAUD_115200, 115200 }, 116 }; 117 118 extern struct bus_space arm_generic_bs_tag; 119 120 #if NPLCOM > 0 121 static struct plcom_instance plcom_console; 122 #endif 123 124 struct arm32_bus_dma_tag acpi_coherent_dma_tag; 125 static struct arm32_dma_range acpi_coherent_ranges[] = { 126 [0] = { 127 .dr_sysbase = 0, 128 .dr_busbase = 0, 129 .dr_len = UINTPTR_MAX, 130 .dr_flags = _BUS_DMAMAP_COHERENT, 131 } 132 }; 133 134 static const struct pmap_devmap * 135 acpi_platform_devmap(void) 136 { 137 static const struct pmap_devmap devmap[] = { 138 DEVMAP_ENTRY_END 139 }; 140 141 return devmap; 142 } 143 144 static void 145 acpi_platform_bootstrap(void) 146 { 147 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 148 149 acpi_coherent_dma_tag = arm_generic_dma_tag; 150 acpi_coherent_dma_tag._ranges = acpi_coherent_ranges; 151 acpi_coherent_dma_tag._nranges = __arraycount(acpi_coherent_ranges); 152 } 153 154 static void 155 acpi_platform_attach_uart(ACPI_TABLE_SPCR *spcr) 156 { 157 #if NCOM > 0 158 struct com_regs regs; 159 bus_space_handle_t dummy_bsh; 160 u_int reg_shift; 161 #endif 162 int baud_rate, n; 163 164 /* 165 * Only MMIO access is supported today. 166 */ 167 if (spcr->SerialPort.SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) { 168 return; 169 } 170 if (le64toh(spcr->SerialPort.Address) == 0) { 171 return; 172 } 173 174 /* 175 * Lookup SPCR baud rate. 176 */ 177 baud_rate = 0; 178 for (n = 0; n < __arraycount(acpi_spcr_baud_rates); n++) { 179 if (acpi_spcr_baud_rates[n].id == spcr->BaudRate) { 180 baud_rate = acpi_spcr_baud_rates[n].baud_rate; 181 break; 182 } 183 } 184 185 /* 186 * Attach console device. 187 */ 188 switch (spcr->InterfaceType) { 189 #if NPLCOM > 0 190 case ACPI_DBG2_ARM_PL011: 191 case ACPI_DBG2_ARM_SBSA_32BIT: 192 case ACPI_DBG2_ARM_SBSA_GENERIC: 193 plcom_console.pi_type = PLCOM_TYPE_PL011; 194 plcom_console.pi_iot = &arm_generic_bs_tag; 195 plcom_console.pi_iobase = le64toh(spcr->SerialPort.Address); 196 plcom_console.pi_size = PL011COM_UART_SIZE; 197 plcom_console.pi_flags = PLC_FLAG_32BIT_ACCESS; 198 199 plcomcnattach(&plcom_console, baud_rate, 0, TTYDEF_CFLAG, -1); 200 break; 201 #endif 202 203 #if NCOM > 0 204 case ACPI_DBG2_16550_COMPATIBLE: 205 case ACPI_DBG2_16550_SUBSET: 206 case ACPI_DBG2_16550_GAS: 207 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 208 switch (spcr->SerialPort.BitWidth) { 209 case 8: 210 reg_shift = 0; 211 break; 212 case 16: 213 reg_shift = 1; 214 break; 215 case 32: 216 reg_shift = 2; 217 break; 218 default: 219 /* 220 * Bit width 0 is possible for types 0 and 1. Otherwise, 221 * possibly buggy firmware. 222 */ 223 if (spcr->InterfaceType == ACPI_DBG2_16550_COMPATIBLE) { 224 reg_shift = 0; 225 } else { 226 reg_shift = 2; 227 } 228 break; 229 } 230 com_init_regs_stride(®s, &arm_generic_bs_tag, dummy_bsh, 231 le64toh(spcr->SerialPort.Address), reg_shift); 232 comcnattach1(®s, baud_rate, -1, COM_TYPE_NORMAL, 233 TTYDEF_CFLAG); 234 break; 235 236 case ACPI_DBG2_BCM2835: 237 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 238 com_init_regs_stride(®s, &arm_generic_bs_tag, dummy_bsh, 239 le64toh(spcr->SerialPort.Address) + 0x40, 2); 240 comcnattach1(®s, baud_rate, -1, COM_TYPE_BCMAUXUART, 241 TTYDEF_CFLAG); 242 cn_set_magic("+++++"); 243 break; 244 #endif 245 246 default: 247 printf("SPCR: kernel does not support interface type %#x\n", 248 spcr->InterfaceType); 249 break; 250 } 251 252 /* 253 * UEFI firmware may leave the console in an undesireable state (wrong 254 * foreground/background colour, etc). Reset the terminal and clear 255 * text from the cursor to the end of the screne. 256 */ 257 printf_flags(TOCONS|NOTSTAMP, "\033[0m"); 258 printf_flags(TOCONS|NOTSTAMP, "\033[0J"); 259 } 260 261 static void 262 acpi_platform_startup(void) 263 { 264 ACPI_TABLE_SPCR *spcr; 265 ACPI_TABLE_FADT *fadt; 266 #ifdef MULTIPROCESSOR 267 ACPI_TABLE_MADT *madt; 268 #endif 269 270 /* 271 * Setup serial console device 272 */ 273 if (ACPI_SUCCESS(acpi_table_find(ACPI_SIG_SPCR, (void **)&spcr))) { 274 acpi_platform_attach_uart(spcr); 275 acpi_table_unmap((ACPI_TABLE_HEADER *)spcr); 276 } 277 278 /* 279 * Initialize PSCI 0.2+ if implemented 280 */ 281 if (ACPI_SUCCESS(acpi_table_find(ACPI_SIG_FADT, (void **)&fadt))) { 282 const uint16_t boot_flags = le16toh(fadt->ArmBootFlags); 283 if ((boot_flags & ACPI_FADT_PSCI_COMPLIANT) != 0) { 284 if ((boot_flags & ACPI_FADT_PSCI_USE_HVC) != 0) { 285 psci_init(psci_call_hvc); 286 } else { 287 psci_init(psci_call_smc); 288 } 289 smccc_probe(); 290 } 291 acpi_table_unmap((ACPI_TABLE_HEADER *)fadt); 292 } 293 294 #ifdef MULTIPROCESSOR 295 /* 296 * Count CPUs 297 */ 298 if (ACPI_SUCCESS(acpi_table_find(ACPI_SIG_MADT, (void **)&madt))) { 299 char *end = (char *)madt + le32toh(madt->Header.Length); 300 char *where = (char *)madt + sizeof(ACPI_TABLE_MADT); 301 while (where < end) { 302 ACPI_SUBTABLE_HEADER *subtable = 303 (ACPI_SUBTABLE_HEADER *)where; 304 if (subtable->Type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) 305 arm_cpu_max++; 306 where += subtable->Length; 307 } 308 acpi_table_unmap((ACPI_TABLE_HEADER *)madt); 309 } 310 #endif /* MULTIPROCESSOR */ 311 } 312 313 static void 314 acpi_platform_init_attach_args(struct fdt_attach_args *faa) 315 { 316 extern struct bus_space arm_generic_bs_tag; 317 318 faa->faa_bst = &arm_generic_bs_tag; 319 faa->faa_dmat = &acpi_coherent_dma_tag; 320 } 321 322 static void 323 acpi_platform_device_register(device_t self, void *aux) 324 { 325 #if NCOM > 0 326 prop_dictionary_t prop = device_properties(self); 327 ACPI_STATUS rv; 328 329 if (device_is_a(self, "com")) { 330 ACPI_TABLE_SPCR *spcr; 331 332 rv = acpi_table_find(ACPI_SIG_SPCR, (void **)&spcr); 333 if (ACPI_FAILURE(rv)) { 334 return; 335 } 336 337 if (spcr->SerialPort.SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) { 338 goto spcr_unmap; 339 } 340 if (le64toh(spcr->SerialPort.Address) == 0) { 341 goto spcr_unmap; 342 } 343 if (spcr->InterfaceType != ACPI_DBG2_16550_COMPATIBLE && 344 spcr->InterfaceType != ACPI_DBG2_16550_SUBSET) { 345 goto spcr_unmap; 346 } 347 348 if (device_is_a(device_parent(self), "puc")) { 349 const struct puc_attach_args * const paa = aux; 350 int b, d, f; 351 352 const int s = pci_get_segment(paa->pc); 353 pci_decompose_tag(paa->pc, paa->tag, &b, &d, &f); 354 355 if (spcr->PciSegment == s && spcr->PciBus == b && 356 spcr->PciDevice == d && spcr->PciFunction == f) { 357 prop_dictionary_set_bool(prop, 358 "force_console", true); 359 } 360 } 361 362 if (device_is_a(device_parent(self), "acpi")) { 363 struct acpi_attach_args * const aa = aux; 364 struct acpi_resources res; 365 struct acpi_mem *mem; 366 367 if (ACPI_FAILURE(acpi_resource_parse(self, 368 aa->aa_node->ad_handle, "_CRS", &res, 369 &acpi_resource_parse_ops_quiet))) { 370 goto spcr_unmap; 371 } 372 373 mem = acpi_res_mem(&res, 0); 374 if (mem == NULL) { 375 goto crs_cleanup; 376 } 377 378 if (mem->ar_base == le64toh(spcr->SerialPort.Address)) { 379 prop_dictionary_set_bool(prop, 380 "force_console", true); 381 } 382 383 crs_cleanup: 384 acpi_resource_cleanup(&res); 385 } 386 387 spcr_unmap: 388 acpi_table_unmap((ACPI_TABLE_HEADER *)spcr); 389 } 390 #endif 391 } 392 393 static void 394 acpi_platform_reset(void) 395 { 396 #ifdef EFI_RUNTIME 397 if (arm_efirt_reset(EFI_RESET_COLD) == 0) 398 return; 399 #endif 400 if (psci_available()) 401 psci_system_reset(); 402 } 403 404 static u_int 405 acpi_platform_uart_freq(void) 406 { 407 return 0; 408 } 409 410 static const struct arm_platform acpi_platform = { 411 .ap_devmap = acpi_platform_devmap, 412 .ap_bootstrap = acpi_platform_bootstrap, 413 .ap_startup = acpi_platform_startup, 414 .ap_init_attach_args = acpi_platform_init_attach_args, 415 .ap_device_register = acpi_platform_device_register, 416 .ap_reset = acpi_platform_reset, 417 .ap_delay = gtmr_delay, 418 .ap_uart_freq = acpi_platform_uart_freq, 419 }; 420 421 ARM_PLATFORM(acpi, "netbsd,generic-acpi", &acpi_platform); 422