1 /* $NetBSD: intr.h,v 1.6 2001/01/15 20:19:52 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ignatios Souvatzis. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * machine/intr.h for the Amiga port. 41 * Currently, only a wrapper, for most of the stuff, around the old 42 * include files. 43 */ 44 45 #ifndef _MACHINE_INTR_H_ 46 #define _MACHINE_INTR_H_ 47 48 #include <amiga/amiga/isr.h> 49 #include <amiga/include/mtpr.h> 50 51 /* ADAM: commented out 52 #define IPL_SOFTSERIAL 1 53 #define IPL_SOFTNET 1 54 */ 55 56 #ifdef splaudio 57 #undef splaudio 58 #define splaudio spl6 59 #endif 60 61 #define spllpt() spl6() 62 63 /* ADAM: from macppc/intr.h */ 64 /* Interrupt priority `levels'. */ 65 #define IPL_NONE 9 /* nothing */ 66 #define IPL_SOFTCLOCK 8 /* timeouts */ 67 #define IPL_SOFTNET 7 /* protocol stacks */ 68 #define IPL_BIO 6 /* block I/O */ 69 #define IPL_NET 5 /* network */ 70 #define IPL_SOFTSERIAL 4 /* serial */ 71 #define IPL_TTY 3 /* terminal */ 72 #define IPL_IMP 3 /* memory allocation */ 73 #define IPL_AUDIO 2 /* audio */ 74 #define IPL_CLOCK 1 /* clock */ 75 #define IPL_HIGH 1 /* everything */ 76 #define IPL_SERIAL 0 /* serial */ 77 #define NIPL 10 78 79 /* Interrupt sharing types. */ 80 #define IST_NONE 0 /* none */ 81 #define IST_PULSE 1 /* pulsed */ 82 #define IST_EDGE 2 /* edge-triggered */ 83 #define IST_LEVEL 3 /* level-triggered */ 84 85 #ifndef _LOCORE 86 87 /* 88 * Interrupt handler chains. intr_establish() inserts a handler into 89 * the list. The handler is called with its (single) argument. 90 */ 91 struct intrhand { 92 int (*ih_fun) __P((void *)); 93 void *ih_arg; 94 u_long ih_count; 95 struct intrhand *ih_next; 96 int ih_level; 97 int ih_irq; 98 }; 99 100 void clearsoftclock __P((void)); 101 int splsoftclock __P((void)); 102 /* 103 void setsoftnet __P((void)); 104 */ 105 void clearsoftnet __P((void)); 106 int splsoftnet __P((void)); 107 108 void do_pending_int __P((void)); 109 110 static __inline int splraise __P((int)); 111 static __inline int spllower __P((int)); 112 static __inline void splx __P((int)); 113 static __inline void softintr __P((int)); 114 115 /* 116 extern volatile int cpl, ipending, astpending, tickspending; 117 */ 118 extern int imask[]; 119 120 /* 121 * Reorder protection in the following inline functions is 122 * achived with the "eieio" instruction which the assembler 123 * seems to detect and then doen't move instructions past.... 124 */ 125 static __inline int 126 splraise(ncpl) 127 int ncpl; 128 { 129 int ocpl; 130 131 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 132 /* 133 ocpl = cpl; 134 cpl = ocpl | ncpl; 135 */ 136 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 137 return (ocpl); 138 } 139 140 static __inline void 141 splx(ncpl) 142 int ncpl; 143 { 144 145 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 146 /* 147 cpl = ncpl; 148 if (ipending & ~ncpl) 149 do_pending_int(); 150 */ 151 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 152 } 153 154 static __inline int 155 spllower(ncpl) 156 int ncpl; 157 { 158 int ocpl; 159 160 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 161 /* 162 ocpl = cpl; 163 cpl = ncpl; 164 if (ipending & ~ncpl) 165 do_pending_int(); 166 */ 167 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 168 return (ocpl); 169 } 170 171 /* Following code should be implemented with lwarx/stwcx to avoid 172 * the disable/enable. i need to read the manual once more.... */ 173 static __inline void 174 softintr(ipl) 175 int ipl; 176 { 177 int msrsave; 178 179 __asm__ volatile("mfmsr %0" : "=r"(msrsave)); 180 __asm__ volatile("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 181 // ipending |= 1 << ipl; 182 __asm__ volatile("mtmsr %0" :: "r"(msrsave)); 183 } 184 185 #define ICU_LEN 32 186 187 /* Soft interrupt masks. */ 188 /* 189 #define SIR_CLOCK 28 190 #define SIR_NET 29 191 #define SIR_SERIAL 30 192 */ 193 #define SPL_CLOCK 31 194 195 /* 196 * Hardware interrupt masks 197 */ 198 #define splbio() splraise(imask[IPL_BIO]) 199 #define splnet() splraise(imask[IPL_NET]) 200 #define spltty() splraise(imask[IPL_TTY]) 201 #define splaudio() splraise(imask[IPL_AUDIO]) 202 #define splclock() splraise(imask[IPL_CLOCK]) 203 #define splstatclock() splclock() 204 #define splserial() splraise(imask[IPL_SERIAL]) 205 206 /* ADAM: see above 207 #define spllpt() spltty() 208 */ 209 210 /* 211 * Software interrupt masks 212 * 213 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 214 * clock to softclock before it calls softclock(). 215 */ 216 #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 217 #define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 218 #define splsoftnet() splraise(imask[IPL_SOFTNET]) 219 #define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 220 221 /* 222 * Miscellaneous 223 */ 224 #define splimp() splraise(imask[IPL_IMP]) 225 #define splvm() splraise(imask[IPL_IMP]) 226 #define splhigh() splraise(imask[IPL_HIGH]) 227 #define splsched() splhigh() 228 #define spllock() splhigh() 229 #define spl0() spllower(0) 230 231 /* 232 #define setsoftnet() softintr(SIR_NET) 233 #define setsoftserial() softintr(SIR_SERIAL) 234 */ 235 extern long intrcnt[]; 236 237 #define CNT_IRQ0 0 238 #define CNT_CLOCK 64 239 #define CNT_SOFTCLOCK 65 240 #define CNT_SOFTNET 66 241 #define CNT_SOFTSERIAL 67 242 243 #endif /* !_LOCORE */ 244 245 #endif /* !_MACPPC_INTR_H_ */ 246