1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Utah Hdr: cpu.h 1.16 91/03/25 39 * from: @(#)cpu.h 7.7 (Berkeley) 6/27/91 40 * $Id: cpu.h,v 1.3 1993/09/02 18:08:19 mw Exp $ 41 */ 42 43 /* 44 * Exported definitions unique to amiga/68k cpu support. 45 */ 46 47 /* 48 * definitions of cpu-dependent requirements 49 * referenced in generic code 50 */ 51 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 52 53 /* 54 * function vs. inline configuration; 55 * these are defined to get generic functions 56 * rather than inline or machine-dependent implementations 57 */ 58 #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */ 59 #undef NEED_FFS /* don't need ffs function */ 60 #undef NEED_BCMP /* don't need bcmp function */ 61 #undef NEED_STRLEN /* don't need strlen function */ 62 63 #define cpu_exec(p) /* nothing */ 64 #define cpu_wait(p) /* nothing */ 65 66 /* 67 * Arguments to hardclock, softclock and gatherstats 68 * encapsulate the previous machine state in an opaque 69 * clockframe; for hp300, use just what the hardware 70 * leaves on the stack. 71 */ 72 typedef struct intrframe { 73 int pc; 74 int ps; 75 } clockframe; 76 77 #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0) 78 #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0) 79 #define CLKF_PC(framep) ((framep)->pc) 80 81 82 /* 83 * Preempt the current process if in interrupt from user mode, 84 * or after the current trap/syscall if in system mode. 85 */ 86 #define need_resched() { want_resched++; aston(); } 87 88 /* 89 * Give a profiling tick to the current process from the softclock 90 * interrupt. On hp300, request an ast to send us through trap(), 91 * marking the proc as needing a profiling tick. 92 */ 93 #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } 94 95 /* 96 * Notify the current process (p) that it has a signal pending, 97 * process as soon as possible. 98 */ 99 #define signotify(p) aston() 100 101 #define aston() (astpending++) 102 103 int astpending; /* need to trap before returning to user mode */ 104 int want_resched; /* resched() was called */ 105 106 107 /* 108 * simulated software interrupt register 109 */ 110 extern unsigned char ssir; 111 112 #define SIR_NET 0x1 113 #define SIR_CLOCK 0x2 114 115 #define siroff(x) ssir &= ~(x) 116 #define setsoftnet() ssir |= SIR_NET 117 #define setsoftclock() ssir |= SIR_CLOCK 118 119 120 /* 121 * The rest of this should probably be moved to ../amiga/amigacpu.h, 122 * although some of it could probably be put into generic 68k headers. 123 */ 124 125 /* values for machineid (happen to be AFF_* settings of AttnFlags) 126 * NOTE: '40 support does NOT YET exist! */ 127 #define AMIGA_68020 (1L<<1) 128 #define AMIGA_68030 (1L<<2) 129 #define AMIGA_68040 (1L<<3) 130 #define AMIGA_68881 (1L<<4) 131 #define AMIGA_68882 (1L<<5) 132 #define AMIGA_FPU40 (1L<<6) 133 134 135 /* values for mmutype (assigned for quick testing) */ 136 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 137 #define MMU_68851 1 /* Motorola 68851 */ 138 139 /* values for cpuspeed (not really related to clock speed due to caches) */ 140 #define MHZ_8 1 141 #define MHZ_16 2 142 #define MHZ_25 3 143 #define MHZ_33 4 144 #define MHZ_50 6 145 146 #ifdef KERNEL 147 extern int machineid, mmutype; 148 149 /* what is this supposed to do? i.e. how is it different than startrtclock? 150 #define enablertclock() 151 152 Answer (MW): startrtclock is supposed to start the clock chip (to get an 153 accurate uptime, enablertclock is called later (after *vital* stuff 154 has been setup) to enable clock interrupts. Enabling clock interrupts 155 at startrtclock-time can get you into big troubles... */ 156 157 #endif 158 159 /* physical memory sections */ 160 #define CHIPMEMBASE (0x00000000) 161 /* maximum for mapping, not the whole range is needed in physical equivalence */ 162 #define CHIPMEMTOP (0x00200000) 163 #define CHIPMEMSIZE btoc(CHIPMEMTOP-CHIPMEMBASE) 164 /* CIA-A and CIA-B */ 165 #define CIABASE (0x00BFC000) 166 #define CIATOP (0x00C00000) 167 #define CIASIZE btoc(CIATOP-CIABASE) 168 #if 0 169 #define CUSTOMBASE (0x00DFE000) 170 #define CUSTOMTOP (0x00E00000) 171 #define CUSTOMSIZE btoc(CUSTOMTOP-CUSTOMBASE) 172 #ifdef A3000 173 #define SCSIBASE (0x00DD0000) 174 #define SCSITOP (0x00DD0000+AMIGA_PAGE_SIZE) 175 #define SCSISIZE btoc(SCSITOP-SCSIBASE) 176 #endif 177 #else 178 /* zorro2 really starts at 0x00E00000, but starting mapping at D8 also 179 includes the clock and scsi space on the A3000, as well as the 180 normal custom chip area on any amiga. That's nice :-)) */ 181 #define ZORRO2BASE (0x00D80000) 182 #define ZORRO2TOP (0x00F80000) 183 #define ZORRO2SIZE btoc(ZORRO2TOP-ZORRO2BASE) 184 #define CUSTOMBASE (0x00DFF000) /* now just offset rel to zorro2 */ 185 #endif 186 187 /* XXX only correct for A3000 memory map! 188 * corresponds to address of last physical memory page, for A3000 189 * this is always 0x08000000 - pagesize (== NBPS) 190 */ 191 #define MAXADDR (0x08000000 - UPAGES) 192 193 194 #if 0 195 /* these are not used, verbatim from hp300, but not used :-)) */ 196 197 /* Amiga specific mappings: 198 * 199 * phys-start map-start phys-end map-end name 200 * 201 * 0x00000000 chipmembase - 0x00200000 chipmemlimit CHIP MEM 202 * 0x00be0000 ciabase - 0x00c00000 cialimit CIA-B/CIA-A 203 * 0x00d80000 customchipbase - 0x00f00000 customchiplimit CUSTOM/ZORRO2 204 */ 205 #define ISCHIPMEM(va) \ 206 ((char *)(va) >= chipmembase && (char *)(va) < chipmemlimit) 207 #define CHIPMEMV(pa) ((int)(pa)-CHIPMEMBASE+(int)chipmembase) 208 #define CHIPMEMP(va) ((int)(va)-(int)chipmembase+CHIPMEMBASE) 209 #define CHIPMEMPOFF(pa) ((int)(pa)-CHIPMEMBASE) 210 #define CHIPMEMMAPSIZE btoc(CHIPMEMTOP-CHIPMEMBASE) /* 2mb */ 211 212 #define ISCIA(va) \ 213 ((char *)(va) >= ciabase && (char *)(va) < cialimit) 214 #define CIAV(pa) ((int)(pa)-CIABASE+(int)ciabase) 215 #define CIAP(va) ((int)(va)-(int)ciabase+CIABASE) 216 #define CIAPOFF(pa) ((int)(pa)-CIABASE) 217 #define CIAMAPSIZE btoc(CIATOP-CIABASE) /* 8k */ 218 219 #define ISCUSTOMCHIP(va) \ 220 ((char *)(va) >= customchipbase && (char *)(va) < customchiplimit) 221 #define CUSTOMCHIPV(pa) ((int)(pa)-CUSTOMCHIPBASE+(int)customchipbase) 222 #define CUSTOMCHIPP(va) ((int)(va)-(int)customchipbase+CUSTOMCHIPBASE) 223 #define CUSTOMCHIPPOFF(pa) ((int)(pa)-CUSTOMCHIPBASE) 224 #define CUSTOMCHIPMAPSIZE btoc(CUSTOMCHIPTOP-CUSTOMCHIPBASE) /* 1.5mb */ 225 #endif 226 227 228 /* 229 * 68851 and 68030 MMU 230 */ 231 #define PMMU_LVLMASK 0x0007 232 #define PMMU_INV 0x0400 233 #define PMMU_WP 0x0800 234 #define PMMU_ALV 0x1000 235 #define PMMU_SO 0x2000 236 #define PMMU_LV 0x4000 237 #define PMMU_BE 0x8000 238 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 239 240 /* 680X0 function codes */ 241 #define FC_USERD 1 /* user data space */ 242 #define FC_USERP 2 /* user program space */ 243 #define FC_SUPERD 5 /* supervisor data space */ 244 #define FC_SUPERP 6 /* supervisor program space */ 245 #define FC_CPU 7 /* CPU space */ 246 247 /* fields in the 68020 cache control register */ 248 #define IC_ENABLE 0x0001 /* enable instruction cache */ 249 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 250 #define IC_CE 0x0004 /* clear instruction cache entry */ 251 #define IC_CLR 0x0008 /* clear entire instruction cache */ 252 253 /* additional fields in the 68030 cache control register */ 254 #define IC_BE 0x0010 /* instruction burst enable */ 255 #define DC_ENABLE 0x0100 /* data cache enable */ 256 #define DC_FREEZE 0x0200 /* data cache freeze */ 257 #define DC_CE 0x0400 /* clear data cache entry */ 258 #define DC_CLR 0x0800 /* clear entire data cache */ 259 #define DC_BE 0x1000 /* data burst enable */ 260 #define DC_WA 0x2000 /* write allocate */ 261 262 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 263 #define CACHE_OFF (DC_CLR|IC_CLR) 264 #define CACHE_CLR (CACHE_ON) 265 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 266 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 267