1 /* $NetBSD: sbic.c,v 1.11 1995/03/02 02:24:06 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 /* need to know if any tapes have been configured */ 47 #include "st.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/disklabel.h> 53 #include <sys/dkstat.h> 54 #include <sys/buf.h> 55 #include <scsi/scsi_all.h> 56 #include <scsi/scsiconf.h> 57 #include <vm/vm.h> 58 #include <vm/vm_kern.h> 59 #include <vm/vm_page.h> 60 #include <machine/pmap.h> 61 #include <machine/cpu.h> 62 #include <amiga/amiga/device.h> 63 #include <amiga/amiga/custom.h> 64 #include <amiga/amiga/isr.h> 65 #include <amiga/dev/dmavar.h> 66 #include <amiga/dev/sbicreg.h> 67 #include <amiga/dev/sbicvar.h> 68 69 /* 70 * SCSI delays 71 * In u-seconds, primarily for state changes on the SPC. 72 */ 73 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 74 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 75 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 76 77 #define b_cylin b_resid 78 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 79 80 extern u_int kvtop(); 81 82 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int,u_char)); 83 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 84 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 85 int sbicgetsense __P((struct sbic_softc *, struct scsi_xfer *)); 86 int sbicwait __P((sbic_regmap_p, char, int , int)); 87 int sbiccheckdmap __P((void *, u_long, u_long)); 88 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_p, u_char, u_char, u_char)); 89 int sbicxfstart __P((sbic_regmap_p, int, u_char, int)); 90 int sbicxfout __P((sbic_regmap_p regs, int, void *, int)); 91 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 92 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_p, int)); 93 int sbicintr __P((struct sbic_softc *)); 94 void sbicxfin __P((sbic_regmap_p regs, int, void *)); 95 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_p, int)); 96 void sbicabort __P((struct sbic_softc *, sbic_regmap_p, char *)); 97 void sbicerror __P((struct sbic_softc *, sbic_regmap_p, u_char)); 98 void sbicstart __P((struct sbic_softc *)); 99 void sbicreset __P((struct sbic_softc *)); 100 void sbicsetdelay __P((int)); 101 void sbic_scsidone __P((struct sbic_softc *, int)); 102 void sbic_donextcmd __P((struct sbic_softc *)); 103 104 /* 105 * Synch xfer parameters, and timing conversions 106 */ 107 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 108 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 109 110 int sbic_cmd_wait = SBIC_CMD_WAIT; 111 int sbic_data_wait = SBIC_DATA_WAIT; 112 int sbic_init_wait = SBIC_INIT_WAIT; 113 114 /* 115 * was broken before.. now if you want this you get it for all drives 116 * on sbic controllers. 117 */ 118 int sbic_inhibit_sync = 0; 119 int sbic_clock_override = 0; 120 int sbic_no_dma = 0; 121 122 #ifdef DEBUG 123 int sbicdma_ops = 0; /* total DMA operations */ 124 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 125 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 126 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 127 #define QPRINTF(a) if (sbic_debug > 1) printf a 128 int sbic_debug = 0; 129 int sync_debug = 0; 130 int sbic_dma_debug = 0; 131 #else 132 #define QPRINTF 133 #endif 134 135 /* 136 * default minphys routine for sbic based controllers 137 */ 138 void 139 sbic_minphys(bp) 140 struct buf *bp; 141 { 142 /* 143 * no max transfer at this level 144 */ 145 } 146 147 /* 148 * used by specific sbic controller 149 * 150 * it appears that the higher level code does nothing with LUN's 151 * so I will too. I could plug it in, however so could they 152 * in scsi_scsi_cmd(). 153 */ 154 int 155 sbic_scsicmd(xs) 156 struct scsi_xfer *xs; 157 { 158 struct sbic_pending *pendp; 159 struct sbic_softc *dev; 160 struct scsi_link *slp; 161 int flags, s; 162 163 slp = xs->sc_link; 164 dev = slp->adapter_softc; 165 flags = xs->flags; 166 167 if (flags & SCSI_DATA_UIO) 168 panic("sbic: scsi data uio requested"); 169 170 if (dev->sc_xs && flags & SCSI_POLL) 171 panic("sbic_scsicmd: busy"); 172 173 s = splbio(); 174 pendp = &dev->sc_xsstore[slp->target][slp->lun]; 175 if (pendp->xs) { 176 splx(s); 177 return(TRY_AGAIN_LATER); 178 } 179 180 if (dev->sc_xs) { 181 pendp->xs = xs; 182 TAILQ_INSERT_TAIL(&dev->sc_xslist, pendp, link); 183 splx(s); 184 return(SUCCESSFULLY_QUEUED); 185 } 186 pendp->xs = NULL; 187 dev->sc_xs = xs; 188 splx(s); 189 190 /* 191 * nothing is pending do it now. 192 */ 193 sbic_donextcmd(dev); 194 195 if (flags & SCSI_POLL) 196 return(COMPLETE); 197 return(SUCCESSFULLY_QUEUED); 198 } 199 200 /* 201 * entered with dev->sc_xs pointing to the next xfer to perform 202 */ 203 void 204 sbic_donextcmd(dev) 205 struct sbic_softc *dev; 206 { 207 struct scsi_xfer *xs; 208 struct scsi_link *slp; 209 int flags, phase, stat; 210 211 xs = dev->sc_xs; 212 slp = xs->sc_link; 213 flags = xs->flags; 214 215 if (flags & SCSI_DATA_IN) 216 phase = DATA_IN_PHASE; 217 else if (flags & SCSI_DATA_OUT) 218 phase = DATA_OUT_PHASE; 219 else 220 phase = STATUS_PHASE; 221 222 if (flags & SCSI_RESET) 223 sbicreset(dev); 224 225 dev->sc_stat[0] = -1; 226 xs->cmd->bytes[0] |= slp->lun << 5; 227 if (phase == STATUS_PHASE || flags & SCSI_POLL || 228 sbicdmaok(dev, xs) == 0) 229 stat = sbicicmd(dev, slp->target, slp->lun, xs->cmd, 230 xs->cmdlen, xs->data, xs->datalen, phase); 231 else if (sbicgo(dev, xs) == 0) 232 return; 233 else 234 stat = dev->sc_stat[0]; 235 236 sbic_scsidone(dev, stat); 237 } 238 239 void 240 sbic_scsidone(dev, stat) 241 struct sbic_softc *dev; 242 int stat; 243 { 244 struct sbic_pending *pendp; 245 struct scsi_xfer *xs; 246 int s, donext; 247 248 xs = dev->sc_xs; 249 #ifdef DIAGNOSTIC 250 if (xs == NULL) 251 panic("sbic_scsidone"); 252 #endif 253 #if 1 254 if (((struct device *)(xs->sc_link->device_softc))->dv_unit < dk_ndrive) 255 ++dk_xfer[((struct device *)(xs->sc_link->device_softc))->dv_unit]; 256 #endif 257 /* 258 * is this right? 259 */ 260 xs->status = stat; 261 262 if (stat == 0) 263 xs->resid = 0; 264 else { 265 switch(stat) { 266 case SCSI_CHECK: 267 if (stat = sbicgetsense(dev, xs)) 268 goto bad_sense; 269 xs->error = XS_SENSE; 270 break; 271 case SCSI_BUSY: 272 xs->error = XS_BUSY; 273 break; 274 bad_sense: 275 default: 276 xs->error = XS_DRIVER_STUFFUP; 277 QPRINTF(("sbic_scsicmd() bad %x\n", stat)); 278 break; 279 } 280 } 281 xs->flags |= ITSDONE; 282 283 /* 284 * grab next command before scsi_done() 285 * this way no single device can hog scsi resources. 286 */ 287 s = splbio(); 288 pendp = dev->sc_xslist.tqh_first; 289 if (pendp == NULL) { 290 donext = 0; 291 dev->sc_xs = NULL; 292 } else { 293 donext = 1; 294 TAILQ_REMOVE(&dev->sc_xslist, pendp, link); 295 dev->sc_xs = pendp->xs; 296 pendp->xs = NULL; 297 } 298 splx(s); 299 scsi_done(xs); 300 301 if (donext) 302 sbic_donextcmd(dev); 303 } 304 305 int 306 sbicgetsense(dev, xs) 307 struct sbic_softc *dev; 308 struct scsi_xfer *xs; 309 { 310 struct scsi_sense rqs; 311 struct scsi_link *slp; 312 int stat; 313 314 slp = xs->sc_link; 315 316 rqs.opcode = REQUEST_SENSE; 317 rqs.byte2 = slp->lun << 5; 318 #ifdef not_yet 319 rqs.length = xs->req_sense_length ? xs->req_sense_length : 320 sizeof(xs->sense); 321 #else 322 rqs.length = sizeof(xs->sense); 323 #endif 324 325 rqs.unused[0] = rqs.unused[1] = rqs.control = 0; 326 327 return(sbicicmd(dev, slp->target, slp->lun, &rqs, sizeof(rqs), 328 &xs->sense, rqs.length, DATA_IN_PHASE)); 329 } 330 331 int 332 sbicdmaok(dev, xs) 333 struct sbic_softc *dev; 334 struct scsi_xfer *xs; 335 { 336 if (sbic_no_dma || xs->datalen & 0x1 || (u_int)xs->data & 0x3) 337 return(0); 338 /* 339 * controller supports dma to any addresses? 340 */ 341 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 342 return(1); 343 /* 344 * this address is ok for dma? 345 */ 346 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 347 return(1); 348 /* 349 * we have a bounce buffer? 350 */ 351 else if (dev->sc_dmabuffer) 352 return(1); 353 return(0); 354 } 355 356 357 int 358 sbicwait(regs, until, timeo, line) 359 sbic_regmap_p regs; 360 char until; 361 int timeo; 362 int line; 363 { 364 u_char val; 365 int csr; 366 367 if (timeo == 0) 368 timeo = 1000000; /* some large value.. */ 369 370 GET_SBIC_asr(regs,val); 371 while ((val & until) == 0) { 372 if (timeo-- == 0) { 373 GET_SBIC_csr(regs, csr); 374 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 375 line, val, csr); 376 break; 377 } 378 DELAY(1); 379 GET_SBIC_asr(regs,val); 380 } 381 return(val); 382 } 383 384 void 385 sbicabort(dev, regs, where) 386 struct sbic_softc *dev; 387 sbic_regmap_p regs; 388 char *where; 389 { 390 u_char csr, asr; 391 392 GET_SBIC_csr(regs, csr); 393 GET_SBIC_asr(regs, asr); 394 395 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 396 dev->sc_dev.dv_xname, where, csr, asr); 397 398 if (dev->sc_flags & SBICF_SELECTED) { 399 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 400 WAIT_CIP(regs); 401 402 GET_SBIC_asr(regs, asr); 403 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 404 /* ok, get more drastic.. */ 405 406 SET_SBIC_cmd (regs, SBIC_CMD_RESET); 407 DELAY(25); 408 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 409 /* clears interrupt also */ 410 GET_SBIC_csr (regs, csr); 411 412 dev->sc_flags &= ~SBICF_SELECTED; 413 return; 414 } 415 416 do { 417 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 418 GET_SBIC_csr (regs, csr); 419 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 420 && (csr != SBIC_CSR_CMD_INVALID)); 421 422 /* lets just hope it worked.. */ 423 dev->sc_flags &= ~SBICF_SELECTED; 424 } 425 } 426 427 /* 428 * XXX Set/reset long delays. 429 * 430 * if delay == 0, reset default delays 431 * if delay < 0, set both delays to default long initialization values 432 * if delay > 0, set both delays to this value 433 * 434 * Used when a devices is expected to respond slowly (e.g. during 435 * initialization). 436 */ 437 void 438 sbicsetdelay(del) 439 int del; 440 { 441 static int saved_cmd_wait, saved_data_wait; 442 443 if (del) { 444 saved_cmd_wait = sbic_cmd_wait; 445 saved_data_wait = sbic_data_wait; 446 if (del > 0) 447 sbic_cmd_wait = sbic_data_wait = del; 448 else 449 sbic_cmd_wait = sbic_data_wait = sbic_init_wait; 450 } else { 451 sbic_cmd_wait = saved_cmd_wait; 452 sbic_data_wait = saved_data_wait; 453 } 454 } 455 456 void 457 sbicreset(dev) 458 struct sbic_softc *dev; 459 { 460 sbic_regmap_p regs; 461 u_int i, s; 462 u_char my_id, csr; 463 464 regs = dev->sc_sbicp; 465 466 if (dev->sc_flags & SBICF_ALIVE) 467 sbicabort(dev, regs, "reset"); 468 469 s = splbio(); 470 /* preserve our ID for now */ 471 GET_SBIC_myid (regs, my_id); 472 my_id &= SBIC_ID_MASK; 473 474 if (dev->sc_clkfreq < 110) 475 my_id |= SBIC_ID_FS_8_10; 476 else if (dev->sc_clkfreq < 160) 477 my_id |= SBIC_ID_FS_12_15; 478 else if (dev->sc_clkfreq < 210) 479 my_id |= SBIC_ID_FS_16_20; 480 481 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 482 483 SET_SBIC_myid(regs, my_id); 484 485 /* 486 * Disable interrupts (in dmainit) then reset the chip 487 */ 488 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 489 DELAY(25); 490 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 491 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 492 493 /* 494 * Set up various chip parameters 495 */ 496 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI 497 | SBIC_MACHINE_DMA_MODE); 498 /* 499 * don't allow (re)selection (SBIC_RID_ES) 500 * until we can handle target mode!! 501 */ 502 SET_SBIC_rselid(regs, 0); 503 SET_SBIC_syn(regs, 0); /* asynch for now */ 504 505 /* 506 * anything else was zeroed by reset 507 */ 508 splx(s); 509 510 dev->sc_flags |= SBICF_ALIVE; 511 dev->sc_flags &= ~SBICF_SELECTED; 512 } 513 514 void 515 sbicerror(dev, regs, csr) 516 struct sbic_softc *dev; 517 sbic_regmap_p regs; 518 u_char csr; 519 { 520 struct scsi_xfer *xs; 521 522 xs = dev->sc_xs; 523 524 #ifdef DIAGNOSTIC 525 if (xs == NULL) 526 panic("sbicerror"); 527 #endif 528 if (xs->flags & SCSI_SILENT) 529 return; 530 531 printf("%s: ", dev->sc_dev.dv_xname); 532 printf("csr == 0x%02i\n", csr); /* XXX */ 533 } 534 535 /* 536 * select the bus, return when selected or error. 537 */ 538 int 539 sbicselectbus(dev, regs, target, lun, our_addr) 540 struct sbic_softc *dev; 541 sbic_regmap_p regs; 542 u_char target, lun, our_addr; 543 { 544 u_char asr, csr, id; 545 546 QPRINTF(("sbicselectbus %d\n", target)); 547 548 /* 549 * if we're already selected, return (XXXX panic maybe?) 550 */ 551 if (dev->sc_flags & SBICF_SELECTED) 552 return(1); 553 554 /* 555 * issue select 556 */ 557 SBIC_TC_PUT(regs, 0); 558 SET_SBIC_selid(regs, target); 559 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 560 561 /* 562 * set sync or async 563 */ 564 if (dev->sc_sync[target].state == SYNC_DONE) 565 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 566 dev->sc_sync[target].period)); 567 else 568 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 569 570 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 571 572 /* 573 * wait for select (merged from seperate function may need 574 * cleanup) 575 */ 576 WAIT_CIP(regs); 577 do { 578 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 579 GET_SBIC_csr (regs, csr); 580 QPRINTF(("%02x ", csr)); 581 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 582 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 583 584 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) 585 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 586 else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 587 /* 588 * Send identify message 589 * (SCSI-2 requires an identify msg (?)) 590 */ 591 GET_SBIC_selid(regs, id); 592 593 /* 594 * handle drives that don't want to be asked 595 * whether to go sync at all. 596 */ 597 if (sbic_inhibit_sync && dev->sc_sync[id].state == SYNC_START) { 598 #ifdef DEBUG 599 if (sync_debug) 600 printf("Forcing target %d asynchronous.\n", id); 601 #endif 602 dev->sc_sync[id].offset = 0; 603 dev->sc_sync[id].period = sbic_min_period; 604 dev->sc_sync[id].state = SYNC_DONE; 605 } 606 607 608 if (dev->sc_sync[id].state != SYNC_START) 609 SEND_BYTE (regs, MSG_IDENTIFY | lun); 610 else { 611 /* 612 * try to initiate a sync transfer. 613 * So compose the sync message we're going 614 * to send to the target 615 */ 616 617 #ifdef DEBUG 618 if (sync_debug) 619 printf("Sending sync request to target %d ... ", 620 id); 621 #endif 622 /* 623 * setup scsi message sync message request 624 */ 625 dev->sc_msg[0] = MSG_IDENTIFY | lun; 626 dev->sc_msg[1] = MSG_EXT_MESSAGE; 627 dev->sc_msg[2] = 3; 628 dev->sc_msg[3] = MSG_SYNC_REQ; 629 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 630 sbic_min_period); 631 dev->sc_msg[5] = sbic_max_offset; 632 633 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 634 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 635 636 dev->sc_sync[id].state = SYNC_SENT; 637 #ifdef DEBUG 638 if (sync_debug) 639 printf ("sent\n"); 640 #endif 641 } 642 643 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 644 GET_SBIC_csr (regs, csr); 645 QPRINTF(("[%02x]", csr)); 646 #ifdef DEBUG 647 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 648 printf("csr-result of last msgout: 0x%x\n", csr); 649 #endif 650 651 if (csr != SBIC_CSR_SEL_TIMEO) 652 dev->sc_flags |= SBICF_SELECTED; 653 } 654 655 QPRINTF(("\n")); 656 657 return(csr == SBIC_CSR_SEL_TIMEO); 658 } 659 660 int 661 sbicxfstart(regs, len, phase, wait) 662 sbic_regmap_p regs; 663 int len, wait; 664 u_char phase; 665 { 666 u_char id; 667 668 if (phase == DATA_IN_PHASE || phase == MESG_IN_PHASE) { 669 GET_SBIC_selid (regs, id); 670 id |= SBIC_SID_FROM_SCSI; 671 SET_SBIC_selid (regs, id); 672 SBIC_TC_PUT (regs, (unsigned)len); 673 } else if (phase == DATA_OUT_PHASE || phase == MESG_OUT_PHASE 674 || phase == CMD_PHASE) 675 SBIC_TC_PUT (regs, (unsigned)len); 676 else 677 SBIC_TC_PUT (regs, 0); 678 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 679 680 return(1); 681 } 682 683 int 684 sbicxfout(regs, len, bp, phase) 685 sbic_regmap_p regs; 686 int len; 687 void *bp; 688 int phase; 689 { 690 u_char orig_csr, csr, asr, *buf; 691 int wait; 692 693 buf = bp; 694 wait = sbic_data_wait; 695 696 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 697 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 698 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 699 700 GET_SBIC_csr (regs, orig_csr); 701 702 /* 703 * sigh.. WD-PROTO strikes again.. sending the command in one go 704 * causes the chip to lock up if talking to certain (misbehaving?) 705 * targets. Anyway, this procedure should work for all targets, but 706 * it's slightly slower due to the overhead 707 */ 708 WAIT_CIP (regs); 709 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 710 for (;len > 0; len--) { 711 GET_SBIC_asr (regs, asr); 712 while ((asr & SBIC_ASR_DBR) == 0) { 713 if ((asr & SBIC_ASR_INT) || --wait < 0) { 714 #ifdef DEBUG 715 if (sbic_debug) 716 printf("sbicxfout fail: l%d i%x w%d\n", 717 len, asr, wait); 718 #endif 719 return (len); 720 } 721 DELAY(1); 722 GET_SBIC_asr (regs, asr); 723 } 724 725 SET_SBIC_data (regs, *buf); 726 buf++; 727 } 728 729 QPRINTF(("sbicxfout done\n")); 730 /* 731 * this leaves with one csr to be read 732 */ 733 return(0); 734 } 735 736 void 737 sbicxfin(regs, len, bp) 738 sbic_regmap_p regs; 739 int len; 740 void *bp; 741 { 742 int wait; 743 u_char *obp, *buf; 744 u_char orig_csr, csr, asr; 745 746 wait = sbic_data_wait; 747 obp = bp; 748 buf = bp; 749 750 GET_SBIC_csr (regs, orig_csr); 751 752 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 753 754 WAIT_CIP (regs); 755 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 756 for (;len > 0; len--) { 757 GET_SBIC_asr (regs, asr); 758 while ((asr & SBIC_ASR_DBR) == 0) { 759 if ((asr & SBIC_ASR_INT) || --wait < 0) { 760 #ifdef DEBUG 761 if (sbic_debug) 762 printf("sbicxfin fail: l%d i%x w%d\n", 763 len, asr, wait); 764 #endif 765 return; 766 } 767 768 DELAY(1); 769 GET_SBIC_asr (regs, asr); 770 } 771 772 GET_SBIC_data (regs, *buf); 773 buf++; 774 } 775 776 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 777 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 778 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 779 780 /* this leaves with one csr to be read */ 781 } 782 783 784 /* 785 * SCSI 'immediate' command: issue a command to some SCSI device 786 * and get back an 'immediate' response (i.e., do programmed xfer 787 * to get the response data). 'cbuf' is a buffer containing a scsi 788 * command of length clen bytes. 'buf' is a buffer of length 'len' 789 * bytes for data. The transfer direction is determined by the device 790 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 791 * command must supply no data. 'xferphase' is the bus phase the 792 * caller expects to happen after the command is issued. It should 793 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 794 */ 795 int 796 sbicicmd(dev, target, lun, cbuf, clen, buf, len, xferphase) 797 struct sbic_softc *dev; 798 void *cbuf, *buf; 799 int clen, len; 800 u_char xferphase; 801 { 802 sbic_regmap_p regs; 803 u_char phase, csr, asr; 804 int wait; 805 806 regs = dev->sc_sbicp; 807 808 /* 809 * set the sbic into non-DMA mode 810 */ 811 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 812 813 retry_selection: 814 /* 815 * select the SCSI bus (it's an error if bus isn't free) 816 */ 817 if (sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) 818 return(-1); 819 /* 820 * Wait for a phase change (or error) then let the device sequence 821 * us through the various SCSI phases. 822 */ 823 dev->sc_stat[0] = 0xff; 824 dev->sc_msg[0] = 0xff; 825 phase = CMD_PHASE; 826 827 new_phase: 828 wait = sbic_cmd_wait; 829 830 GET_SBIC_csr (regs, csr); 831 QPRINTF((">CSR:%02x<", csr)); 832 833 /* 834 * requesting some new phase 835 */ 836 if ((csr != 0xff) && (csr & 0xf0) && (csr & 0x08)) 837 phase = csr & PHASE; 838 else if ((csr == SBIC_CSR_DISC) || (csr == SBIC_CSR_DISC_1) 839 || (csr == SBIC_CSR_S_XFERRED)) { 840 dev->sc_flags &= ~SBICF_SELECTED; 841 GET_SBIC_cmd_phase (regs, phase); 842 if (phase == 0x60) 843 GET_SBIC_tlun (regs, dev->sc_stat[0]); 844 else 845 return(-1); 846 goto out; 847 } else { 848 sbicerror(dev, regs, csr); 849 goto abort; 850 } 851 852 switch (phase) { 853 case CMD_PHASE: 854 if (sbicxfstart (regs, clen, phase, wait)) 855 if (sbicxfout (regs, clen, cbuf, phase)) 856 goto abort; 857 phase = xferphase; 858 break; 859 case DATA_IN_PHASE: 860 if (len <= 0) 861 goto abort; 862 wait = sbic_data_wait; 863 if (sbicxfstart(regs, len, phase, wait)) 864 sbicxfin(regs, len, buf); 865 phase = STATUS_PHASE; 866 break; 867 case MESG_IN_PHASE: 868 if (sbicxfstart(regs, sizeof(dev->sc_msg), phase, wait) == 0) 869 break; 870 dev->sc_msg[0] = 0xff; 871 sbicxfin(regs, sizeof(dev->sc_msg), dev->sc_msg); 872 /* 873 * get the command completion interrupt, or we 874 * can't send a new command (LCI) 875 */ 876 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 877 GET_SBIC_csr(regs, csr); 878 #ifdef DEBUG 879 if (sync_debug) 880 printf("msgin done csr 0x%x\n", csr); 881 #endif 882 /* 883 * test whether this is a reply to our sync 884 * request 885 */ 886 if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 887 && dev->sc_msg[2] == MSG_SYNC_REQ) { 888 889 dev->sc_sync[target].period = sbicfromscsiperiod(dev, 890 regs, dev->sc_msg[3]); 891 dev->sc_sync[target].offset = dev->sc_msg[4]; 892 dev->sc_sync[target].state = SYNC_DONE; 893 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 894 dev->sc_sync[target].period)); 895 /* ACK the message */ 896 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 897 WAIT_CIP(regs); 898 phase = CMD_PHASE; /* or whatever */ 899 printf("%s: target %d now synchronous," 900 " period=%dns, offset=%d.\n", 901 dev->sc_dev.dv_xname, target, dev->sc_msg[3] * 4, 902 dev->sc_msg[4]); 903 } else if (dev->sc_msg[0] == MSG_REJECT 904 && dev->sc_sync[target].state == SYNC_SENT) { 905 #ifdef DEBUG 906 if (sync_debug) 907 printf("target %d rejected sync, going async\n", 908 target); 909 #endif 910 dev->sc_sync[target].period = sbic_min_period; 911 dev->sc_sync[target].offset = 0; 912 dev->sc_sync[target].state = SYNC_DONE; 913 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 914 dev->sc_sync[target].period)); 915 /* ACK the message */ 916 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 917 WAIT_CIP(regs); 918 phase = CMD_PHASE; /* or whatever */ 919 } else if (dev->sc_msg[0] == MSG_REJECT) { 920 /* 921 * we'll never REJECt a REJECT message.. 922 */ 923 /* ACK the message */ 924 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 925 WAIT_CIP(regs); 926 phase = CMD_PHASE; /* or whatever */ 927 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE 928 || dev->sc_msg[0] == 0xff) { 929 /* !! KLUDGE ALERT !! quite a few drives don't seem to 930 * really like the current way of sending the 931 * sync-handshake together with the ident-message, and 932 * they react by sending command-complete and 933 * disconnecting right after returning the valid sync 934 * handshake. So, all I can do is reselect the drive, 935 * and hope it won't disconnect again. I don't think 936 * this is valid behavior, but I can't help fixing a 937 * problem that apparently exists. 938 * 939 * Note: we should not get here on `normal' command 940 * completion, as that condition is handled by the 941 * high-level sel&xfer resume command used to walk 942 * thru status/cc-phase. 943 */ 944 945 #ifdef DEBUG 946 if (sync_debug) 947 printf ("GOT CMD-COMPLETE! %d acting weird.." 948 " waiting for disconnect...\n", target); 949 #endif 950 /* ACK the message */ 951 SET_SBIC_cmd (regs, SBIC_CMD_CLR_ACK); 952 WAIT_CIP(regs); 953 954 /* wait for disconnect */ 955 while (csr != SBIC_CSR_DISC && 956 csr != SBIC_CSR_DISC_1) { 957 DELAY(1); 958 GET_SBIC_csr(regs, csr); 959 } 960 #ifdef DEBUG 961 if (sync_debug) 962 printf ("ok.\nRetrying selection.\n"); 963 #endif 964 dev->sc_flags &= ~SBICF_SELECTED; 965 goto retry_selection; 966 } else { 967 #ifdef DEBUG 968 if (sbic_debug || sync_debug) 969 printf ("Rejecting message 0x%02x\n", 970 dev->sc_msg[0]); 971 #endif 972 /* prepare to reject the message, NACK */ 973 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 974 WAIT_CIP(regs); 975 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 976 WAIT_CIP(regs); 977 phase = MESG_OUT_PHASE; 978 } 979 break; 980 981 case MESG_OUT_PHASE: 982 #ifdef DEBUG 983 if (sync_debug) 984 printf ("sending REJECT msg to last msg.\n"); 985 #endif 986 /* 987 * should only get here on reject, 988 * since it's always US that 989 * initiate a sync transfer 990 */ 991 SEND_BYTE(regs, MSG_REJECT); 992 phase = STATUS_PHASE; 993 break; 994 case DATA_OUT_PHASE: 995 if (len <= 0) 996 goto abort; 997 wait = sbic_data_wait; 998 if (sbicxfstart(regs, len, phase, wait)) 999 if (sbicxfout (regs, len, buf, phase)) 1000 goto abort; 1001 phase = STATUS_PHASE; 1002 break; 1003 case STATUS_PHASE: 1004 /* 1005 * the sbic does the status/cmd-complete reading ok, 1006 * so do this with its hi-level commands. 1007 */ 1008 SBIC_TC_PUT(regs, 0); 1009 SET_SBIC_cmd_phase(regs, 0x46); 1010 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1011 phase = BUS_FREE_PHASE; 1012 break; 1013 case BUS_FREE_PHASE: 1014 goto out; 1015 default: 1016 printf("%s: unexpected phase %d in icmd from %d\n", 1017 dev->sc_dev.dv_xname, phase, target); 1018 goto abort; 1019 } 1020 1021 /* 1022 * make sure the last command was taken, 1023 * ie. we're not hunting after an ignored command.. 1024 */ 1025 GET_SBIC_asr(regs, asr); 1026 if (asr & SBIC_ASR_LCI) 1027 goto abort; 1028 1029 /* tapes may take a loooong time.. */ 1030 while (asr & SBIC_ASR_BSY) { 1031 DELAY(1); 1032 GET_SBIC_asr(regs, asr); 1033 } 1034 1035 /* 1036 * wait for last command to complete 1037 */ 1038 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1039 1040 /* 1041 * do it again 1042 */ 1043 goto new_phase; 1044 abort: 1045 sbicabort(dev, regs, "icmd"); 1046 out: 1047 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1048 return(dev->sc_stat[0]); 1049 } 1050 1051 /* 1052 * Finish SCSI xfer command: After the completion interrupt from 1053 * a read/write operation, sequence through the final phases in 1054 * programmed i/o. This routine is a lot like sbicicmd except we 1055 * skip (and don't allow) the select, cmd out and data in/out phases. 1056 */ 1057 void 1058 sbicxfdone(dev, regs, target) 1059 struct sbic_softc *dev; 1060 sbic_regmap_p regs; 1061 int target; 1062 { 1063 u_char phase, csr; 1064 int s; 1065 1066 QPRINTF(("{")); 1067 s = splbio(); 1068 1069 /* 1070 * have the sbic complete on its own 1071 */ 1072 SBIC_TC_PUT(regs, 0); 1073 SET_SBIC_cmd_phase(regs, 0x46); 1074 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1075 1076 do { 1077 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1078 GET_SBIC_csr (regs, csr); 1079 QPRINTF(("%02x:", csr)); 1080 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1081 && (csr != SBIC_CSR_S_XFERRED)); 1082 1083 dev->sc_flags &= ~SBICF_SELECTED; 1084 1085 GET_SBIC_cmd_phase (regs, phase); 1086 QPRINTF(("}%02x", phase)); 1087 if (phase == 0x60) 1088 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1089 else 1090 sbicerror(dev, regs, csr); 1091 1092 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1093 splx(s); 1094 } 1095 1096 int 1097 sbicgo(dev, xs) 1098 struct sbic_softc *dev; 1099 struct scsi_xfer *xs; 1100 { 1101 int i, dmaflags, count, tcount, target, len, wait; 1102 u_char phase, csr, asr, cmd, *addr, *tmpaddr; 1103 sbic_regmap_p regs; 1104 struct dma_chain *dcp; 1105 u_int deoff, dspa; 1106 char *dmaend; 1107 1108 target = xs->sc_link->target; 1109 count = xs->datalen; 1110 addr = xs->data; 1111 1112 regs = dev->sc_sbicp; 1113 dmaend = NULL; 1114 1115 /* 1116 * set the sbic into DMA mode 1117 */ 1118 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1119 SBIC_MACHINE_DMA_MODE); 1120 1121 /* 1122 * select the SCSI bus (it's an error if bus isn't free) 1123 */ 1124 if (sbicselectbus(dev, regs, target, xs->sc_link->lun, 1125 dev->sc_scsiaddr)) { 1126 dev->sc_dmafree(dev); 1127 return(-1); 1128 } 1129 1130 /* 1131 * Wait for a phase change (or error) then let the device 1132 * sequence us through command phase (we may have to take 1133 * a msg in/out before doing the command). If the disk has 1134 * to do a seek, it may be a long time until we get a change 1135 * to data phase so, in the absense of an explicit phase 1136 * change, we assume data phase will be coming up and tell 1137 * the SPC to start a transfer whenever it does. We'll get 1138 * a service required interrupt later if this assumption is 1139 * wrong. Otherwise we'll get a service required int when 1140 * the transfer changes to status phase. 1141 */ 1142 phase = CMD_PHASE; 1143 1144 new_phase: 1145 wait = sbic_cmd_wait; 1146 switch (phase) { 1147 case CMD_PHASE: 1148 if (sbicxfstart(regs, xs->cmdlen, phase, wait)) 1149 if (sbicxfout(regs, xs->cmdlen, xs->cmd, phase)) 1150 goto abort; 1151 break; 1152 case MESG_IN_PHASE: 1153 if (sbicxfstart(regs, sizeof(dev->sc_msg), phase, wait) == 0) 1154 break; 1155 1156 sbicxfin(regs, sizeof(dev->sc_msg), dev->sc_msg); 1157 /* 1158 * prepare to reject any mesgin, 1159 * no matter what it might be.. 1160 */ 1161 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1162 WAIT_CIP(regs); 1163 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1164 phase = MESG_OUT_PHASE; 1165 break; 1166 case MESG_OUT_PHASE: 1167 SEND_BYTE(regs, MSG_REJECT); 1168 phase = STATUS_PHASE; 1169 break; 1170 case DATA_IN_PHASE: 1171 case DATA_OUT_PHASE: 1172 goto out; 1173 /* 1174 * status phase can happen, if the issued read/write command 1175 * is illegal (for example, reading after EOT on tape) and the 1176 * device doesn't even go to data in/out phase. So handle this 1177 * here normally, instead of going thru abort-handling. 1178 */ 1179 case STATUS_PHASE: 1180 dev->sc_dmafree(dev); 1181 sbicxfdone(dev, regs, target); 1182 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF); 1183 sbic_scsidone(dev, dev->sc_stat[0]); 1184 return(0); 1185 default: 1186 printf("%s: unexpected phase %d in go from %d\n", phase, 1187 dev->sc_dev.dv_xname, target); 1188 goto abort; 1189 } 1190 1191 /* 1192 * make sure the last command was taken, 1193 * ie. we're not hunting after an ignored command.. 1194 */ 1195 GET_SBIC_asr(regs, asr); 1196 if (asr & SBIC_ASR_LCI) 1197 goto abort; 1198 1199 /* 1200 * tapes may take a loooong time.. 1201 */ 1202 while (asr & SBIC_ASR_BSY) { 1203 DELAY(1); 1204 GET_SBIC_asr(regs, asr); 1205 } 1206 1207 if (wait <= 0) 1208 goto abort; 1209 1210 /* 1211 * wait for last command to complete 1212 */ 1213 SBIC_WAIT(regs, SBIC_ASR_INT, wait); 1214 1215 GET_SBIC_csr(regs, csr); 1216 QPRINTF((">CSR:%02x<", csr)); 1217 1218 /* 1219 * requesting some new phase 1220 */ 1221 if ((csr != 0xff) && (csr & 0xf0) && (csr & 0x08)) 1222 phase = csr & PHASE; 1223 else { 1224 sbicerror(dev, regs, csr); 1225 goto abort; 1226 } 1227 /* 1228 * start again with for new phase 1229 */ 1230 goto new_phase; 1231 out: 1232 dmaflags = 0; 1233 if (xs->flags & SCSI_DATA_IN) 1234 dmaflags |= DMAGO_READ; 1235 1236 if (count > MAXPHYS) 1237 printf("sbicgo: bp->b_bcount > MAXPHYS %08x\n", count); 1238 1239 #ifdef DEBUG 1240 ++sbicdma_ops; /* count total DMA operations */ 1241 #endif 1242 if (dev->sc_flags & SBICF_BADDMA && 1243 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1244 /* 1245 * need to bounce the dma. 1246 */ 1247 if (dmaflags & DMAGO_READ) { 1248 dev->sc_flags |= SBICF_BBUF; 1249 dev->sc_dmausrbuf = addr; 1250 dev->sc_dmausrlen = count; 1251 } else { /* write: copy to dma buffer */ 1252 bcopy (addr, dev->sc_dmabuffer, count); 1253 } 1254 addr = dev->sc_dmabuffer; /* and use dma buffer */ 1255 #ifdef DEBUG 1256 ++sbicdma_bounces; /* count number of bounced */ 1257 #endif 1258 } 1259 tmpaddr = addr; 1260 len = count; 1261 #ifdef DEBUG 1262 if (sbic_dma_debug & DDB_FOLLOW) 1263 printf("sbicgo(%d, %x, %x, %x)\n", dev->sc_dev.dv_unit, 1264 addr, count, dmaflags); 1265 #endif 1266 /* 1267 * Build the DMA chain 1268 */ 1269 for (dcp = dev->sc_chain; count > 0; dcp++) { 1270 dcp->dc_addr = (char *) kvtop(addr); 1271 if (count < (tcount = NBPG - ((int)addr & PGOFSET))) 1272 tcount = count; 1273 addr += tcount; 1274 count -= tcount; 1275 dcp->dc_count = tcount >> 1; 1276 1277 /* 1278 * check if contigous, if not mark new end 1279 * else increment end and count on previous. 1280 */ 1281 if (dcp->dc_addr != dmaend) { 1282 dmaend = dcp->dc_addr + tcount; 1283 #ifdef DEBUG 1284 if (dcp != dev->sc_chain) 1285 ++sbicdma_misses; /* count non-contiguous */ 1286 #endif 1287 } else { 1288 dcp--; 1289 dmaend += tcount; 1290 dcp->dc_count += tcount >> 1; 1291 #ifdef DEBUG 1292 ++sbicdma_hits; /* count contiguous */ 1293 #endif 1294 } 1295 } 1296 1297 dev->sc_cur = dev->sc_chain; 1298 dev->sc_last = --dcp; 1299 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 1300 1301 #ifdef DEBUG 1302 if (sbic_dma_debug & DDB_IO) { 1303 for (dcp = dev->sc_chain; dcp <= dev->sc_last; dcp++) 1304 printf(" %d: %d@%x\n", dcp-dev->sc_chain, 1305 dcp->dc_count, dcp->dc_addr); 1306 } 1307 #endif 1308 1309 /* 1310 * push the data cash 1311 */ 1312 #if 0 1313 DCIS(); 1314 #elif defined(M68040) 1315 if (cpu040) { 1316 dma_cachectl(tmpaddr, len); 1317 1318 dspa = (u_int)dev->sc_chain[0].dc_addr; 1319 deoff = (u_int)dev->sc_last->dc_addr 1320 + (dev->sc_last->dc_count >> 1); 1321 if ((dspa & 0xF) || (deoff & 0xF)) 1322 dev->sc_flags |= SBICF_DCFLUSH; 1323 } 1324 #endif 1325 1326 /* 1327 * dmago() also enables interrupts for the sbic 1328 */ 1329 i = dev->sc_dmago(dev, addr, xs->datalen, dmaflags); 1330 1331 SBIC_TC_PUT(regs, (unsigned)i); 1332 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 1333 1334 return(0); 1335 1336 abort: 1337 sbicabort(dev, regs, "go"); 1338 dev->sc_dmafree(dev); 1339 return(-1); 1340 } 1341 1342 1343 int 1344 sbicintr(dev) 1345 struct sbic_softc *dev; 1346 { 1347 sbic_regmap_p regs; 1348 struct dma_chain *df, *dl; 1349 u_char asr, csr; 1350 int i; 1351 1352 regs = dev->sc_sbicp; 1353 1354 /* 1355 * pending interrupt? 1356 */ 1357 GET_SBIC_asr (regs, asr); 1358 if ((asr & SBIC_ASR_INT) == 0) 1359 return(0); 1360 1361 GET_SBIC_csr(regs, csr); 1362 QPRINTF(("[0x%x]", csr)); 1363 1364 if (csr == (SBIC_CSR_XFERRED|STATUS_PHASE) 1365 || csr == (SBIC_CSR_MIS|STATUS_PHASE) 1366 || csr == (SBIC_CSR_MIS_1|STATUS_PHASE) 1367 || csr == (SBIC_CSR_MIS_2|STATUS_PHASE)) { 1368 /* 1369 * this should be the normal i/o completion case. 1370 * get the status & cmd complete msg then let the 1371 * device driver look at what happened. 1372 */ 1373 sbicxfdone(dev, regs, dev->sc_xs->sc_link->target); 1374 /* 1375 * check for overlapping cache line, flush if so 1376 */ 1377 #ifdef M68040 1378 if (dev->sc_flags & SBICF_DCFLUSH) { 1379 df = dev->sc_chain; 1380 dl = dev->sc_last; 1381 DCFL(df->dc_addr); 1382 DCFL(dl->dc_addr + (dl->dc_count >> 1)); 1383 } 1384 #endif 1385 dev->sc_dmafree(dev); 1386 if (dev->sc_flags & SBICF_BBUF) { 1387 bcopy(dev->sc_dmabuffer, dev->sc_dmausrbuf, 1388 dev->sc_dmausrlen); 1389 if (dev->sc_dmausrbuf >= (u_char *)0xff000000) 1390 printf("%s: WARNING - dmausrbuf = %x\n", 1391 dev->sc_dev.dv_xname, dev->sc_dmausrbuf); 1392 } 1393 dev->sc_flags &= ~(SBICF_INDMA | SBICF_BBUF | SBICF_DCFLUSH); 1394 sbic_scsidone(dev, dev->sc_stat[0]); 1395 } else if (csr == (SBIC_CSR_XFERRED|DATA_OUT_PHASE) 1396 || csr == (SBIC_CSR_XFERRED|DATA_IN_PHASE) 1397 || csr == (SBIC_CSR_MIS|DATA_OUT_PHASE) 1398 || csr == (SBIC_CSR_MIS|DATA_IN_PHASE) 1399 || csr == (SBIC_CSR_MIS_1|DATA_OUT_PHASE) 1400 || csr == (SBIC_CSR_MIS_1|DATA_IN_PHASE) 1401 || csr == (SBIC_CSR_MIS_2|DATA_OUT_PHASE) 1402 || csr == (SBIC_CSR_MIS_2|DATA_IN_PHASE)) { 1403 /* 1404 * do scatter-gather dma 1405 * hacking the controller chip, ouch.. 1406 */ 1407 /* 1408 * set next dma addr and dec count 1409 */ 1410 dev->sc_cur->dc_addr += dev->sc_tcnt; 1411 dev->sc_cur->dc_count -= (dev->sc_tcnt >> 1); 1412 1413 if (dev->sc_cur->dc_count == 0) 1414 ++dev->sc_cur; /* advance to next segment */ 1415 1416 i = dev->sc_dmanext(dev); 1417 SBIC_TC_PUT(regs, (unsigned)i); 1418 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 1419 } else { 1420 /* 1421 * Something unexpected happened -- deal with it. 1422 */ 1423 dev->sc_dmastop(dev); 1424 sbicerror(dev, regs, csr); 1425 sbicabort(dev, regs, "intr"); 1426 if (dev->sc_flags & SBICF_INDMA) { 1427 /* 1428 * check for overlapping cache line, flush if so 1429 */ 1430 #ifdef M68040 1431 if (dev->sc_flags & SBICF_DCFLUSH) { 1432 df = dev->sc_chain; 1433 dl = dev->sc_last; 1434 DCFL(df->dc_addr); 1435 DCFL(dl->dc_addr + (dl->dc_count >> 1)); 1436 } 1437 #endif 1438 dev->sc_flags &= 1439 ~(SBICF_INDMA | SBICF_BBUF | SBICF_DCFLUSH); 1440 dev->sc_dmafree(dev); 1441 sbic_scsidone(dev, -1); 1442 } 1443 } 1444 return(1); 1445 } 1446 1447 /* 1448 * Check if DMA can not be used with specified buffer 1449 */ 1450 1451 int 1452 sbiccheckdmap(bp, len, mask) 1453 void *bp; 1454 u_long len, mask; 1455 { 1456 u_char *buffer; 1457 u_long phy_buf; 1458 u_long phy_len; 1459 1460 buffer = bp; 1461 1462 if (len == 0) 1463 return(0); 1464 1465 while (len) { 1466 phy_buf = kvtop(buffer); 1467 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 1468 phy_len = len; 1469 if (phy_buf & mask) 1470 return(1); 1471 buffer += phy_len; 1472 len -= phy_len; 1473 } 1474 return(0); 1475 } 1476 1477 int 1478 sbictoscsiperiod(dev, regs, a) 1479 struct sbic_softc *dev; 1480 sbic_regmap_p regs; 1481 int a; 1482 { 1483 unsigned int fs; 1484 1485 /* 1486 * cycle = DIV / (2*CLK) 1487 * DIV = FS+2 1488 * best we can do is 200ns at 20Mhz, 2 cycles 1489 */ 1490 1491 GET_SBIC_myid(regs,fs); 1492 fs = (fs >>6) + 2; /* DIV */ 1493 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 1494 if (a < 2) a = 8; /* map to Cycles */ 1495 return ((fs*a)>>2); /* in 4 ns units */ 1496 } 1497 1498 int 1499 sbicfromscsiperiod(dev, regs, p) 1500 struct sbic_softc *dev; 1501 sbic_regmap_p regs; 1502 int p; 1503 { 1504 register unsigned int fs, ret; 1505 1506 /* Just the inverse of the above */ 1507 1508 GET_SBIC_myid(regs,fs); 1509 fs = (fs >>6) + 2; /* DIV */ 1510 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 1511 1512 ret = p << 2; /* in ns units */ 1513 ret = ret / fs; /* in Cycles */ 1514 if (ret < sbic_min_period) 1515 return(sbic_min_period); 1516 1517 /* verify rounding */ 1518 if (sbictoscsiperiod(dev, regs, ret) < p) 1519 ret++; 1520 return (ret >= 8) ? 0 : ret; 1521 } 1522 1523