1 /* $NetBSD: sbic.c,v 1.39 2000/03/23 06:33:12 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Van Jacobson of Lawrence Berkeley Laboratory. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 * 39 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 40 */ 41 42 /* 43 * AMIGA AMD 33C93 scsi adaptor driver 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> /* For hz */ 52 #include <sys/disklabel.h> 53 #include <sys/dkstat.h> 54 #include <sys/buf.h> 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <vm/vm.h> 59 #include <vm/vm_kern.h> 60 #include <vm/vm_page.h> 61 #include <machine/pmap.h> 62 #include <machine/cpu.h> 63 #include <amiga/amiga/device.h> 64 #include <amiga/amiga/custom.h> 65 #include <amiga/amiga/isr.h> 66 #include <amiga/dev/dmavar.h> 67 #include <amiga/dev/sbicreg.h> 68 #include <amiga/dev/sbicvar.h> 69 70 /* These are for bounce buffers */ 71 #include <amiga/amiga/cc.h> 72 #include <amiga/dev/zbusvar.h> 73 74 #include <vm/pmap.h> 75 76 /* Since I can't find this in any other header files */ 77 #define SCSI_PHASE(reg) (reg&0x07) 78 79 /* 80 * SCSI delays 81 * In u-seconds, primarily for state changes on the SPC. 82 */ 83 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 84 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 85 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 86 87 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 88 89 int sbicicmd __P((struct sbic_softc *, int, int, void *, int, void *, int)); 90 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 91 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 92 int sbicwait __P((sbic_regmap_t, char, int , int)); 93 int sbiccheckdmap __P((void *, u_long, u_long)); 94 int sbicselectbus __P((struct sbic_softc *, sbic_regmap_t, u_char, u_char, u_char)); 95 int sbicxfstart __P((sbic_regmap_t, int, u_char, int)); 96 int sbicxfout __P((sbic_regmap_t regs, int, void *, int)); 97 int sbicfromscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 98 int sbictoscsiperiod __P((struct sbic_softc *, sbic_regmap_t, int)); 99 int sbicpoll __P((struct sbic_softc *)); 100 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 101 int sbicmsgin __P((struct sbic_softc *)); 102 int sbicxfin __P((sbic_regmap_t regs, int, void *)); 103 int sbicabort __P((struct sbic_softc *, sbic_regmap_t, char *)); 104 void sbicxfdone __P((struct sbic_softc *, sbic_regmap_t, int)); 105 void sbicerror __P((struct sbic_softc *, sbic_regmap_t, u_char)); 106 void sbicstart __P((struct sbic_softc *)); 107 void sbicreset __P((struct sbic_softc *)); 108 void sbic_scsidone __P((struct sbic_acb *, int)); 109 void sbic_sched __P((struct sbic_softc *)); 110 void sbic_save_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 111 void sbic_load_ptrs __P((struct sbic_softc *, sbic_regmap_t,int,int)); 112 #ifdef DEBUG 113 void sbicdumpstate __P((void)); 114 void sbic_dump_acb __P((struct sbic_acb *)); 115 #endif 116 117 /* 118 * Synch xfer parameters, and timing conversions 119 */ 120 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 121 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 122 123 int sbic_cmd_wait = SBIC_CMD_WAIT; 124 int sbic_data_wait = SBIC_DATA_WAIT; 125 int sbic_init_wait = SBIC_INIT_WAIT; 126 127 /* 128 * was broken before.. now if you want this you get it for all drives 129 * on sbic controllers. 130 */ 131 u_char sbic_inhibit_sync[8]; 132 int sbic_enable_reselect = 1; 133 int sbic_clock_override = 0; 134 int sbic_no_dma = 0; 135 int sbic_parallel_operations = 1; 136 137 #ifdef DEBUG 138 sbic_regmap_t debug_sbic_regs; 139 int sbicdma_ops = 0; /* total DMA operations */ 140 int sbicdma_bounces = 0; /* number operations using bounce buffer */ 141 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 142 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 143 int sbicdma_saves = 0; 144 #define QPRINTF(a) if (sbic_debug > 1) printf a 145 int sbic_debug = 0; 146 int sync_debug = 0; 147 int sbic_dma_debug = 0; 148 int reselect_debug = 0; 149 int report_sense = 0; 150 int data_pointer_debug = 0; 151 u_char debug_asr, debug_csr, routine; 152 void sbictimeout __P((struct sbic_softc *dev)); 153 154 #define CSR_TRACE_SIZE 32 155 #if CSR_TRACE_SIZE 156 #define CSR_TRACE(w,c,a,x) do { \ 157 int s = splbio(); \ 158 csr_trace[csr_traceptr].whr = (w); csr_trace[csr_traceptr].csr = (c); \ 159 csr_trace[csr_traceptr].asr = (a); csr_trace[csr_traceptr].xtn = (x); \ 160 dma_cachectl((caddr_t)&csr_trace[csr_traceptr], sizeof(csr_trace[0])); \ 161 csr_traceptr = (csr_traceptr + 1) & (CSR_TRACE_SIZE - 1); \ 162 /* dma_cachectl((caddr_t)&csr_traceptr, sizeof(csr_traceptr));*/ \ 163 splx(s); \ 164 } while (0) 165 int csr_traceptr; 166 int csr_tracesize = CSR_TRACE_SIZE; 167 struct { 168 u_char whr; 169 u_char csr; 170 u_char asr; 171 u_char xtn; 172 } csr_trace[CSR_TRACE_SIZE]; 173 #else 174 #define CSR_TRACE(w,c,a,x) 175 #endif 176 177 #define SBIC_TRACE_SIZE 0 178 #if SBIC_TRACE_SIZE 179 #define SBIC_TRACE(dev) do { \ 180 int s = splbio(); \ 181 sbic_trace[sbic_traceptr].sp = &s; \ 182 sbic_trace[sbic_traceptr].line = __LINE__; \ 183 sbic_trace[sbic_traceptr].sr = s; \ 184 sbic_trace[sbic_traceptr].csr = csr_traceptr; \ 185 dma_cachectl(&sbic_trace[sbic_traceptr], sizeof(sbic_trace[0])); \ 186 sbic_traceptr = (sbic_traceptr + 1) & (SBIC_TRACE_SIZE - 1); \ 187 dma_cachectl(&sbic_traceptr, sizeof(sbic_traceptr)); \ 188 if (dev) dma_cachectl(dev, sizeof(*dev)); \ 189 splx(s); \ 190 } while (0) 191 int sbic_traceptr; 192 int sbic_tracesize = SBIC_TRACE_SIZE; 193 struct { 194 void *sp; 195 u_short line; 196 u_short sr; 197 int csr; 198 } sbic_trace[SBIC_TRACE_SIZE]; 199 #else 200 #define SBIC_TRACE(dev) 201 #endif 202 203 #else /* DEBUG */ 204 #define QPRINTF(a) 205 #define CSR_TRACE(w,c,a,x) 206 #define SBIC_TRACE(dev) 207 #endif /* DEBUG */ 208 209 /* 210 * default minphys routine for sbic based controllers 211 */ 212 void 213 sbic_minphys(bp) 214 struct buf *bp; 215 { 216 217 /* 218 * No max transfer at this level. 219 */ 220 minphys(bp); 221 } 222 223 /* 224 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 225 */ 226 void 227 sbic_save_ptrs(dev, regs, target, lun) 228 struct sbic_softc *dev; 229 sbic_regmap_t regs; 230 int target, lun; 231 { 232 int count, asr, s; 233 struct sbic_acb* acb; 234 235 SBIC_TRACE(dev); 236 if( !dev->sc_cur ) return; 237 if( !(dev->sc_flags & SBICF_INDMA) ) return; /* DMA not active */ 238 239 s = splbio(); 240 241 acb = dev->sc_nexus; 242 count = -1; 243 do { 244 GET_SBIC_asr(regs, asr); 245 if( asr & SBIC_ASR_DBR ) { 246 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 247 splx(s); 248 SBIC_TRACE(dev); 249 return; 250 } 251 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 252 253 /* Save important state */ 254 /* must be done before dmastop */ 255 acb->sc_dmacmd = dev->sc_dmacmd; 256 SBIC_TC_GET(regs, count); 257 258 /* Shut down DMA ====CAREFUL==== */ 259 dev->sc_dmastop(dev); 260 dev->sc_flags &= ~SBICF_INDMA; 261 SBIC_TC_PUT(regs, 0); 262 263 #ifdef DEBUG 264 if(!count && sbic_debug) printf("%dcount0",target); 265 if(data_pointer_debug == -1) 266 printf("SBIC saving target %d data pointers from (%p,%x)%xASR:%02x", 267 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 268 acb->sc_dmacmd, asr); 269 #endif 270 271 /* Fixup partial xfers */ 272 acb->sc_kv.dc_addr += (dev->sc_tcnt - count); 273 acb->sc_kv.dc_count -= (dev->sc_tcnt - count); 274 acb->sc_pa.dc_addr += (dev->sc_tcnt - count); 275 acb->sc_pa.dc_count -= ((dev->sc_tcnt - count)>>1); 276 277 acb->sc_tcnt = dev->sc_tcnt = count; 278 #ifdef DEBUG 279 if(data_pointer_debug) 280 printf(" at (%p,%x):%x\n", 281 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 282 sbicdma_saves++; 283 #endif 284 splx(s); 285 SBIC_TRACE(dev); 286 } 287 288 289 /* 290 * DOES NOT RESTART DMA!!! 291 */ 292 void sbic_load_ptrs(dev, regs, target, lun) 293 struct sbic_softc *dev; 294 sbic_regmap_t regs; 295 int target, lun; 296 { 297 int s, count; 298 char* vaddr, * paddr; 299 struct sbic_acb *acb; 300 301 SBIC_TRACE(dev); 302 acb = dev->sc_nexus; 303 if( !acb->sc_kv.dc_count ) { 304 /* No data to xfer */ 305 SBIC_TRACE(dev); 306 return; 307 } 308 309 s = splbio(); 310 311 dev->sc_last = dev->sc_cur = &acb->sc_pa; 312 dev->sc_tcnt = acb->sc_tcnt; 313 dev->sc_dmacmd = acb->sc_dmacmd; 314 315 #ifdef DEBUG 316 sbicdma_ops++; 317 #endif 318 if( !dev->sc_tcnt ) { 319 /* sc_tcnt == 0 implies end of segment */ 320 321 /* do kvm to pa mappings */ 322 paddr = acb->sc_pa.dc_addr = 323 (char *) kvtop(acb->sc_kv.dc_addr); 324 325 vaddr = acb->sc_kv.dc_addr; 326 count = acb->sc_kv.dc_count; 327 for(count = (NBPG - ((int)vaddr & PGOFSET)); 328 count < acb->sc_kv.dc_count 329 && (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 330 count += NBPG); 331 /* If it's all contiguous... */ 332 if(count > acb->sc_kv.dc_count ) { 333 count = acb->sc_kv.dc_count; 334 #ifdef DEBUG 335 sbicdma_hits++; 336 #endif 337 } else { 338 #ifdef DEBUG 339 sbicdma_misses++; 340 #endif 341 } 342 acb->sc_tcnt = count; 343 acb->sc_pa.dc_count = count >> 1; 344 345 #ifdef DEBUG 346 if(data_pointer_debug) 347 printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", 348 acb->sc_kv.dc_addr, 349 acb->sc_kv.dc_count, 350 acb->sc_pa.dc_addr, 351 acb->sc_tcnt); 352 #endif 353 } 354 splx(s); 355 #ifdef DEBUG 356 if(data_pointer_debug) 357 printf("SBIC restoring target %d data pointers at (%p,%x)%x\n", 358 target, dev->sc_cur->dc_addr, dev->sc_cur->dc_count, 359 dev->sc_dmacmd); 360 #endif 361 SBIC_TRACE(dev); 362 } 363 364 /* 365 * used by specific sbic controller 366 * 367 * it appears that the higher level code does nothing with LUN's 368 * so I will too. I could plug it in, however so could they 369 * in scsi_scsipi_cmd(). 370 */ 371 int 372 sbic_scsicmd(xs) 373 struct scsipi_xfer *xs; 374 { 375 struct sbic_acb *acb; 376 struct sbic_softc *dev; 377 struct scsipi_link *slp; 378 int flags, s, stat; 379 380 slp = xs->sc_link; 381 dev = slp->adapter_softc; 382 SBIC_TRACE(dev); 383 flags = xs->xs_control; 384 385 if (flags & XS_CTL_DATA_UIO) 386 panic("sbic: scsi data uio requested"); 387 388 if (dev->sc_nexus && flags & XS_CTL_POLL) 389 panic("sbic_scsicmd: busy"); 390 391 if (slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target) 392 return ESCAPE_NOT_SUPPORTED; 393 394 s = splbio(); 395 acb = dev->free_list.tqh_first; 396 if (acb) 397 TAILQ_REMOVE(&dev->free_list, acb, chain); 398 splx(s); 399 400 if (acb == NULL) { 401 #ifdef DEBUG 402 printf("sbic_scsicmd: unable to queue request for target %d\n", 403 slp->scsipi_scsi.target); 404 #ifdef DDB 405 Debugger(); 406 #endif 407 #endif 408 xs->error = XS_DRIVER_STUFFUP; 409 SBIC_TRACE(dev); 410 return(TRY_AGAIN_LATER); 411 } 412 413 acb->flags = ACB_ACTIVE; 414 if (flags & XS_CTL_DATA_IN) 415 acb->flags |= ACB_DATAIN; 416 acb->xs = xs; 417 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 418 acb->clen = xs->cmdlen; 419 acb->sc_kv.dc_addr = xs->data; 420 acb->sc_kv.dc_count = xs->datalen; 421 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; /* XXXX check */ 422 423 if (flags & XS_CTL_POLL) { 424 s = splbio(); 425 /* 426 * This has major side effects -- it locks up the machine 427 */ 428 429 dev->sc_flags |= SBICF_ICMD; 430 do { 431 while(dev->sc_nexus) 432 sbicpoll(dev); 433 dev->sc_nexus = acb; 434 dev->sc_stat[0] = -1; 435 dev->sc_xs = xs; 436 dev->target = slp->scsipi_scsi.target; 437 dev->lun = slp->scsipi_scsi.lun; 438 stat = sbicicmd(dev, slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 439 &acb->cmd, acb->clen, 440 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 441 } while (dev->sc_nexus != acb); 442 sbic_scsidone(acb, stat); 443 444 splx(s); 445 SBIC_TRACE(dev); 446 return(COMPLETE); 447 } 448 449 s = splbio(); 450 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 451 452 if (dev->sc_nexus) { 453 splx(s); 454 SBIC_TRACE(dev); 455 return(SUCCESSFULLY_QUEUED); 456 } 457 458 /* 459 * nothing is active, try to start it now. 460 */ 461 sbic_sched(dev); 462 splx(s); 463 464 SBIC_TRACE(dev); 465 /* TODO: add sbic_poll to do XS_CTL_POLL operations */ 466 #if 0 467 if (flags & XS_CTL_POLL) 468 return(COMPLETE); 469 #endif 470 return(SUCCESSFULLY_QUEUED); 471 } 472 473 /* 474 * attempt to start the next available command 475 */ 476 void 477 sbic_sched(dev) 478 struct sbic_softc *dev; 479 { 480 struct scsipi_xfer *xs; 481 struct scsipi_link *slp; 482 struct sbic_acb *acb; 483 int flags, /*phase,*/ stat, i; 484 485 SBIC_TRACE(dev); 486 if (dev->sc_nexus) 487 return; /* a command is current active */ 488 489 SBIC_TRACE(dev); 490 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 491 slp = acb->xs->sc_link; 492 i = slp->scsipi_scsi.target; 493 if (!(dev->sc_tinfo[i].lubusy & (1 << slp->scsipi_scsi.lun))) { 494 struct sbic_tinfo *ti = &dev->sc_tinfo[i]; 495 496 TAILQ_REMOVE(&dev->ready_list, acb, chain); 497 dev->sc_nexus = acb; 498 slp = acb->xs->sc_link; 499 ti = &dev->sc_tinfo[slp->scsipi_scsi.target]; 500 ti->lubusy |= (1 << slp->scsipi_scsi.lun); 501 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 502 break; 503 } 504 } 505 506 SBIC_TRACE(dev); 507 if (acb == NULL) 508 return; /* did not find an available command */ 509 510 dev->sc_xs = xs = acb->xs; 511 slp = xs->sc_link; 512 flags = xs->xs_control; 513 514 if (flags & XS_CTL_RESET) 515 sbicreset(dev); 516 517 #ifdef DEBUG 518 if( data_pointer_debug > 1 ) 519 printf("sbic_sched(%d,%d)\n",slp->scsipi_scsi.target, 520 slp->scsipi_scsi.lun); 521 #endif 522 dev->sc_stat[0] = -1; 523 dev->target = slp->scsipi_scsi.target; 524 dev->lun = slp->scsipi_scsi.lun; 525 if ( flags & XS_CTL_POLL || ( !sbic_parallel_operations 526 && (sbicdmaok(dev, xs) == 0))) 527 stat = sbicicmd(dev, slp->scsipi_scsi.target, 528 slp->scsipi_scsi.lun, &acb->cmd, 529 acb->clen, acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 530 else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) { 531 SBIC_TRACE(dev); 532 return; 533 } else 534 stat = dev->sc_stat[0]; 535 536 sbic_scsidone(acb, stat); 537 SBIC_TRACE(dev); 538 } 539 540 void 541 sbic_scsidone(acb, stat) 542 struct sbic_acb *acb; 543 int stat; 544 { 545 struct scsipi_xfer *xs; 546 struct scsipi_link *slp; 547 struct sbic_softc *dev; 548 int dosched = 0; 549 550 xs = acb->xs; 551 slp = xs->sc_link; 552 dev = slp->adapter_softc; 553 SBIC_TRACE(dev); 554 #ifdef DIAGNOSTIC 555 if (acb == NULL || xs == NULL) { 556 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", 557 dev->target, dev->lun); 558 #ifdef DDB 559 Debugger(); 560 #endif 561 return; 562 } 563 #endif 564 /* 565 * is this right? 566 */ 567 xs->status = stat; 568 569 #ifdef DEBUG 570 if( data_pointer_debug > 1 ) 571 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", 572 slp->scsipi_scsi.target, slp->scsipi_scsi.lun, 573 dev->target, dev->lun, stat); 574 if( xs->sc_link->scsipi_scsi.target == 575 dev->sc_link.scsipi_scsi.adapter_target ) 576 panic("target == hostid"); 577 #endif 578 579 if (xs->error == XS_NOERROR && !(acb->flags & ACB_CHKSENSE)) { 580 if (stat == SCSI_CHECK) { 581 /* Schedule a REQUEST SENSE */ 582 struct scsipi_sense *ss = (void *)&acb->cmd; 583 #ifdef DEBUG 584 if (report_sense) 585 printf("sbic_scsidone: autosense %02x targ %d lun %d", 586 acb->cmd.opcode, slp->scsipi_scsi.target, 587 slp->scsipi_scsi.lun); 588 #endif 589 bzero(ss, sizeof(*ss)); 590 ss->opcode = REQUEST_SENSE; 591 ss->byte2 = slp->scsipi_scsi.lun << 5; 592 ss->length = sizeof(struct scsipi_sense_data); 593 acb->clen = sizeof(*ss); 594 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 595 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 596 acb->pa_addr = (char *)kvtop((u_char *)&xs->sense.scsi_sense); /* XXX check */ 597 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 598 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 599 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 600 ~(1 << slp->scsipi_scsi.lun); 601 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 602 if (dev->sc_nexus == acb) { 603 dev->sc_nexus = NULL; 604 dev->sc_xs = NULL; 605 sbic_sched(dev); 606 } 607 SBIC_TRACE(dev); 608 return; 609 } 610 } 611 if (xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE)) { 612 xs->error = XS_SENSE; 613 #ifdef DEBUG 614 if (report_sense) 615 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 616 xs->sense.scsi_sense.extra_bytes[3]); 617 #endif 618 } else { 619 xs->resid = 0; /* XXXX */ 620 } 621 #if whataboutthisone 622 case SCSI_BUSY: 623 xs->error = XS_BUSY; 624 break; 625 #endif 626 xs->xs_status |= XS_STS_DONE; 627 628 /* 629 * Remove the ACB from whatever queue it's on. We have to do a bit of 630 * a hack to figure out which queue it's on. Note that it is *not* 631 * necessary to cdr down the ready queue, but we must cdr down the 632 * nexus queue and see if it's there, so we can mark the unit as no 633 * longer busy. This code is sickening, but it works. 634 */ 635 if (acb == dev->sc_nexus) { 636 dev->sc_nexus = NULL; 637 dev->sc_xs = NULL; 638 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 639 ~(1<<slp->scsipi_scsi.lun); 640 if (dev->ready_list.tqh_first) 641 dosched = 1; /* start next command */ 642 } else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { 643 TAILQ_REMOVE(&dev->ready_list, acb, chain); 644 } else { 645 register struct sbic_acb *acb2; 646 for (acb2 = dev->nexus_list.tqh_first; acb2; 647 acb2 = acb2->chain.tqe_next) { 648 if (acb2 == acb) { 649 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 650 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy 651 &= ~(1<<slp->scsipi_scsi.lun); 652 break; 653 } 654 } 655 if (acb2) 656 ; 657 else if (acb->chain.tqe_next) { 658 TAILQ_REMOVE(&dev->ready_list, acb, chain); 659 } else { 660 printf("%s: can't find matching acb\n", 661 dev->sc_dev.dv_xname); 662 #ifdef DDB 663 Debugger(); 664 #endif 665 } 666 } 667 /* Put it on the free list. */ 668 acb->flags = ACB_FREE; 669 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 670 671 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 672 673 scsipi_done(xs); 674 675 if (dosched) 676 sbic_sched(dev); 677 SBIC_TRACE(dev); 678 } 679 680 int 681 sbicdmaok(dev, xs) 682 struct sbic_softc *dev; 683 struct scsipi_xfer *xs; 684 { 685 if (sbic_no_dma || !xs->datalen || xs->datalen & 0x1 || 686 (u_int)xs->data & 0x3) 687 return(0); 688 /* 689 * controller supports dma to any addresses? 690 */ 691 else if ((dev->sc_flags & SBICF_BADDMA) == 0) 692 return(1); 693 /* 694 * this address is ok for dma? 695 */ 696 else if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) 697 return(1); 698 /* 699 * we have a bounce buffer? 700 */ 701 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 702 return(1); 703 /* 704 * try to get one 705 */ 706 else if ((dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 707 = (char *)alloc_z2mem(MAXPHYS))) { 708 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 709 printf("alloc ZII target %d bounce pa 0x%x\n", 710 xs->sc_link->scsipi_scsi.target, 711 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 712 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 713 printf("alloc CHIP target %d bounce pa 0x%p\n", 714 xs->sc_link->scsipi_scsi.target, 715 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 716 return(1); 717 } 718 719 return(0); 720 } 721 722 723 int 724 sbicwait(regs, until, timeo, line) 725 sbic_regmap_t regs; 726 char until; 727 int timeo; 728 int line; 729 { 730 u_char val; 731 int csr; 732 733 SBIC_TRACE((struct sbic_softc *)0); 734 if (timeo == 0) 735 timeo = 1000000; /* some large value.. */ 736 737 GET_SBIC_asr(regs,val); 738 while ((val & until) == 0) { 739 if (timeo-- == 0) { 740 GET_SBIC_csr(regs, csr); 741 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", 742 line, val, csr); 743 #if defined(DDB) && defined(DEBUG) 744 Debugger(); 745 #endif 746 return(val); /* Maybe I should abort */ 747 break; 748 } 749 DELAY(1); 750 GET_SBIC_asr(regs,val); 751 } 752 SBIC_TRACE((struct sbic_softc *)0); 753 return(val); 754 } 755 756 int 757 sbicabort(dev, regs, where) 758 struct sbic_softc *dev; 759 sbic_regmap_t regs; 760 char *where; 761 { 762 u_char csr, asr; 763 764 GET_SBIC_asr(regs, asr); 765 GET_SBIC_csr(regs, csr); 766 767 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 768 dev->sc_dev.dv_xname, where, csr, asr); 769 770 771 #if 0 772 /* Clean up running command */ 773 if (dev->sc_nexus != NULL) { 774 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 775 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 776 } 777 while (acb = dev->nexus_list.tqh_first) { 778 acb->xs->error = XS_DRIVER_STUFFUP; 779 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 780 } 781 #endif 782 783 /* Clean up chip itself */ 784 if (dev->sc_flags & SBICF_SELECTED) { 785 while( asr & SBIC_ASR_DBR ) { 786 /* sbic is jammed w/data. need to clear it */ 787 /* But we don't know what direction it needs to go */ 788 GET_SBIC_data(regs, asr); 789 printf("%s: abort %s: clearing data buffer 0x%02x\n", 790 dev->sc_dev.dv_xname, where, asr); 791 GET_SBIC_asr(regs, asr); 792 if( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 793 SET_SBIC_data(regs, asr); 794 GET_SBIC_asr(regs, asr); 795 } 796 WAIT_CIP(regs); 797 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 798 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 799 WAIT_CIP(regs); 800 801 GET_SBIC_asr(regs, asr); 802 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 803 /* ok, get more drastic.. */ 804 805 printf("%s: sbicabort - asr %x, trying to reset\n", dev->sc_dev.dv_xname, asr); 806 sbicreset(dev); 807 dev->sc_flags &= ~SBICF_SELECTED; 808 return -1; 809 } 810 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 811 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 812 813 do { 814 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 815 GET_SBIC_csr (regs, csr); 816 CSR_TRACE('a',csr,asr,0); 817 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 818 && (csr != SBIC_CSR_CMD_INVALID)); 819 820 /* lets just hope it worked.. */ 821 dev->sc_flags &= ~SBICF_SELECTED; 822 } 823 return -1; 824 } 825 826 827 /* 828 * Initialize driver-private structures 829 */ 830 831 void 832 sbicinit(dev) 833 struct sbic_softc *dev; 834 { 835 sbic_regmap_t regs; 836 u_int i; 837 struct sbic_acb *acb; 838 u_int inhibit_sync; 839 840 extern u_long scsi_nosync; 841 extern int shift_nosync; 842 843 regs = dev->sc_sbic; 844 845 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 846 TAILQ_INIT(&dev->ready_list); 847 TAILQ_INIT(&dev->nexus_list); 848 TAILQ_INIT(&dev->free_list); 849 callout_init(&dev->sc_timo_ch); 850 dev->sc_nexus = NULL; 851 dev->sc_xs = NULL; 852 acb = dev->sc_acb; 853 bzero(acb, sizeof(dev->sc_acb)); 854 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 855 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 856 acb++; 857 } 858 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 859 #ifdef DEBUG 860 /* make sure timeout is really not needed */ 861 callout_reset(&dev->sc_timo_ch, 30 * hz, 862 (void *)sbictimeout, dev); 863 #endif 864 865 } else panic("sbic: reinitializing driver!"); 866 867 dev->sc_flags |= SBICF_ALIVE; 868 dev->sc_flags &= ~SBICF_SELECTED; 869 870 /* initialize inhibit array */ 871 if (scsi_nosync) { 872 inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 873 shift_nosync += 8; 874 #ifdef DEBUG 875 if (inhibit_sync) 876 printf("%s: Inhibiting synchronous transfer %02x\n", 877 dev->sc_dev.dv_xname, inhibit_sync); 878 #endif 879 for (i = 0; i < 8; ++i) 880 if (inhibit_sync & (1 << i)) 881 sbic_inhibit_sync[i] = 1; 882 } 883 884 sbicreset(dev); 885 } 886 887 void 888 sbicreset(dev) 889 struct sbic_softc *dev; 890 { 891 sbic_regmap_t regs; 892 u_int my_id, s; 893 u_char csr; 894 #if 0 895 u_int i; 896 struct sbic_acb *acb; 897 #endif 898 899 regs = dev->sc_sbic; 900 #if 0 901 if (dev->sc_flags & SBICF_ALIVE) { 902 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 903 WAIT_CIP(regs); 904 } 905 #else 906 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 907 WAIT_CIP(regs); 908 #endif 909 s = splbio(); 910 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 911 912 /* Enable advanced mode */ 913 my_id |= SBIC_ID_EAF /*| SBIC_ID_EHP*/ ; 914 SET_SBIC_myid(regs, my_id); 915 916 /* 917 * Disable interrupts (in dmainit) then reset the chip 918 */ 919 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 920 DELAY(25); 921 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 922 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 923 924 if (dev->sc_clkfreq < 110) 925 my_id |= SBIC_ID_FS_8_10; 926 else if (dev->sc_clkfreq < 160) 927 my_id |= SBIC_ID_FS_12_15; 928 else if (dev->sc_clkfreq < 210) 929 my_id |= SBIC_ID_FS_16_20; 930 931 SET_SBIC_myid(regs, my_id); 932 933 /* 934 * Set up various chip parameters 935 */ 936 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /* | SBIC_CTL_HSP */ 937 | SBIC_MACHINE_DMA_MODE); 938 /* 939 * don't allow (re)selection (SBIC_RID_ES) 940 * until we can handle target mode!! 941 */ 942 SET_SBIC_rselid(regs, SBIC_RID_ER); 943 SET_SBIC_syn(regs, 0); /* asynch for now */ 944 945 /* 946 * anything else was zeroed by reset 947 */ 948 splx(s); 949 950 #if 0 951 if ((dev->sc_flags & SBICF_ALIVE) == 0) { 952 TAILQ_INIT(&dev->ready_list); 953 TAILQ_INIT(&dev->nexus_list); 954 TAILQ_INIT(&dev->free_list); 955 dev->sc_nexus = NULL; 956 dev->sc_xs = NULL; 957 acb = dev->sc_acb; 958 bzero(acb, sizeof(dev->sc_acb)); 959 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 960 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 961 acb++; 962 } 963 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 964 } else { 965 if (dev->sc_nexus != NULL) { 966 dev->sc_nexus->xs->error = XS_DRIVER_STUFFUP; 967 sbic_scsidone(dev->sc_nexus, dev->sc_stat[0]); 968 } 969 while (acb = dev->nexus_list.tqh_first) { 970 acb->xs->error = XS_DRIVER_STUFFUP; 971 sbic_scsidone(acb, -1 /*acb->stat[0]*/); 972 } 973 } 974 975 dev->sc_flags |= SBICF_ALIVE; 976 #endif 977 dev->sc_flags &= ~SBICF_SELECTED; 978 } 979 980 void 981 sbicerror(dev, regs, csr) 982 struct sbic_softc *dev; 983 sbic_regmap_t regs; 984 u_char csr; 985 { 986 struct scsipi_xfer *xs; 987 988 xs = dev->sc_xs; 989 990 #ifdef DIAGNOSTIC 991 if (xs == NULL) 992 panic("sbicerror"); 993 #endif 994 if (xs->xs_control & XS_CTL_SILENT) 995 return; 996 997 printf("%s: ", dev->sc_dev.dv_xname); 998 printf("csr == 0x%02x\n", csr); /* XXX */ 999 } 1000 1001 /* 1002 * select the bus, return when selected or error. 1003 */ 1004 int 1005 sbicselectbus(dev, regs, target, lun, our_addr) 1006 struct sbic_softc *dev; 1007 sbic_regmap_t regs; 1008 u_char target, lun, our_addr; 1009 { 1010 u_char asr, csr, id; 1011 1012 SBIC_TRACE(dev); 1013 QPRINTF(("sbicselectbus %d\n", target)); 1014 1015 /* 1016 * if we're already selected, return (XXXX panic maybe?) 1017 */ 1018 if (dev->sc_flags & SBICF_SELECTED) { 1019 SBIC_TRACE(dev); 1020 return(1); 1021 } 1022 1023 /* 1024 * issue select 1025 */ 1026 SBIC_TC_PUT(regs, 0); 1027 SET_SBIC_selid(regs, target); 1028 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250,dev->sc_clkfreq)); 1029 1030 /* 1031 * set sync or async 1032 */ 1033 if (dev->sc_sync[target].state == SYNC_DONE) 1034 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[target].offset, 1035 dev->sc_sync[target].period)); 1036 else 1037 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 1038 1039 GET_SBIC_asr(regs, asr); 1040 if( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1041 /* This means we got ourselves reselected upon */ 1042 /* printf("sbicselectbus: INT/BSY asr %02x\n", asr);*/ 1043 #ifdef DDB 1044 /* Debugger();*/ 1045 #endif 1046 SBIC_TRACE(dev); 1047 return 1; 1048 } 1049 1050 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1051 1052 /* 1053 * wait for select (merged from seperate function may need 1054 * cleanup) 1055 */ 1056 WAIT_CIP(regs); 1057 do { 1058 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1059 if (asr & SBIC_ASR_LCI) { 1060 #ifdef DEBUG 1061 if (reselect_debug) 1062 printf("sbicselectbus: late LCI asr %02x\n", asr); 1063 #endif 1064 SBIC_TRACE(dev); 1065 return 1; 1066 } 1067 GET_SBIC_csr (regs, csr); 1068 CSR_TRACE('s',csr,asr,target); 1069 QPRINTF(("%02x ", csr)); 1070 if( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 1071 #ifdef DEBUG 1072 if(reselect_debug) 1073 printf("sbicselectbus: reselected asr %02x\n", asr); 1074 #endif 1075 /* We need to handle this now so we don't lock up later */ 1076 sbicnextstate(dev, csr, asr); 1077 SBIC_TRACE(dev); 1078 return 1; 1079 } 1080 if( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 1081 panic("sbicselectbus: target issued select!"); 1082 return 1; 1083 } 1084 } while (csr != (SBIC_CSR_MIS_2|MESG_OUT_PHASE) 1085 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); 1086 1087 /* Enable (or not) reselection */ 1088 if(!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1089 SET_SBIC_rselid (regs, 0); 1090 else 1091 SET_SBIC_rselid (regs, SBIC_RID_ER); 1092 1093 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { 1094 dev->sc_flags |= SBICF_SELECTED; /* device ignored ATN */ 1095 GET_SBIC_selid(regs, id); 1096 dev->target = id; 1097 GET_SBIC_tlun(regs,dev->lun); 1098 if( dev->lun & SBIC_TLUN_VALID ) 1099 dev->lun &= SBIC_TLUN_MASK; 1100 else 1101 dev->lun = lun; 1102 } else if (csr == (SBIC_CSR_MIS_2|MESG_OUT_PHASE)) { 1103 /* 1104 * Send identify message 1105 * (SCSI-2 requires an identify msg (?)) 1106 */ 1107 GET_SBIC_selid(regs, id); 1108 dev->target = id; 1109 GET_SBIC_tlun(regs,dev->lun); 1110 if( dev->lun & SBIC_TLUN_VALID ) 1111 dev->lun &= SBIC_TLUN_MASK; 1112 else 1113 dev->lun = lun; 1114 /* 1115 * handle drives that don't want to be asked 1116 * whether to go sync at all. 1117 */ 1118 if (sbic_inhibit_sync[id] 1119 && dev->sc_sync[id].state == SYNC_START) { 1120 #ifdef DEBUG 1121 if (sync_debug) 1122 printf("Forcing target %d asynchronous.\n", id); 1123 #endif 1124 dev->sc_sync[id].offset = 0; 1125 dev->sc_sync[id].period = sbic_min_period; 1126 dev->sc_sync[id].state = SYNC_DONE; 1127 } 1128 1129 1130 if (dev->sc_sync[id].state != SYNC_START){ 1131 if( dev->sc_xs->xs_control & XS_CTL_POLL 1132 || (dev->sc_flags & SBICF_ICMD) 1133 || !sbic_enable_reselect ) 1134 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1135 else 1136 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1137 } else { 1138 /* 1139 * try to initiate a sync transfer. 1140 * So compose the sync message we're going 1141 * to send to the target 1142 */ 1143 1144 #ifdef DEBUG 1145 if (sync_debug) 1146 printf("Sending sync request to target %d ... ", 1147 id); 1148 #endif 1149 /* 1150 * setup scsi message sync message request 1151 */ 1152 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1153 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1154 dev->sc_msg[2] = 3; 1155 dev->sc_msg[3] = MSG_SYNC_REQ; 1156 dev->sc_msg[4] = sbictoscsiperiod(dev, regs, 1157 sbic_min_period); 1158 dev->sc_msg[5] = sbic_max_offset; 1159 1160 if (sbicxfstart(regs, 6, MESG_OUT_PHASE, sbic_cmd_wait)) 1161 sbicxfout(regs, 6, dev->sc_msg, MESG_OUT_PHASE); 1162 1163 dev->sc_sync[id].state = SYNC_SENT; 1164 #ifdef DEBUG 1165 if (sync_debug) 1166 printf ("sent\n"); 1167 #endif 1168 } 1169 1170 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1171 GET_SBIC_csr (regs, csr); 1172 CSR_TRACE('y',csr,asr,target); 1173 QPRINTF(("[%02x]", csr)); 1174 #ifdef DEBUG 1175 if (sync_debug && dev->sc_sync[id].state == SYNC_SENT) 1176 printf("csr-result of last msgout: 0x%x\n", csr); 1177 #endif 1178 1179 if (csr != SBIC_CSR_SEL_TIMEO) 1180 dev->sc_flags |= SBICF_SELECTED; 1181 } 1182 if (csr == SBIC_CSR_SEL_TIMEO) 1183 dev->sc_xs->error = XS_SELTIMEOUT; 1184 1185 QPRINTF(("\n")); 1186 1187 SBIC_TRACE(dev); 1188 return(csr == SBIC_CSR_SEL_TIMEO); 1189 } 1190 1191 int 1192 sbicxfstart(regs, len, phase, wait) 1193 sbic_regmap_t regs; 1194 int len, wait; 1195 u_char phase; 1196 { 1197 u_char id; 1198 1199 switch (phase) { 1200 case DATA_IN_PHASE: 1201 case MESG_IN_PHASE: 1202 GET_SBIC_selid (regs, id); 1203 id |= SBIC_SID_FROM_SCSI; 1204 SET_SBIC_selid (regs, id); 1205 SBIC_TC_PUT (regs, (unsigned)len); 1206 break; 1207 case DATA_OUT_PHASE: 1208 case MESG_OUT_PHASE: 1209 case CMD_PHASE: 1210 GET_SBIC_selid (regs, id); 1211 id &= ~SBIC_SID_FROM_SCSI; 1212 SET_SBIC_selid (regs, id); 1213 SBIC_TC_PUT (regs, (unsigned)len); 1214 break; 1215 default: 1216 SBIC_TC_PUT (regs, 0); 1217 } 1218 QPRINTF(("sbicxfstart %d, %d, %d\n", len, phase, wait)); 1219 1220 return(1); 1221 } 1222 1223 int 1224 sbicxfout(regs, len, bp, phase) 1225 sbic_regmap_t regs; 1226 int len; 1227 void *bp; 1228 int phase; 1229 { 1230 u_char orig_csr, asr, *buf; 1231 int wait; 1232 1233 buf = bp; 1234 wait = sbic_data_wait; 1235 1236 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1237 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1238 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1239 1240 GET_SBIC_csr (regs, orig_csr); 1241 CSR_TRACE('>',orig_csr,0,0); 1242 1243 /* 1244 * sigh.. WD-PROTO strikes again.. sending the command in one go 1245 * causes the chip to lock up if talking to certain (misbehaving?) 1246 * targets. Anyway, this procedure should work for all targets, but 1247 * it's slightly slower due to the overhead 1248 */ 1249 WAIT_CIP (regs); 1250 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1251 for (;len > 0; len--) { 1252 GET_SBIC_asr (regs, asr); 1253 while ((asr & SBIC_ASR_DBR) == 0) { 1254 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1255 #ifdef DEBUG 1256 if (sbic_debug) 1257 printf("sbicxfout fail: l%d i%x w%d\n", 1258 len, asr, wait); 1259 #endif 1260 return (len); 1261 } 1262 /* DELAY(1);*/ 1263 GET_SBIC_asr (regs, asr); 1264 } 1265 1266 SET_SBIC_data (regs, *buf); 1267 buf++; 1268 } 1269 SBIC_TC_GET(regs, len); 1270 QPRINTF(("sbicxfout done %d bytes\n", len)); 1271 /* 1272 * this leaves with one csr to be read 1273 */ 1274 return(0); 1275 } 1276 1277 /* returns # bytes left to read */ 1278 int 1279 sbicxfin(regs, len, bp) 1280 sbic_regmap_t regs; 1281 int len; 1282 void *bp; 1283 { 1284 int wait; 1285 u_char *obp, *buf; 1286 u_char orig_csr, csr, asr; 1287 1288 wait = sbic_data_wait; 1289 obp = bp; 1290 buf = bp; 1291 1292 GET_SBIC_csr (regs, orig_csr); 1293 CSR_TRACE('<',orig_csr,0,0); 1294 1295 QPRINTF(("sbicxfin %d, csr=%02x\n", len, orig_csr)); 1296 1297 WAIT_CIP (regs); 1298 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1299 for (;len > 0; len--) { 1300 GET_SBIC_asr (regs, asr); 1301 if((asr & SBIC_ASR_PE)) { 1302 #ifdef DEBUG 1303 printf("sbicxfin parity error: l%d i%x w%d\n", 1304 len, asr, wait); 1305 /* return ((unsigned long)buf - (unsigned long)bp); */ 1306 #ifdef DDB 1307 Debugger(); 1308 #endif 1309 #endif 1310 } 1311 while ((asr & SBIC_ASR_DBR) == 0) { 1312 if ((asr & SBIC_ASR_INT) || --wait < 0) { 1313 #ifdef DEBUG 1314 if (sbic_debug) { 1315 QPRINTF(("sbicxfin fail:{%d} %02x %02x %02x %02x %02x %02x " 1316 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1317 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1318 printf("sbicxfin fail: l%d i%x w%d\n", 1319 len, asr, wait); 1320 } 1321 #endif 1322 return len; 1323 } 1324 1325 if( ! asr & SBIC_ASR_BSY ) { 1326 GET_SBIC_csr(regs, csr); 1327 CSR_TRACE('<',csr,asr,len); 1328 QPRINTF(("[CSR%02xASR%02x]", csr, asr)); 1329 } 1330 1331 /* DELAY(1);*/ 1332 GET_SBIC_asr (regs, asr); 1333 } 1334 1335 GET_SBIC_data (regs, *buf); 1336 /* QPRINTF(("asr=%02x, csr=%02x, data=%02x\n", asr, csr, *buf));*/ 1337 buf++; 1338 } 1339 1340 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1341 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1342 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1343 1344 /* this leaves with one csr to be read */ 1345 return len; 1346 } 1347 1348 /* 1349 * SCSI 'immediate' command: issue a command to some SCSI device 1350 * and get back an 'immediate' response (i.e., do programmed xfer 1351 * to get the response data). 'cbuf' is a buffer containing a scsi 1352 * command of length clen bytes. 'buf' is a buffer of length 'len' 1353 * bytes for data. The transfer direction is determined by the device 1354 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1355 * command must supply no data. 1356 */ 1357 int 1358 sbicicmd(dev, target, lun, cbuf, clen, buf, len) 1359 struct sbic_softc *dev; 1360 void *cbuf, *buf; 1361 int clen, len; 1362 { 1363 sbic_regmap_t regs; 1364 u_char phase, csr, asr; 1365 int wait, i; 1366 struct sbic_acb *acb; 1367 1368 #define CSR_LOG_BUF_SIZE 0 1369 #if CSR_LOG_BUF_SIZE 1370 int bufptr; 1371 int csrbuf[CSR_LOG_BUF_SIZE]; 1372 bufptr=0; 1373 #endif 1374 1375 SBIC_TRACE(dev); 1376 regs = dev->sc_sbic; 1377 acb = dev->sc_nexus; 1378 1379 /* Make sure pointers are OK */ 1380 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1381 dev->sc_tcnt = acb->sc_tcnt = 0; 1382 acb->sc_pa.dc_count = 0; /* No DMA */ 1383 acb->sc_kv.dc_addr = buf; 1384 acb->sc_kv.dc_count = len; 1385 1386 #ifdef DEBUG 1387 routine = 3; 1388 debug_sbic_regs = regs; /* store this to allow debug calls */ 1389 if( data_pointer_debug > 1 ) 1390 printf("sbicicmd(%d,%d):%d\n", target, lun, 1391 acb->sc_kv.dc_count); 1392 #endif 1393 1394 /* 1395 * set the sbic into non-DMA mode 1396 */ 1397 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI /*| SBIC_CTL_HSP*/); 1398 1399 dev->sc_stat[0] = 0xff; 1400 dev->sc_msg[0] = 0xff; 1401 i = 1; /* pre-load */ 1402 1403 /* We're stealing the SCSI bus */ 1404 dev->sc_flags |= SBICF_ICMD; 1405 1406 do { 1407 /* 1408 * select the SCSI bus (it's an error if bus isn't free) 1409 */ 1410 if (!( dev->sc_flags & SBICF_SELECTED ) 1411 && sbicselectbus(dev, regs, target, lun, dev->sc_scsiaddr)) { 1412 /* printf("sbicicmd: trying to select busy bus!\n"); */ 1413 dev->sc_flags &= ~SBICF_ICMD; 1414 return(-1); 1415 } 1416 1417 /* 1418 * Wait for a phase change (or error) then let the device sequence 1419 * us through the various SCSI phases. 1420 */ 1421 1422 wait = sbic_cmd_wait; 1423 1424 asr = GET_SBIC_asr (regs, asr); 1425 GET_SBIC_csr (regs, csr); 1426 CSR_TRACE('I',csr,asr,target); 1427 QPRINTF((">ASR:%02xCSR:%02x<", asr, csr)); 1428 1429 #if CSR_LOG_BUF_SIZE 1430 csrbuf[bufptr++] = csr; 1431 #endif 1432 1433 1434 switch (csr) { 1435 case SBIC_CSR_S_XFERRED: 1436 case SBIC_CSR_DISC: 1437 case SBIC_CSR_DISC_1: 1438 dev->sc_flags &= ~SBICF_SELECTED; 1439 GET_SBIC_cmd_phase (regs, phase); 1440 if (phase == 0x60) { 1441 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1442 i = 0; /* done */ 1443 /* break; */ /* Bypass all the state gobldygook */ 1444 } else { 1445 #ifdef DEBUG 1446 if(reselect_debug>1) 1447 printf("sbicicmd: handling disconnect\n"); 1448 #endif 1449 i = SBIC_STATE_DISCONNECT; 1450 } 1451 break; 1452 1453 case SBIC_CSR_XFERRED|CMD_PHASE: 1454 case SBIC_CSR_MIS|CMD_PHASE: 1455 case SBIC_CSR_MIS_1|CMD_PHASE: 1456 case SBIC_CSR_MIS_2|CMD_PHASE: 1457 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) 1458 if (sbicxfout(regs, clen, 1459 cbuf, CMD_PHASE)) 1460 i = sbicabort(dev, regs,"icmd sending cmd"); 1461 #if 0 1462 GET_SBIC_csr(regs, csr); /* Lets us reload tcount */ 1463 WAIT_CIP(regs); 1464 GET_SBIC_asr(regs, asr); 1465 CSR_TRACE('I',csr,asr,target); 1466 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 1467 printf("next: cmd sent asr %02x, csr %02x\n", 1468 asr, csr); 1469 #endif 1470 break; 1471 1472 #if 0 1473 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 1474 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 1475 case SBIC_CSR_MIS|DATA_OUT_PHASE: 1476 case SBIC_CSR_MIS|DATA_IN_PHASE: 1477 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 1478 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 1479 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 1480 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 1481 if (acb->sc_kv.dc_count <= 0) 1482 i = sbicabort(dev, regs, "icmd out of data"); 1483 else { 1484 wait = sbic_data_wait; 1485 if (sbicxfstart(regs, 1486 acb->sc_kv.dc_count, 1487 SBIC_PHASE(csr), wait)) 1488 if (csr & 0x01) 1489 /* data in? */ 1490 i=sbicxfin(regs, 1491 acb->sc_kv.dc_count, 1492 acb->sc_kv.dc_addr); 1493 else 1494 i=sbicxfout(regs, 1495 acb->sc_kv.dc_count, 1496 acb->sc_kv.dc_addr, 1497 SBIC_PHASE(csr)); 1498 acb->sc_kv.dc_addr += 1499 (acb->sc_kv.dc_count - i); 1500 acb->sc_kv.dc_count = i; 1501 i = 1; 1502 } 1503 break; 1504 1505 #endif 1506 case SBIC_CSR_XFERRED|STATUS_PHASE: 1507 case SBIC_CSR_MIS|STATUS_PHASE: 1508 case SBIC_CSR_MIS_1|STATUS_PHASE: 1509 case SBIC_CSR_MIS_2|STATUS_PHASE: 1510 /* 1511 * the sbic does the status/cmd-complete reading ok, 1512 * so do this with its hi-level commands. 1513 */ 1514 #ifdef DEBUG 1515 if(sbic_debug) 1516 printf("SBICICMD status phase\n"); 1517 #endif 1518 SBIC_TC_PUT(regs, 0); 1519 SET_SBIC_cmd_phase(regs, 0x46); 1520 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1521 break; 1522 1523 #if THIS_IS_A_RESERVED_STATE 1524 case BUS_FREE_PHASE: /* This is not legal */ 1525 if( dev->sc_stat[0] != 0xff ) 1526 goto out; 1527 break; 1528 #endif 1529 1530 default: 1531 i = sbicnextstate(dev, csr, asr); 1532 } 1533 1534 /* 1535 * make sure the last command was taken, 1536 * ie. we're not hunting after an ignored command.. 1537 */ 1538 GET_SBIC_asr(regs, asr); 1539 1540 /* tapes may take a loooong time.. */ 1541 while (asr & SBIC_ASR_BSY){ 1542 if(asr & SBIC_ASR_DBR) { 1543 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1544 csr,asr); 1545 #ifdef DDB 1546 Debugger(); 1547 #endif 1548 /* SBIC is jammed */ 1549 /* DUNNO which direction */ 1550 /* Try old direction */ 1551 GET_SBIC_data(regs,i); 1552 GET_SBIC_asr(regs, asr); 1553 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1554 SET_SBIC_data(regs,i); 1555 } 1556 GET_SBIC_asr(regs, asr); 1557 } 1558 1559 /* 1560 * wait for last command to complete 1561 */ 1562 if (asr & SBIC_ASR_LCI) { 1563 printf("sbicicmd: last command ignored\n"); 1564 } 1565 else if( i == 1 ) /* Bsy */ 1566 SBIC_WAIT (regs, SBIC_ASR_INT, wait); 1567 1568 /* 1569 * do it again 1570 */ 1571 } while ( i > 0 && dev->sc_stat[0] == 0xff); 1572 1573 /* Sometimes we need to do an extra read of the CSR */ 1574 GET_SBIC_csr(regs, csr); 1575 CSR_TRACE('I',csr,asr,0xff); 1576 1577 #if CSR_LOG_BUF_SIZE 1578 if(reselect_debug>1) 1579 for(i=0; i<bufptr; i++) 1580 printf("CSR:%02x", csrbuf[i]); 1581 #endif 1582 1583 #ifdef DEBUG 1584 if(data_pointer_debug > 1) 1585 printf("sbicicmd done(%d,%d):%d =%d=\n", 1586 dev->target, lun, 1587 acb->sc_kv.dc_count, 1588 dev->sc_stat[0]); 1589 #endif 1590 1591 QPRINTF(("=STS:%02x=", dev->sc_stat[0])); 1592 dev->sc_flags &= ~SBICF_ICMD; 1593 1594 SBIC_TRACE(dev); 1595 return(dev->sc_stat[0]); 1596 } 1597 1598 /* 1599 * Finish SCSI xfer command: After the completion interrupt from 1600 * a read/write operation, sequence through the final phases in 1601 * programmed i/o. This routine is a lot like sbicicmd except we 1602 * skip (and don't allow) the select, cmd out and data in/out phases. 1603 */ 1604 void 1605 sbicxfdone(dev, regs, target) 1606 struct sbic_softc *dev; 1607 sbic_regmap_t regs; 1608 int target; 1609 { 1610 u_char phase, asr, csr; 1611 int s; 1612 1613 SBIC_TRACE(dev); 1614 QPRINTF(("{")); 1615 s = splbio(); 1616 1617 /* 1618 * have the sbic complete on its own 1619 */ 1620 SBIC_TC_PUT(regs, 0); 1621 SET_SBIC_cmd_phase(regs, 0x46); 1622 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1623 1624 do { 1625 asr = SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1626 GET_SBIC_csr (regs, csr); 1627 CSR_TRACE('f',csr,asr,target); 1628 QPRINTF(("%02x:", csr)); 1629 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 1630 && (csr != SBIC_CSR_S_XFERRED)); 1631 1632 dev->sc_flags &= ~SBICF_SELECTED; 1633 1634 GET_SBIC_cmd_phase (regs, phase); 1635 QPRINTF(("}%02x", phase)); 1636 if (phase == 0x60) 1637 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1638 else 1639 sbicerror(dev, regs, csr); 1640 1641 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1642 splx(s); 1643 SBIC_TRACE(dev); 1644 } 1645 1646 /* 1647 * No DMA chains 1648 */ 1649 1650 int 1651 sbicgo(dev, xs) 1652 struct sbic_softc *dev; 1653 struct scsipi_xfer *xs; 1654 { 1655 int i, dmaflags, count, usedma; 1656 u_char csr, asr, *addr; 1657 sbic_regmap_t regs; 1658 struct sbic_acb *acb; 1659 1660 SBIC_TRACE(dev); 1661 dev->target = xs->sc_link->scsipi_scsi.target; 1662 dev->lun = xs->sc_link->scsipi_scsi.lun; 1663 acb = dev->sc_nexus; 1664 regs = dev->sc_sbic; 1665 1666 usedma = sbicdmaok(dev, xs); 1667 #ifdef DEBUG 1668 routine = 1; 1669 debug_sbic_regs = regs; /* store this to allow debug calls */ 1670 if( data_pointer_debug > 1 ) 1671 printf("sbicgo(%d,%d)\n", dev->target, dev->lun); 1672 #endif 1673 1674 /* 1675 * set the sbic into DMA mode 1676 */ 1677 if( usedma ) 1678 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 1679 SBIC_MACHINE_DMA_MODE); 1680 else 1681 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1682 1683 1684 /* 1685 * select the SCSI bus (it's an error if bus isn't free) 1686 */ 1687 if (sbicselectbus(dev, regs, dev->target, dev->lun, 1688 dev->sc_scsiaddr)) { 1689 /* printf("sbicgo: Trying to select busy bus!\n"); */ 1690 SBIC_TRACE(dev); 1691 return(0); /* Not done: needs to be rescheduled */ 1692 } 1693 dev->sc_stat[0] = 0xff; 1694 1695 /* 1696 * Calculate DMA chains now 1697 */ 1698 1699 dmaflags = 0; 1700 if (acb->flags & ACB_DATAIN) 1701 dmaflags |= DMAGO_READ; 1702 1703 1704 /* 1705 * Deal w/bounce buffers. 1706 */ 1707 1708 addr = acb->sc_kv.dc_addr; 1709 count = acb->sc_kv.dc_count; 1710 if (count && (char *)kvtop(addr) != acb->sc_pa.dc_addr) { /* XXXX check */ 1711 printf("sbic: DMA buffer mapping changed %p->%x\n", 1712 acb->sc_pa.dc_addr, kvtop(addr)); 1713 #ifdef DDB 1714 Debugger(); 1715 #endif 1716 } 1717 1718 #ifdef DEBUG 1719 ++sbicdma_ops; /* count total DMA operations */ 1720 #endif 1721 if (count && usedma && dev->sc_flags & SBICF_BADDMA && 1722 sbiccheckdmap(addr, count, dev->sc_dmamask)) { 1723 /* 1724 * need to bounce the dma. 1725 */ 1726 if (dmaflags & DMAGO_READ) { 1727 acb->flags |= ACB_BBUF; 1728 acb->sc_dmausrbuf = addr; 1729 acb->sc_dmausrlen = count; 1730 acb->sc_usrbufpa = (u_char *)kvtop(addr); 1731 if(!dev->sc_tinfo[dev->target].bounce) { 1732 printf("sbicgo: HELP! no bounce allocated for %d\n", 1733 dev->target); 1734 printf("xfer: (%p->%p,%lx)\n", acb->sc_dmausrbuf, 1735 acb->sc_usrbufpa, acb->sc_dmausrlen); 1736 dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce 1737 = (char *)alloc_z2mem(MAXPHYS); 1738 if (isztwomem(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)) 1739 printf("alloc ZII target %d bounce pa 0x%x\n", 1740 xs->sc_link->scsipi_scsi.target, 1741 kvtop(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1742 else if (dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce) 1743 printf("alloc CHIP target %d bounce pa 0x%p\n", 1744 xs->sc_link->scsipi_scsi.target, 1745 PREP_DMA_MEM(dev->sc_tinfo[xs->sc_link->scsipi_scsi.target].bounce)); 1746 1747 printf("Allocating %d bounce at %x\n", 1748 dev->target, 1749 kvtop(dev->sc_tinfo[dev->target].bounce)); 1750 } 1751 } else { /* write: copy to dma buffer */ 1752 #ifdef DEBUG 1753 if(data_pointer_debug) 1754 printf("sbicgo: copying %x bytes to target %d bounce %x\n", 1755 count, dev->target, 1756 kvtop(dev->sc_tinfo[dev->target].bounce)); 1757 #endif 1758 bcopy (addr, dev->sc_tinfo[dev->target].bounce, count); 1759 } 1760 addr = dev->sc_tinfo[dev->target].bounce;/* and use dma buffer */ 1761 acb->sc_kv.dc_addr = addr; 1762 #ifdef DEBUG 1763 ++sbicdma_bounces; /* count number of bounced */ 1764 #endif 1765 } 1766 1767 /* 1768 * Allocate the DMA chain 1769 */ 1770 1771 /* Set start KVM addresses */ 1772 #if 0 1773 acb->sc_kv.dc_addr = addr; 1774 acb->sc_kv.dc_count = count; 1775 #endif 1776 1777 /* Mark end of segment */ 1778 acb->sc_tcnt = dev->sc_tcnt = 0; 1779 acb->sc_pa.dc_count = 0; 1780 1781 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 1782 SBIC_TRACE(dev); 1783 /* Enable interrupts but don't do any DMA */ 1784 dev->sc_enintr(dev); 1785 if (usedma) { 1786 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1787 acb->sc_pa.dc_count, 1788 dmaflags); 1789 #ifdef DEBUG 1790 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1791 #endif 1792 } else 1793 dev->sc_dmacmd = 0; /* Don't use DMA */ 1794 dev->sc_flags |= SBICF_INDMA; 1795 /* SBIC_TC_PUT(regs, dev->sc_tcnt); */ /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */ 1796 SBIC_TRACE(dev); 1797 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1798 1799 /* 1800 * push the data cache ( I think this won't work (EH)) 1801 */ 1802 #if defined(M68040) || defined(M68060) 1803 if (mmutype == MMU_68040 && usedma && count) { 1804 dma_cachectl(addr, count); 1805 if (((u_int)addr & 0xF) || (((u_int)addr + count) & 0xF)) 1806 dev->sc_flags |= SBICF_DCFLUSH; 1807 } 1808 #endif 1809 1810 /* 1811 * enintr() also enables interrupts for the sbic 1812 */ 1813 #ifdef DEBUG 1814 if( data_pointer_debug > 1 ) 1815 printf("sbicgo dmago:%d(%p:%lx)\n", 1816 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 1817 #if 0 1818 /* 1819 * Hmm - this isn't right: asr and csr haven't been set yet. 1820 */ 1821 debug_asr = asr; 1822 debug_csr = csr; 1823 #endif 1824 #endif 1825 1826 /* 1827 * Lets cycle a while then let the interrupt handler take over 1828 */ 1829 1830 asr = GET_SBIC_asr(regs, asr); 1831 do { 1832 GET_SBIC_csr(regs, csr); 1833 CSR_TRACE('g',csr,asr,dev->target); 1834 #ifdef DEBUG 1835 debug_csr = csr; 1836 routine = 1; 1837 #endif 1838 QPRINTF(("go[0x%x]", csr)); 1839 1840 i = sbicnextstate(dev, csr, asr); 1841 1842 WAIT_CIP(regs); 1843 GET_SBIC_asr(regs, asr); 1844 #ifdef DEBUG 1845 debug_asr = asr; 1846 #endif 1847 if(asr & SBIC_ASR_LCI) printf("sbicgo: LCI asr:%02x csr:%02x\n", 1848 asr,csr); 1849 } while( i == SBIC_STATE_RUNNING 1850 && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1851 1852 CSR_TRACE('g',csr,asr,i<<4); 1853 SBIC_TRACE(dev); 1854 if (i == SBIC_STATE_DONE && dev->sc_stat[0] == 0xff) printf("sbicgo: done & stat = 0xff\n"); 1855 if (i == SBIC_STATE_DONE && dev->sc_stat[0] != 0xff) { 1856 /* if( i == SBIC_STATE_DONE && dev->sc_stat[0] ) { */ 1857 /* Did we really finish that fast? */ 1858 return 1; 1859 } 1860 return 0; 1861 } 1862 1863 1864 int 1865 sbicintr(dev) 1866 struct sbic_softc *dev; 1867 { 1868 sbic_regmap_t regs; 1869 u_char asr, csr; 1870 int i; 1871 1872 regs = dev->sc_sbic; 1873 1874 /* 1875 * pending interrupt? 1876 */ 1877 GET_SBIC_asr (regs, asr); 1878 if ((asr & SBIC_ASR_INT) == 0) 1879 return(0); 1880 1881 SBIC_TRACE(dev); 1882 do { 1883 GET_SBIC_csr(regs, csr); 1884 CSR_TRACE('i',csr,asr,dev->target); 1885 #ifdef DEBUG 1886 debug_csr = csr; 1887 routine = 2; 1888 #endif 1889 QPRINTF(("intr[0x%x]", csr)); 1890 1891 i = sbicnextstate(dev, csr, asr); 1892 1893 WAIT_CIP(regs); 1894 GET_SBIC_asr(regs, asr); 1895 #ifdef DEBUG 1896 debug_asr = asr; 1897 #endif 1898 #if 0 1899 if(asr & SBIC_ASR_LCI) printf("sbicintr: LCI asr:%02x csr:%02x\n", 1900 asr,csr); 1901 #endif 1902 } while(i == SBIC_STATE_RUNNING && 1903 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1904 CSR_TRACE('i',csr,asr,i<<4); 1905 SBIC_TRACE(dev); 1906 return(1); 1907 } 1908 1909 /* 1910 * Run commands and wait for disconnect 1911 */ 1912 int 1913 sbicpoll(dev) 1914 struct sbic_softc *dev; 1915 { 1916 sbic_regmap_t regs; 1917 u_char asr, csr; 1918 int i; 1919 1920 SBIC_TRACE(dev); 1921 regs = dev->sc_sbic; 1922 1923 do { 1924 GET_SBIC_asr (regs, asr); 1925 #ifdef DEBUG 1926 debug_asr = asr; 1927 #endif 1928 GET_SBIC_csr(regs, csr); 1929 CSR_TRACE('p',csr,asr,dev->target); 1930 #ifdef DEBUG 1931 debug_csr = csr; 1932 routine = 2; 1933 #endif 1934 QPRINTF(("poll[0x%x]", csr)); 1935 1936 i = sbicnextstate(dev, csr, asr); 1937 1938 WAIT_CIP(regs); 1939 GET_SBIC_asr(regs, asr); 1940 /* tapes may take a loooong time.. */ 1941 while (asr & SBIC_ASR_BSY){ 1942 if(asr & SBIC_ASR_DBR) { 1943 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", 1944 csr,asr); 1945 #ifdef DDB 1946 Debugger(); 1947 #endif 1948 /* SBIC is jammed */ 1949 /* DUNNO which direction */ 1950 /* Try old direction */ 1951 GET_SBIC_data(regs,i); 1952 GET_SBIC_asr(regs, asr); 1953 if( asr & SBIC_ASR_DBR) /* Wants us to write */ 1954 SET_SBIC_data(regs,i); 1955 } 1956 GET_SBIC_asr(regs, asr); 1957 } 1958 1959 if(asr & SBIC_ASR_LCI) printf("sbicpoll: LCI asr:%02x csr:%02x\n", 1960 asr,csr); 1961 else if( i == 1 ) /* BSY */ 1962 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1963 } while(i == SBIC_STATE_RUNNING); 1964 CSR_TRACE('p',csr,asr,i<<4); 1965 SBIC_TRACE(dev); 1966 return(1); 1967 } 1968 1969 /* 1970 * Handle a single msgin 1971 */ 1972 1973 int 1974 sbicmsgin(dev) 1975 struct sbic_softc *dev; 1976 { 1977 sbic_regmap_t regs; 1978 int recvlen; 1979 u_char asr, csr, *tmpaddr; 1980 1981 regs = dev->sc_sbic; 1982 1983 dev->sc_msg[0] = 0xff; 1984 dev->sc_msg[1] = 0xff; 1985 1986 GET_SBIC_asr(regs, asr); 1987 #ifdef DEBUG 1988 if(reselect_debug>1) 1989 printf("sbicmsgin asr=%02x\n", asr); 1990 #endif 1991 1992 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 1993 1994 GET_SBIC_selid (regs, csr); 1995 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1996 1997 SBIC_TC_PUT(regs, 0); 1998 tmpaddr = dev->sc_msg; 1999 recvlen = 1; 2000 do { 2001 while( recvlen-- ) { 2002 asr = GET_SBIC_asr(regs, asr); 2003 GET_SBIC_csr(regs, csr); 2004 QPRINTF(("sbicmsgin ready to go (csr,asr)=(%02x,%02x)\n", 2005 csr, asr)); 2006 2007 RECV_BYTE(regs, *tmpaddr); 2008 CSR_TRACE('m',csr,asr,*tmpaddr); 2009 #if 1 2010 /* 2011 * get the command completion interrupt, or we 2012 * can't send a new command (LCI) 2013 */ 2014 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2015 GET_SBIC_csr(regs, csr); 2016 CSR_TRACE('X',csr,asr,dev->target); 2017 #else 2018 WAIT_CIP(regs); 2019 do { 2020 GET_SBIC_asr(regs, asr); 2021 csr = 0xff; 2022 GET_SBIC_csr(regs, csr); 2023 CSR_TRACE('X',csr,asr,dev->target); 2024 if( csr == 0xff ) 2025 printf("sbicmsgin waiting: csr %02x asr %02x\n", csr, asr); 2026 } while( csr == 0xff ); 2027 #endif 2028 #ifdef DEBUG 2029 if(reselect_debug>1) 2030 printf("sbicmsgin: got %02x csr %02x asr %02x\n", 2031 *tmpaddr, csr, asr); 2032 #endif 2033 #if do_parity_check 2034 if( asr & SBIC_ASR_PE ) { 2035 printf ("Parity error"); 2036 /* This code simply does not work. */ 2037 WAIT_CIP(regs); 2038 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2039 WAIT_CIP(regs); 2040 GET_SBIC_asr(regs, asr); 2041 WAIT_CIP(regs); 2042 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2043 WAIT_CIP(regs); 2044 if( !(asr & SBIC_ASR_LCI) ) 2045 /* Target wants to send garbled msg*/ 2046 continue; 2047 printf("--fixing\n"); 2048 /* loop until a msgout phase occurs on target */ 2049 while(csr & 0x07 != MESG_OUT_PHASE) { 2050 while( asr & SBIC_ASR_BSY && 2051 !(asr & SBIC_ASR_DBR|SBIC_ASR_INT) ) 2052 GET_SBIC_asr(regs, asr); 2053 if( asr & SBIC_ASR_DBR ) 2054 panic("msgin: jammed again!\n"); 2055 GET_SBIC_csr(regs, csr); 2056 CSR_TRACE('e',csr,asr,dev->target); 2057 if( csr & 0x07 != MESG_OUT_PHASE ) { 2058 sbicnextstate(dev, csr, asr); 2059 sbic_save_ptrs(dev, regs, 2060 dev->target, 2061 dev->lun); 2062 } 2063 } 2064 /* Should be msg out by now */ 2065 SEND_BYTE(regs, MSG_PARITY_ERROR); 2066 } 2067 else 2068 #endif 2069 tmpaddr++; 2070 2071 if(recvlen) { 2072 /* Clear ACK */ 2073 WAIT_CIP(regs); 2074 GET_SBIC_asr(regs, asr); 2075 GET_SBIC_csr(regs, csr); 2076 CSR_TRACE('X',csr,asr,dev->target); 2077 QPRINTF(("sbicmsgin pre byte CLR_ACK (csr,asr)=(%02x,%02x)\n", 2078 csr, asr)); 2079 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2080 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2081 } 2082 2083 }; 2084 2085 if(dev->sc_msg[0] == 0xff) { 2086 printf("sbicmsgin: sbic swallowed our message\n"); 2087 break; 2088 } 2089 #ifdef DEBUG 2090 if (sync_debug) 2091 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", 2092 csr, asr, dev->sc_msg[0]); 2093 #endif 2094 /* 2095 * test whether this is a reply to our sync 2096 * request 2097 */ 2098 if (MSG_ISIDENTIFY(dev->sc_msg[0])) { 2099 QPRINTF(("IFFY")); 2100 #if 0 2101 /* There is an implied load-ptrs here */ 2102 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2103 #endif 2104 /* Got IFFY msg -- ack it */ 2105 } else if (dev->sc_msg[0] == MSG_REJECT 2106 && dev->sc_sync[dev->target].state == SYNC_SENT) { 2107 QPRINTF(("REJECT of SYN")); 2108 #ifdef DEBUG 2109 if (sync_debug) 2110 printf("target %d rejected sync, going async\n", 2111 dev->target); 2112 #endif 2113 dev->sc_sync[dev->target].period = sbic_min_period; 2114 dev->sc_sync[dev->target].offset = 0; 2115 dev->sc_sync[dev->target].state = SYNC_DONE; 2116 SET_SBIC_syn(regs, 2117 SBIC_SYN(dev->sc_sync[dev->target].offset, 2118 dev->sc_sync[dev->target].period)); 2119 } else if ((dev->sc_msg[0] == MSG_REJECT)) { 2120 QPRINTF(("REJECT")); 2121 /* 2122 * we'll never REJECt a REJECT message.. 2123 */ 2124 } else if ((dev->sc_msg[0] == MSG_SAVE_DATA_PTR)) { 2125 QPRINTF(("MSG_SAVE_DATA_PTR")); 2126 /* 2127 * don't reject this either. 2128 */ 2129 } else if ((dev->sc_msg[0] == MSG_DISCONNECT)) { 2130 QPRINTF(("DISCONNECT")); 2131 #ifdef DEBUG 2132 if( reselect_debug>1 && dev->sc_msg[0] == MSG_DISCONNECT ) 2133 printf("sbicmsgin: got disconnect msg %s\n", 2134 (dev->sc_flags & SBICF_ICMD)?"rejecting":""); 2135 #endif 2136 if( dev->sc_flags & SBICF_ICMD ) { 2137 /* We're in immediate mode. Prevent disconnects. */ 2138 /* prepare to reject the message, NACK */ 2139 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2140 WAIT_CIP(regs); 2141 } 2142 } else if (dev->sc_msg[0] == MSG_CMD_COMPLETE ) { 2143 QPRINTF(("CMD_COMPLETE")); 2144 /* !! KLUDGE ALERT !! quite a few drives don't seem to 2145 * really like the current way of sending the 2146 * sync-handshake together with the ident-message, and 2147 * they react by sending command-complete and 2148 * disconnecting right after returning the valid sync 2149 * handshake. So, all I can do is reselect the drive, 2150 * and hope it won't disconnect again. I don't think 2151 * this is valid behavior, but I can't help fixing a 2152 * problem that apparently exists. 2153 * 2154 * Note: we should not get here on `normal' command 2155 * completion, as that condition is handled by the 2156 * high-level sel&xfer resume command used to walk 2157 * thru status/cc-phase. 2158 */ 2159 2160 #ifdef DEBUG 2161 if (sync_debug) 2162 printf ("GOT MSG %d! target %d acting weird.." 2163 " waiting for disconnect...\n", 2164 dev->sc_msg[0], dev->target); 2165 #endif 2166 /* Check to see if sbic is handling this */ 2167 GET_SBIC_asr(regs, asr); 2168 if(asr & SBIC_ASR_BSY) 2169 return SBIC_STATE_RUNNING; 2170 2171 /* Let's try this: Assume it works and set status to 00 */ 2172 dev->sc_stat[0] = 0; 2173 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE 2174 && tmpaddr == &dev->sc_msg[1]) { 2175 QPRINTF(("ExtMSG\n")); 2176 /* Read in whole extended message */ 2177 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2178 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2179 GET_SBIC_asr(regs, asr); 2180 GET_SBIC_csr(regs, csr); 2181 QPRINTF(("CLR ACK asr %02x, csr %02x\n", asr, csr)); 2182 RECV_BYTE(regs, *tmpaddr); 2183 CSR_TRACE('x',csr,asr,*tmpaddr); 2184 /* Wait for command completion IRQ */ 2185 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2186 recvlen = *tmpaddr++; 2187 QPRINTF(("Recving ext msg, asr %02x csr %02x len %02x\n", 2188 asr, csr, recvlen)); 2189 } else if (dev->sc_msg[0] == MSG_EXT_MESSAGE && dev->sc_msg[1] == 3 2190 && dev->sc_msg[2] == MSG_SYNC_REQ) { 2191 QPRINTF(("SYN")); 2192 dev->sc_sync[dev->target].period = 2193 sbicfromscsiperiod(dev, 2194 regs, dev->sc_msg[3]); 2195 dev->sc_sync[dev->target].offset = dev->sc_msg[4]; 2196 dev->sc_sync[dev->target].state = SYNC_DONE; 2197 SET_SBIC_syn(regs, 2198 SBIC_SYN(dev->sc_sync[dev->target].offset, 2199 dev->sc_sync[dev->target].period)); 2200 printf("%s: target %d now synchronous," 2201 " period=%dns, offset=%d.\n", 2202 dev->sc_dev.dv_xname, dev->target, 2203 dev->sc_msg[3] * 4, dev->sc_msg[4]); 2204 } else { 2205 #ifdef DEBUG 2206 if (sbic_debug || sync_debug) 2207 printf ("sbicmsgin: Rejecting message 0x%02x\n", 2208 dev->sc_msg[0]); 2209 #endif 2210 /* prepare to reject the message, NACK */ 2211 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2212 WAIT_CIP(regs); 2213 } 2214 /* Clear ACK */ 2215 WAIT_CIP(regs); 2216 GET_SBIC_asr(regs, asr); 2217 GET_SBIC_csr(regs, csr); 2218 CSR_TRACE('X',csr,asr,dev->target); 2219 QPRINTF(("sbicmsgin pre CLR_ACK (csr,asr)=(%02x,%02x)%d\n", 2220 csr, asr, recvlen)); 2221 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2222 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2223 } 2224 #if 0 2225 while((csr == SBIC_CSR_MSGIN_W_ACK) 2226 || (SBIC_PHASE(csr) == MESG_IN_PHASE)); 2227 #else 2228 while (recvlen>0); 2229 #endif 2230 2231 QPRINTF(("sbicmsgin finished: csr %02x, asr %02x\n",csr, asr)); 2232 2233 /* Should still have one CSR to read */ 2234 return SBIC_STATE_RUNNING; 2235 } 2236 2237 2238 /* 2239 * sbicnextstate() 2240 * return: 2241 * 0 == done 2242 * 1 == working 2243 * 2 == disconnected 2244 * -1 == error 2245 */ 2246 int 2247 sbicnextstate(dev, csr, asr) 2248 struct sbic_softc *dev; 2249 u_char csr, asr; 2250 { 2251 sbic_regmap_t regs; 2252 struct sbic_acb *acb; 2253 int i, newtarget, newlun, wait; 2254 #if 0 2255 unsigned tcnt; 2256 #endif 2257 2258 i = 0; 2259 SBIC_TRACE(dev); 2260 regs = dev->sc_sbic; 2261 acb = dev->sc_nexus; 2262 2263 QPRINTF(("next[%02x,%02x]",asr,csr)); 2264 2265 switch (csr) { 2266 case SBIC_CSR_XFERRED|CMD_PHASE: 2267 case SBIC_CSR_MIS|CMD_PHASE: 2268 case SBIC_CSR_MIS_1|CMD_PHASE: 2269 case SBIC_CSR_MIS_2|CMD_PHASE: 2270 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2271 if (sbicxfstart(regs, acb->clen, CMD_PHASE, sbic_cmd_wait)) 2272 if (sbicxfout(regs, acb->clen, 2273 &acb->cmd, CMD_PHASE)) 2274 goto abort; 2275 break; 2276 2277 case SBIC_CSR_XFERRED|STATUS_PHASE: 2278 case SBIC_CSR_MIS|STATUS_PHASE: 2279 case SBIC_CSR_MIS_1|STATUS_PHASE: 2280 case SBIC_CSR_MIS_2|STATUS_PHASE: 2281 /* 2282 * this should be the normal i/o completion case. 2283 * get the status & cmd complete msg then let the 2284 * device driver look at what happened. 2285 */ 2286 sbicxfdone(dev,regs,dev->target); 2287 /* 2288 * check for overlapping cache line, flush if so 2289 */ 2290 #if defined(M68040) || defined(M68060) 2291 if (dev->sc_flags & SBICF_DCFLUSH) { 2292 #if 0 2293 printf("sbic: 68040/68060 DMA cache flush needs" 2294 "fixing? %x:%x\n", 2295 dev->sc_xs->data, dev->sc_xs->datalen); 2296 #endif 2297 } 2298 #endif 2299 #ifdef DEBUG 2300 if( data_pointer_debug > 1 ) 2301 printf("next dmastop: %d(%p:%lx)\n", 2302 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2303 dev->sc_dmatimo = 0; 2304 #endif 2305 dev->sc_dmastop(dev); /* was dmafree */ 2306 if (acb->flags & ACB_BBUF) { 2307 if ((u_char *)kvtop(acb->sc_dmausrbuf) != acb->sc_usrbufpa) 2308 printf("%s: WARNING - buffer mapping changed %p->%x\n", 2309 dev->sc_dev.dv_xname, acb->sc_usrbufpa, 2310 kvtop(acb->sc_dmausrbuf)); 2311 #ifdef DEBUG 2312 if(data_pointer_debug) 2313 printf("sbicgo:copying %lx bytes from target %d bounce %x\n", 2314 acb->sc_dmausrlen, 2315 dev->target, 2316 kvtop(dev->sc_tinfo[dev->target].bounce)); 2317 #endif 2318 bcopy(dev->sc_tinfo[dev->target].bounce, 2319 acb->sc_dmausrbuf, 2320 acb->sc_dmausrlen); 2321 } 2322 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2323 sbic_scsidone(acb, dev->sc_stat[0]); 2324 SBIC_TRACE(dev); 2325 return SBIC_STATE_DONE; 2326 2327 case SBIC_CSR_XFERRED|DATA_OUT_PHASE: 2328 case SBIC_CSR_XFERRED|DATA_IN_PHASE: 2329 case SBIC_CSR_MIS|DATA_OUT_PHASE: 2330 case SBIC_CSR_MIS|DATA_IN_PHASE: 2331 case SBIC_CSR_MIS_1|DATA_OUT_PHASE: 2332 case SBIC_CSR_MIS_1|DATA_IN_PHASE: 2333 case SBIC_CSR_MIS_2|DATA_OUT_PHASE: 2334 case SBIC_CSR_MIS_2|DATA_IN_PHASE: 2335 if( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD 2336 || acb->sc_dmacmd == 0 ) { 2337 /* Do PIO */ 2338 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2339 if (acb->sc_kv.dc_count <= 0) { 2340 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2341 acb->sc_kv.dc_count, asr, csr); 2342 goto abort; 2343 } 2344 wait = sbic_data_wait; 2345 if( sbicxfstart(regs, 2346 acb->sc_kv.dc_count, 2347 SBIC_PHASE(csr), wait)) { 2348 if( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2349 /* data in? */ 2350 i=sbicxfin(regs, 2351 acb->sc_kv.dc_count, 2352 acb->sc_kv.dc_addr); 2353 else 2354 i=sbicxfout(regs, 2355 acb->sc_kv.dc_count, 2356 acb->sc_kv.dc_addr, 2357 SBIC_PHASE(csr)); 2358 } 2359 acb->sc_kv.dc_addr += 2360 (acb->sc_kv.dc_count - i); 2361 acb->sc_kv.dc_count = i; 2362 } else { 2363 if (acb->sc_kv.dc_count <= 0) { 2364 printf("sbicnextstate:xfer count %d asr%x csr%x\n", 2365 acb->sc_kv.dc_count, asr, csr); 2366 goto abort; 2367 } 2368 /* 2369 * do scatter-gather dma 2370 * hacking the controller chip, ouch.. 2371 */ 2372 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2373 SBIC_MACHINE_DMA_MODE); 2374 /* 2375 * set next dma addr and dec count 2376 */ 2377 #if 0 2378 SBIC_TC_GET(regs, tcnt); 2379 dev->sc_cur->dc_count -= ((dev->sc_tcnt - tcnt) >> 1); 2380 dev->sc_cur->dc_addr += (dev->sc_tcnt - tcnt); 2381 dev->sc_tcnt = acb->sc_tcnt = tcnt; 2382 #else 2383 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2384 sbic_load_ptrs(dev, regs, dev->target, dev->lun); 2385 #endif 2386 #ifdef DEBUG 2387 if( data_pointer_debug > 1 ) 2388 printf("next dmanext: %d(%p:%lx)\n", 2389 dev->target,dev->sc_cur->dc_addr, 2390 dev->sc_tcnt); 2391 dev->sc_dmatimo = 1; 2392 #endif 2393 dev->sc_tcnt = dev->sc_dmanext(dev); 2394 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2395 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2396 dev->sc_flags |= SBICF_INDMA; 2397 } 2398 break; 2399 2400 case SBIC_CSR_XFERRED|MESG_IN_PHASE: 2401 case SBIC_CSR_MIS|MESG_IN_PHASE: 2402 case SBIC_CSR_MIS_1|MESG_IN_PHASE: 2403 case SBIC_CSR_MIS_2|MESG_IN_PHASE: 2404 SBIC_TRACE(dev); 2405 return sbicmsgin(dev); 2406 2407 case SBIC_CSR_MSGIN_W_ACK: 2408 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2409 printf("Acking unknown msgin CSR:%02x",csr); 2410 break; 2411 2412 case SBIC_CSR_XFERRED|MESG_OUT_PHASE: 2413 case SBIC_CSR_MIS|MESG_OUT_PHASE: 2414 case SBIC_CSR_MIS_1|MESG_OUT_PHASE: 2415 case SBIC_CSR_MIS_2|MESG_OUT_PHASE: 2416 #ifdef DEBUG 2417 if (sync_debug) 2418 printf ("sending REJECT msg to last msg.\n"); 2419 #endif 2420 2421 sbic_save_ptrs(dev, regs, dev->target, dev->lun); 2422 /* 2423 * should only get here on reject, 2424 * since it's always US that 2425 * initiate a sync transfer 2426 */ 2427 SEND_BYTE(regs, MSG_REJECT); 2428 WAIT_CIP(regs); 2429 if( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI|SBIC_ASR_CIP) ) 2430 printf("next: REJECT sent asr %02x\n", asr); 2431 SBIC_TRACE(dev); 2432 return SBIC_STATE_RUNNING; 2433 2434 case SBIC_CSR_DISC: 2435 case SBIC_CSR_DISC_1: 2436 dev->sc_flags &= ~(SBICF_INDMA|SBICF_SELECTED); 2437 2438 /* Try to schedule another target */ 2439 #ifdef DEBUG 2440 if(reselect_debug>1) 2441 printf("sbicnext target %d disconnected\n", dev->target); 2442 #endif 2443 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2444 ++dev->sc_tinfo[dev->target].dconns; 2445 dev->sc_nexus = NULL; 2446 dev->sc_xs = NULL; 2447 2448 if( acb->xs->xs_control & XS_CTL_POLL 2449 || (dev->sc_flags & SBICF_ICMD) 2450 || !sbic_parallel_operations ) { 2451 SBIC_TRACE(dev); 2452 return SBIC_STATE_DISCONNECT; 2453 } 2454 sbic_sched(dev); 2455 SBIC_TRACE(dev); 2456 return SBIC_STATE_DISCONNECT; 2457 2458 case SBIC_CSR_RSLT_NI: 2459 case SBIC_CSR_RSLT_IFY: 2460 GET_SBIC_rselid(regs, newtarget); 2461 /* check SBIC_RID_SIV? */ 2462 newtarget &= SBIC_RID_MASK; 2463 if (csr == SBIC_CSR_RSLT_IFY) { 2464 /* Read IFY msg to avoid lockup */ 2465 GET_SBIC_data(regs, newlun); 2466 WAIT_CIP(regs); 2467 newlun &= SBIC_TLUN_MASK; 2468 CSR_TRACE('r',csr,asr,newtarget); 2469 } else { 2470 /* Need to get IFY message */ 2471 for (newlun = 256; newlun; --newlun) { 2472 GET_SBIC_asr(regs, asr); 2473 if (asr & SBIC_ASR_INT) 2474 break; 2475 delay(1); 2476 } 2477 newlun = 0; /* XXXX */ 2478 if ((asr & SBIC_ASR_INT) == 0) { 2479 #ifdef DEBUG 2480 if (reselect_debug) 2481 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2482 #endif 2483 } else { 2484 GET_SBIC_csr(regs,csr); 2485 CSR_TRACE('n',csr,asr,newtarget); 2486 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2487 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2488 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2489 sbicmsgin(dev); 2490 newlun = dev->sc_msg[0] & 7; 2491 } else { 2492 printf("RSLT_NI - not MESG_IN_PHASE %x\n", 2493 csr); 2494 } 2495 } 2496 } 2497 #ifdef DEBUG 2498 if(reselect_debug>1 || (reselect_debug && csr==SBIC_CSR_RSLT_NI)) 2499 printf("sbicnext: reselect %s from targ %d lun %d\n", 2500 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", 2501 newtarget, newlun); 2502 #endif 2503 if (dev->sc_nexus) { 2504 #ifdef DEBUG 2505 if (reselect_debug > 1) 2506 printf("%s: reselect %s with active command\n", 2507 dev->sc_dev.dv_xname, 2508 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2509 #ifdef DDB 2510 /* Debugger();*/ 2511 #endif 2512 #endif 2513 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2514 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2515 dev->sc_nexus = NULL; 2516 dev->sc_xs = NULL; 2517 } 2518 /* Reload sync values for this target */ 2519 if (dev->sc_sync[newtarget].state == SYNC_DONE) 2520 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2521 dev->sc_sync[newtarget].period)); 2522 else 2523 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2524 for (acb = dev->nexus_list.tqh_first; acb; 2525 acb = acb->chain.tqe_next) { 2526 if (acb->xs->sc_link->scsipi_scsi.target != newtarget || 2527 acb->xs->sc_link->scsipi_scsi.lun != newlun) 2528 continue; 2529 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2530 dev->sc_nexus = acb; 2531 dev->sc_xs = acb->xs; 2532 dev->sc_flags |= SBICF_SELECTED; 2533 dev->target = newtarget; 2534 dev->lun = newlun; 2535 break; 2536 } 2537 if (acb == NULL) { 2538 printf("%s: reselect %s targ %d not in nexus_list %p\n", 2539 dev->sc_dev.dv_xname, 2540 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2541 &dev->nexus_list.tqh_first); 2542 panic("bad reselect in sbic"); 2543 } 2544 if (csr == SBIC_CSR_RSLT_IFY) 2545 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2546 break; 2547 2548 default: 2549 abort: 2550 /* 2551 * Something unexpected happened -- deal with it. 2552 */ 2553 printf("sbicnextstate: aborting csr %02x asr %02x\n", csr, asr); 2554 #ifdef DDB 2555 Debugger(); 2556 #endif 2557 #ifdef DEBUG 2558 if( data_pointer_debug > 1 ) 2559 printf("next dmastop: %d(%p:%lx)\n", 2560 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2561 dev->sc_dmatimo = 0; 2562 #endif 2563 dev->sc_dmastop(dev); 2564 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2565 sbicerror(dev, regs, csr); 2566 sbicabort(dev, regs, "next"); 2567 if (dev->sc_flags & SBICF_INDMA) { 2568 /* 2569 * check for overlapping cache line, flush if so 2570 */ 2571 #if defined(M68040) || defined(M68060) 2572 if (dev->sc_flags & SBICF_DCFLUSH) { 2573 #if 0 2574 printf("sbic: 68040/060 DMA cache flush needs" 2575 "fixing? %x:%x\n", 2576 dev->sc_xs->data, dev->sc_xs->datalen); 2577 #endif 2578 } 2579 #endif 2580 dev->sc_flags &= 2581 ~(SBICF_INDMA | SBICF_DCFLUSH); 2582 #ifdef DEBUG 2583 if( data_pointer_debug > 1 ) 2584 printf("next dmastop: %d(%p:%lx)\n", 2585 dev->target,dev->sc_cur->dc_addr,dev->sc_tcnt); 2586 dev->sc_dmatimo = 0; 2587 #endif 2588 dev->sc_dmastop(dev); 2589 sbic_scsidone(acb, -1); 2590 } 2591 SBIC_TRACE(dev); 2592 return SBIC_STATE_ERROR; 2593 } 2594 2595 SBIC_TRACE(dev); 2596 return(SBIC_STATE_RUNNING); 2597 } 2598 2599 2600 /* 2601 * Check if DMA can not be used with specified buffer 2602 */ 2603 2604 int 2605 sbiccheckdmap(bp, len, mask) 2606 void *bp; 2607 u_long len, mask; 2608 { 2609 u_char *buffer; 2610 u_long phy_buf; 2611 u_long phy_len; 2612 2613 buffer = bp; 2614 2615 if (len == 0) 2616 return(0); 2617 2618 while (len) { 2619 phy_buf = kvtop(buffer); 2620 if (len < (phy_len = NBPG - ((int) buffer & PGOFSET))) 2621 phy_len = len; 2622 if (phy_buf & mask) 2623 return(1); 2624 buffer += phy_len; 2625 len -= phy_len; 2626 } 2627 return(0); 2628 } 2629 2630 int 2631 sbictoscsiperiod(dev, regs, a) 2632 struct sbic_softc *dev; 2633 sbic_regmap_t regs; 2634 int a; 2635 { 2636 unsigned int fs; 2637 2638 /* 2639 * cycle = DIV / (2*CLK) 2640 * DIV = FS+2 2641 * best we can do is 200ns at 20Mhz, 2 cycles 2642 */ 2643 2644 GET_SBIC_myid(regs,fs); 2645 fs = (fs >>6) + 2; /* DIV */ 2646 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2647 if (a < 2) a = 8; /* map to Cycles */ 2648 return ((fs*a)>>2); /* in 4 ns units */ 2649 } 2650 2651 int 2652 sbicfromscsiperiod(dev, regs, p) 2653 struct sbic_softc *dev; 2654 sbic_regmap_t regs; 2655 int p; 2656 { 2657 register unsigned int fs, ret; 2658 2659 /* Just the inverse of the above */ 2660 2661 GET_SBIC_myid(regs,fs); 2662 fs = (fs >>6) + 2; /* DIV */ 2663 fs = (fs * 10000) / (dev->sc_clkfreq<<1); /* Cycle, in ns */ 2664 2665 ret = p << 2; /* in ns units */ 2666 ret = ret / fs; /* in Cycles */ 2667 if (ret < sbic_min_period) 2668 return(sbic_min_period); 2669 2670 /* verify rounding */ 2671 if (sbictoscsiperiod(dev, regs, ret) < p) 2672 ret++; 2673 return (ret >= 8) ? 0 : ret; 2674 } 2675 2676 #ifdef DEBUG 2677 2678 void 2679 sbicdumpstate() 2680 { 2681 u_char csr, asr; 2682 2683 GET_SBIC_asr(debug_sbic_regs,asr); 2684 GET_SBIC_csr(debug_sbic_regs,csr); 2685 printf("%s: asr:csr(%02x:%02x)->(%02x:%02x)\n", 2686 (routine==1)?"sbicgo": 2687 (routine==2)?"sbicintr": 2688 (routine==3)?"sbicicmd": 2689 (routine==4)?"sbicnext":"unknown", 2690 debug_asr, debug_csr, asr, csr); 2691 2692 } 2693 2694 void 2695 sbictimeout(dev) 2696 struct sbic_softc *dev; 2697 { 2698 int s, asr; 2699 2700 s = splbio(); 2701 if (dev->sc_dmatimo) { 2702 if (dev->sc_dmatimo > 1) { 2703 printf("%s: dma timeout #%d\n", 2704 dev->sc_dev.dv_xname, dev->sc_dmatimo - 1); 2705 GET_SBIC_asr(dev->sc_sbic, asr); 2706 if( asr & SBIC_ASR_INT ) { 2707 /* We need to service a missed IRQ */ 2708 printf("Servicing a missed int:(%02x,%02x)->(%02x,??)\n", 2709 debug_asr, debug_csr, asr); 2710 sbicintr(dev); 2711 } 2712 sbicdumpstate(); 2713 } 2714 dev->sc_dmatimo++; 2715 } 2716 splx(s); 2717 callout_reset(&dev->sc_timo_ch, 30 * hz, 2718 (void *)sbictimeout, dev); 2719 } 2720 2721 void 2722 sbic_dump_acb(acb) 2723 struct sbic_acb *acb; 2724 { 2725 u_char *b = (u_char *) &acb->cmd; 2726 int i; 2727 2728 printf("acb@%p ", acb); 2729 if (acb->xs == NULL) { 2730 printf("<unused>\n"); 2731 return; 2732 } 2733 printf("(%d:%d) flags %2x clen %2d cmd ", 2734 acb->xs->sc_link->scsipi_scsi.target, 2735 acb->xs->sc_link->scsipi_scsi.lun, acb->flags, acb->clen); 2736 for (i = acb->clen; i; --i) 2737 printf(" %02x", *b++); 2738 printf("\n"); 2739 printf(" xs: %8p data %8p:%04x ", acb->xs, acb->xs->data, 2740 acb->xs->datalen); 2741 printf("va %8p:%04x ", acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 2742 printf("pa %8p:%04x tcnt %lx\n", acb->sc_pa.dc_addr, acb->sc_pa.dc_count, 2743 acb->sc_tcnt); 2744 } 2745 2746 void 2747 sbic_dump(dev) 2748 struct sbic_softc *dev; 2749 { 2750 sbic_regmap_t regs; 2751 u_char csr, asr; 2752 struct sbic_acb *acb; 2753 int s; 2754 int i; 2755 2756 s = splbio(); 2757 regs = dev->sc_sbic; 2758 #if CSR_TRACE_SIZE 2759 printf("csr trace: "); 2760 i = csr_traceptr; 2761 do { 2762 printf("%c%02x%02x%02x ", csr_trace[i].whr, 2763 csr_trace[i].csr, csr_trace[i].asr, csr_trace[i].xtn); 2764 switch(csr_trace[i].whr) { 2765 case 'g': 2766 printf("go "); break; 2767 case 's': 2768 printf("select "); break; 2769 case 'y': 2770 printf("select+ "); break; 2771 case 'i': 2772 printf("intr "); break; 2773 case 'f': 2774 printf("finish "); break; 2775 case '>': 2776 printf("out "); break; 2777 case '<': 2778 printf("in "); break; 2779 case 'm': 2780 printf("msgin "); break; 2781 case 'x': 2782 printf("msginx "); break; 2783 case 'X': 2784 printf("msginX "); break; 2785 case 'r': 2786 printf("reselect "); break; 2787 case 'I': 2788 printf("icmd "); break; 2789 case 'a': 2790 printf("abort "); break; 2791 default: 2792 printf("? "); 2793 } 2794 switch(csr_trace[i].csr) { 2795 case 0x11: 2796 printf("INITIATOR"); break; 2797 case 0x16: 2798 printf("S_XFERRED"); break; 2799 case 0x20: 2800 printf("MSGIN_ACK"); break; 2801 case 0x41: 2802 printf("DISC"); break; 2803 case 0x42: 2804 printf("SEL_TIMEO"); break; 2805 case 0x80: 2806 printf("RSLT_NI"); break; 2807 case 0x81: 2808 printf("RSLT_IFY"); break; 2809 case 0x85: 2810 printf("DISC_1"); break; 2811 case 0x18: case 0x19: case 0x1a: 2812 case 0x1b: case 0x1e: case 0x1f: 2813 case 0x28: case 0x29: case 0x2a: 2814 case 0x2b: case 0x2e: case 0x2f: 2815 case 0x48: case 0x49: case 0x4a: 2816 case 0x4b: case 0x4e: case 0x4f: 2817 case 0x88: case 0x89: case 0x8a: 2818 case 0x8b: case 0x8e: case 0x8f: 2819 switch(csr_trace[i].csr & 0xf0) { 2820 case 0x10: 2821 printf("DONE_"); break; 2822 case 0x20: 2823 printf("STOP_"); break; 2824 case 0x40: 2825 printf("ERR_"); break; 2826 case 0x80: 2827 printf("REQ_"); break; 2828 } 2829 switch(csr_trace[i].csr & 7) { 2830 case 0: 2831 printf("DATA_OUT"); break; 2832 case 1: 2833 printf("DATA_IN"); break; 2834 case 2: 2835 printf("CMD"); break; 2836 case 3: 2837 printf("STATUS"); break; 2838 case 6: 2839 printf("MSG_OUT"); break; 2840 case 7: 2841 printf("MSG_IN"); break; 2842 default: 2843 printf("invld phs"); 2844 } 2845 break; 2846 default: printf("****"); break; 2847 } 2848 if (csr_trace[i].asr & SBIC_ASR_INT) 2849 printf(" ASR_INT"); 2850 if (csr_trace[i].asr & SBIC_ASR_LCI) 2851 printf(" ASR_LCI"); 2852 if (csr_trace[i].asr & SBIC_ASR_BSY) 2853 printf(" ASR_BSY"); 2854 if (csr_trace[i].asr & SBIC_ASR_CIP) 2855 printf(" ASR_CIP"); 2856 printf("\n"); 2857 i = (i + 1) & (CSR_TRACE_SIZE - 1); 2858 } while (i != csr_traceptr); 2859 #endif 2860 GET_SBIC_asr(regs, asr); 2861 if ((asr & SBIC_ASR_INT) == 0) 2862 GET_SBIC_csr(regs, csr); 2863 else 2864 csr = 0; 2865 printf("%s@%p regs %p/%p asr %x csr %x\n", dev->sc_dev.dv_xname, 2866 dev, regs.sbic_asr_p, regs.sbic_value_p, asr, csr); 2867 if ((acb = dev->free_list.tqh_first)) { 2868 printf("Free list:\n"); 2869 while (acb) { 2870 sbic_dump_acb(acb); 2871 acb = acb->chain.tqe_next; 2872 } 2873 } 2874 if ((acb = dev->ready_list.tqh_first)) { 2875 printf("Ready list:\n"); 2876 while (acb) { 2877 sbic_dump_acb(acb); 2878 acb = acb->chain.tqe_next; 2879 } 2880 } 2881 if ((acb = dev->nexus_list.tqh_first)) { 2882 printf("Nexus list:\n"); 2883 while (acb) { 2884 sbic_dump_acb(acb); 2885 acb = acb->chain.tqe_next; 2886 } 2887 } 2888 if (dev->sc_nexus) { 2889 printf("nexus:\n"); 2890 sbic_dump_acb(dev->sc_nexus); 2891 } 2892 printf("sc_xs %p targ %d lun %d flags %x tcnt %lx dmacmd %x mask %lx\n", 2893 dev->sc_xs, dev->target, dev->lun, dev->sc_flags, dev->sc_tcnt, 2894 dev->sc_dmacmd, dev->sc_dmamask); 2895 for (i = 0; i < 8; ++i) { 2896 if (dev->sc_tinfo[i].cmds > 2) { 2897 printf("tgt %d: cmds %d disc %d senses %d lubusy %x\n", 2898 i, dev->sc_tinfo[i].cmds, 2899 dev->sc_tinfo[i].dconns, 2900 dev->sc_tinfo[i].senses, 2901 dev->sc_tinfo[i].lubusy); 2902 } 2903 } 2904 splx(s); 2905 } 2906 2907 #endif 2908