xref: /netbsd-src/sys/arch/amiga/dev/mlhsc.c (revision 1ca5c1b28139779176bd5c13ad7c5f25c0bcd5f8)
1 /*	$NetBSD: mlhsc.c,v 1.23 2001/04/25 17:53:07 bouyer Exp $	*/
2 
3 /*
4  * Copyright (c) 1994 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by the University of
19  *	California, Berkeley and its contributors.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  *	@(#)dma.c
37  */
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/device.h>
42 #include <dev/scsipi/scsi_all.h>
43 #include <dev/scsipi/scsipi_all.h>
44 #include <dev/scsipi/scsiconf.h>
45 #include <amiga/amiga/device.h>
46 #include <amiga/amiga/isr.h>
47 #include <amiga/dev/scireg.h>
48 #include <amiga/dev/scivar.h>
49 #include <amiga/dev/zbusvar.h>
50 
51 void mlhscattach __P((struct device *, struct device *, void *));
52 int mlhscmatch __P((struct device *, struct cfdata *, void *));
53 
54 int mlhsc_dma_xfer_in __P((struct sci_softc *dev, int len,
55     register u_char *buf, int phase));
56 int mlhsc_dma_xfer_out __P((struct sci_softc *dev, int len,
57     register u_char *buf, int phase));
58 
59 #ifdef DEBUG
60 extern int sci_debug;
61 #define QPRINTF(a) if (sci_debug > 1) printf a
62 #else
63 #define QPRINTF(a)
64 #endif
65 
66 extern int sci_data_wait;
67 
68 struct cfattach mlhsc_ca = {
69 	sizeof(struct sci_softc), mlhscmatch, mlhscattach
70 };
71 
72 /*
73  * if we are my Hacker's SCSI board we are here.
74  */
75 int
76 mlhscmatch(pdp, cfp, auxp)
77 	struct device *pdp;
78 	struct cfdata *cfp;
79 	void *auxp;
80 {
81 	struct zbus_args *zap;
82 
83 	zap = auxp;
84 
85 	/*
86 	 * Check manufacturer and product id.
87 	 */
88 	if (zap->manid == 2011 && zap->prodid == 1)
89 		return(1);
90 	else
91 		return(0);
92 }
93 
94 void
95 mlhscattach(pdp, dp, auxp)
96 	struct device *pdp, *dp;
97 	void *auxp;
98 {
99 	volatile u_char *rp;
100 	struct sci_softc *sc = (struct sci_softc *)dp;
101 	struct zbus_args *zap;
102 	struct scsipi_adapter *adapt = &sc->sc_adapter;
103 	struct scsipi_channel *chan = &sc->sc_channel;
104 
105 	printf("\n");
106 
107 	zap = auxp;
108 
109 	sc = (struct sci_softc *)dp;
110 	rp = zap->va;
111 	sc->sci_data = rp + 1;
112 	sc->sci_odata = rp + 1;
113 	sc->sci_icmd = rp + 3;
114 	sc->sci_mode = rp + 5;
115 	sc->sci_tcmd = rp + 7;
116 	sc->sci_bus_csr = rp + 9;
117 	sc->sci_sel_enb = rp + 9;
118 	sc->sci_csr = rp + 11;
119 	sc->sci_dma_send = rp + 11;
120 	sc->sci_idata = rp + 13;
121 	sc->sci_trecv = rp + 13;
122 	sc->sci_iack = rp + 15;
123 	sc->sci_irecv = rp + 15;
124 
125 	sc->dma_xfer_in = mlhsc_dma_xfer_in;
126 	sc->dma_xfer_out = mlhsc_dma_xfer_out;
127 
128 	scireset(sc);
129 
130 	/*
131 	 * Fill in the scsipi_adapter.
132 	 */
133 	memset(adapt, 0, sizeof(*adapt));
134 	adapt->adapt_dev = &sc->sc_dev;
135 	adapt->adapt_nchannels = 1;
136 	adapt->adapt_openings = 7;
137 	adapt->adapt_max_periph = 1;
138 	adapt->adapt_request = sci_scsipi_request;
139 	adapt->adapt_minphys = sci_minphys;
140 
141 	/*
142 	 * Fill in the scsipi_channel.
143 	 */
144 	memset(chan, 0, sizeof(*chan));
145 	chan->chan_adapter = adapt;
146 	chan->chan_bustype = &scsi_bustype;
147 	chan->chan_channel = 0;
148 	chan->chan_ntargets = 8;
149 	chan->chan_nluns = 8;
150 	chan->chan_id = 7;
151 
152 	/*
153 	 * attach all scsi units on us
154 	 */
155 	config_found(dp, chan, scsiprint);
156 }
157 
158 int
159 mlhsc_dma_xfer_in (dev, len, buf, phase)
160 	struct sci_softc *dev;
161 	int len;
162 	register u_char *buf;
163 	int phase;
164 {
165 	int wait = sci_data_wait;
166 	u_char csr;
167 	volatile register u_char *sci_dma = dev->sci_data + 16;
168 	volatile register u_char *sci_csr = dev->sci_csr;
169 #ifdef DEBUG
170 	u_char *obp = buf;
171 #endif
172 
173 	csr = *dev->sci_bus_csr;
174 
175 	QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr));
176 
177 	*dev->sci_tcmd = phase;
178 	*dev->sci_mode |= SCI_MODE_DMA;
179 	*dev->sci_icmd = 0;
180 	*dev->sci_irecv = 0;
181 	while (len > 128) {
182 		wait = sci_data_wait;
183 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
184 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
185 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
186 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
187 			  || --wait < 0) {
188 #ifdef DEBUG
189 				if (sci_debug)
190 					printf("mlhdma_in fail: l%d i%x w%d\n",
191 					len, csr, wait);
192 #endif
193 				*dev->sci_mode &= ~SCI_MODE_DMA;
194 				return 0;
195 			}
196 		}
197 
198 #define R1	(*buf++ = *sci_dma)
199 		R1; R1; R1; R1; R1; R1; R1; R1;
200 		R1; R1; R1; R1; R1; R1; R1; R1;
201 		R1; R1; R1; R1; R1; R1; R1; R1;
202 		R1; R1; R1; R1; R1; R1; R1; R1;
203 		R1; R1; R1; R1; R1; R1; R1; R1;
204 		R1; R1; R1; R1; R1; R1; R1; R1;
205 		R1; R1; R1; R1; R1; R1; R1; R1;
206 		R1; R1; R1; R1; R1; R1; R1; R1;
207 		R1; R1; R1; R1; R1; R1; R1; R1;
208 		R1; R1; R1; R1; R1; R1; R1; R1;
209 		R1; R1; R1; R1; R1; R1; R1; R1;
210 		R1; R1; R1; R1; R1; R1; R1; R1;
211 		R1; R1; R1; R1; R1; R1; R1; R1;
212 		R1; R1; R1; R1; R1; R1; R1; R1;
213 		R1; R1; R1; R1; R1; R1; R1; R1;
214 		R1; R1; R1; R1; R1; R1; R1; R1;
215 		len -= 128;
216 	}
217 	while (len > 0) {
218 		wait = sci_data_wait;
219 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
220 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
221 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
222 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
223 			  || --wait < 0) {
224 #ifdef DEBUG
225 				if (sci_debug)
226 					printf("mlhdma_in fail: l%d i%x w%d\n",
227 					len, csr, wait);
228 #endif
229 				*dev->sci_mode &= ~SCI_MODE_DMA;
230 				return 0;
231 			}
232 		}
233 
234 		*buf++ = *sci_dma;
235 		len--;
236 	}
237 
238 	QPRINTF(("mlhdma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
239 	  len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
240 	  obp[6], obp[7], obp[8], obp[9]));
241 
242 	*dev->sci_mode &= ~SCI_MODE_DMA;
243 	return 0;
244 }
245 
246 int
247 mlhsc_dma_xfer_out (dev, len, buf, phase)
248 	struct sci_softc *dev;
249 	int len;
250 	register u_char *buf;
251 	int phase;
252 {
253 	int wait = sci_data_wait;
254 	u_char csr;
255 	volatile register u_char *sci_dma = dev->sci_data + 16;
256 	volatile register u_char *sci_csr = dev->sci_csr;
257 
258 	csr = *dev->sci_bus_csr;
259 
260 	QPRINTF(("mlhdma_xfer %d, csr=%02x\n", len, csr));
261 
262 	QPRINTF(("mlhgdma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
263   	 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
264 	 buf[6], buf[7], buf[8], buf[9]));
265 
266 	*dev->sci_tcmd = phase;
267 	*dev->sci_mode |= SCI_MODE_DMA;
268 	*dev->sci_icmd = SCI_ICMD_DATA;
269 	*dev->sci_dma_send = 0;
270 	while (len > 64) {
271 		wait = sci_data_wait;
272 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
273 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
274 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
275 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
276 			  || --wait < 0) {
277 #ifdef DEBUG
278 				if (sci_debug)
279 					printf("mlhdma_out fail: l%d i%x w%d\n",
280 					len, csr, wait);
281 #endif
282 				*dev->sci_mode &= ~SCI_MODE_DMA;
283 				return 0;
284 			}
285 		}
286 
287 #define W1	(*sci_dma = *buf++)
288 		W1; W1; W1; W1; W1; W1; W1; W1;
289 		W1; W1; W1; W1; W1; W1; W1; W1;
290 		W1; W1; W1; W1; W1; W1; W1; W1;
291 		W1; W1; W1; W1; W1; W1; W1; W1;
292 		W1; W1; W1; W1; W1; W1; W1; W1;
293 		W1; W1; W1; W1; W1; W1; W1; W1;
294 		W1; W1; W1; W1; W1; W1; W1; W1;
295 		W1; W1; W1; W1; W1; W1; W1; W1;
296 		len -= 64;
297 	}
298 	while (len > 0) {
299 		wait = sci_data_wait;
300 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
301 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
302 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
303 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
304 			  || --wait < 0) {
305 #ifdef DEBUG
306 				if (sci_debug)
307 					printf("mlhdma_out fail: l%d i%x w%d\n",
308 					len, csr, wait);
309 #endif
310 				*dev->sci_mode &= ~SCI_MODE_DMA;
311 				return 0;
312 			}
313 		}
314 
315 		*sci_dma = *buf++;
316 		len--;
317 	}
318 
319 	wait = sci_data_wait;
320 	while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
321 	  SCI_CSR_PHASE_MATCH && --wait);
322 
323 	*dev->sci_mode &= ~SCI_MODE_DMA;
324 	return 0;
325 }
326