1 /* $NetBSD: gtsc.c,v 1.21 1997/01/21 05:44:43 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Christian E. Hopps 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)dma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/custom.h> 45 #include <amiga/amiga/cc.h> 46 #include <amiga/amiga/device.h> 47 #include <amiga/amiga/isr.h> 48 #include <amiga/dev/dmavar.h> 49 #include <amiga/dev/sbicreg.h> 50 #include <amiga/dev/sbicvar.h> 51 #include <amiga/dev/gtscreg.h> 52 #include <amiga/dev/zbusvar.h> 53 #include <amiga/dev/gvpbusvar.h> 54 55 void gtscattach __P((struct device *, struct device *, void *)); 56 int gtscmatch __P((struct device *, struct cfdata *, void *)); 57 58 void gtsc_enintr __P((struct sbic_softc *)); 59 void gtsc_dmastop __P((struct sbic_softc *)); 60 int gtsc_dmanext __P((struct sbic_softc *)); 61 int gtsc_dmaintr __P((void *)); 62 int gtsc_dmago __P((struct sbic_softc *, char *, int, int)); 63 64 #ifdef DEBUG 65 void gtsc_dump __P((void)); 66 #endif 67 68 struct scsi_adapter gtsc_scsiswitch = { 69 sbic_scsicmd, 70 sbic_minphys, 71 0, /* no lun support */ 72 0, /* no lun support */ 73 }; 74 75 struct scsi_device gtsc_scsidev = { 76 NULL, /* use default error handler */ 77 NULL, /* have a queue served by this ??? */ 78 NULL, /* have no async handler ??? */ 79 NULL, /* Use default done routine */ 80 }; 81 82 int gtsc_maxdma = 0; /* Maximum size per DMA transfer */ 83 int gtsc_dmamask = 0; 84 int gtsc_dmabounce = 0; 85 int gtsc_clock_override = 0; 86 87 #ifdef DEBUG 88 int gtsc_debug = 0; 89 #endif 90 91 struct cfattach gtsc_ca = { 92 sizeof(struct sbic_softc), gtscmatch, gtscattach 93 }; 94 95 struct cfdriver gtsc_cd = { 96 NULL, "gtsc", DV_DULL, NULL, 0 97 }; 98 99 int 100 gtscmatch(pdp, cfp, auxp) 101 struct device *pdp; 102 struct cfdata *cfp; 103 void *auxp; 104 { 105 struct gvpbus_args *gap; 106 107 gap = auxp; 108 if (gap->flags & GVP_SCSI) 109 return(1); 110 return(0); 111 } 112 113 /* 114 * attach all devices on our board. 115 */ 116 void 117 gtscattach(pdp, dp, auxp) 118 struct device *pdp, *dp; 119 void *auxp; 120 { 121 volatile struct sdmac *rp; 122 struct gvpbus_args *gap; 123 struct sbic_softc *sc; 124 125 gap = auxp; 126 sc = (struct sbic_softc *)dp; 127 sc->sc_cregs = rp = gap->zargs.va; 128 129 /* 130 * disable ints and reset bank register 131 */ 132 rp->CNTR = 0; 133 if ((gap->flags & GVP_NOBANK) == 0) 134 rp->bank = 0; 135 136 sc->sc_dmago = gtsc_dmago; 137 sc->sc_enintr = gtsc_enintr; 138 sc->sc_dmanext = gtsc_dmanext; 139 sc->sc_dmastop = gtsc_dmastop; 140 sc->sc_dmacmd = 0; 141 142 sc->sc_flags |= SBICF_BADDMA; 143 if (gtsc_dmamask) 144 sc->sc_dmamask = gtsc_dmamask; 145 else if (gap->flags & GVP_24BITDMA) 146 sc->sc_dmamask = ~0x00ffffff; 147 else if (gap->flags & GVP_25BITDMA) 148 sc->sc_dmamask = ~0x01ffffff; 149 else 150 sc->sc_dmamask = ~0x07ffffff; 151 printf(": dmamask 0x%lx", ~sc->sc_dmamask); 152 153 if ((gap->flags & GVP_NOBANK) == 0) 154 sc->gtsc_bankmask = (~sc->sc_dmamask >> 18) & 0x01c0; 155 156 #if 0 157 /* 158 * if the user requests a bounce buffer or 159 * the users kva space is not ztwo and dma needs it 160 * try and allocate a bounce buffer. If we allocate 161 * one and it is in ztwo space leave maxdma to user 162 * setting or default to MAXPHYS else the address must 163 * be on the chip bus so decrease it to either the users 164 * setting or 1024 bytes. 165 * 166 * XXX this needs to change if we move to multiple memory segments. 167 */ 168 if (gtsc_dmabounce || kvtop(sc) & sc->sc_dmamask) { 169 sc->sc_dmabuffer = (char *) alloc_z2mem(MAXPHYS * 8); /* XXX */ 170 if (isztwomem(sc->sc_dmabuffer)) 171 printf(" bounce pa 0x%x", kvtop(sc->sc_dmabuffer)); 172 else if (gtsc_maxdma == 0) { 173 gtsc_maxdma = 1024; 174 printf(" bounce pa 0x%x", 175 PREP_DMA_MEM(sc->sc_dmabuffer)); 176 } 177 } 178 #endif 179 if (gtsc_maxdma == 0) 180 gtsc_maxdma = MAXPHYS; 181 182 printf(" flags %x", gap->flags); 183 printf(" maxdma %d\n", gtsc_maxdma); 184 185 sc->sc_sbicp = (sbic_regmap_p) ((int)rp + 0x61); 186 sc->sc_clkfreq = gtsc_clock_override ? gtsc_clock_override : 187 ((gap->flags & GVP_14MHZ) ? 143 : 72); 188 printf("sc_clkfreg: %ld.%ldMhz\n", sc->sc_clkfreq / 10, sc->sc_clkfreq % 10); 189 190 sc->sc_link.channel = SCSI_CHANNEL_ONLY_ONE; 191 sc->sc_link.adapter_softc = sc; 192 sc->sc_link.adapter_target = 7; 193 sc->sc_link.adapter = >sc_scsiswitch; 194 sc->sc_link.device = >sc_scsidev; 195 sc->sc_link.openings = 2; 196 sc->sc_link.max_target = 7; 197 198 sbicinit(sc); 199 200 sc->sc_isr.isr_intr = gtsc_dmaintr; 201 sc->sc_isr.isr_arg = sc; 202 sc->sc_isr.isr_ipl = 2; 203 add_isr(&sc->sc_isr); 204 205 /* 206 * attach all scsi units on us 207 */ 208 config_found(dp, &sc->sc_link, scsiprint); 209 } 210 211 void 212 gtsc_enintr(dev) 213 struct sbic_softc *dev; 214 { 215 volatile struct sdmac *sdp; 216 217 sdp = dev->sc_cregs; 218 219 dev->sc_flags |= SBICF_INTR; 220 sdp->CNTR = GVP_CNTR_INTEN; 221 } 222 223 int 224 gtsc_dmago(dev, addr, count, flags) 225 struct sbic_softc *dev; 226 char *addr; 227 int count, flags; 228 { 229 volatile struct sdmac *sdp; 230 231 sdp = dev->sc_cregs; 232 /* 233 * Set up the command word based on flags 234 */ 235 dev->sc_dmacmd = GVP_CNTR_INTEN; 236 if ((flags & DMAGO_READ) == 0) 237 dev->sc_dmacmd |= GVP_CNTR_DDIR; 238 239 #ifdef DEBUG 240 if (gtsc_debug & DDB_IO) 241 printf("gtsc_dmago: cmd %x\n", dev->sc_dmacmd); 242 #endif 243 dev->sc_flags |= SBICF_INTR; 244 sdp->CNTR = dev->sc_dmacmd; 245 if((u_int)dev->sc_cur->dc_addr & dev->sc_dmamask) { 246 #if 1 247 printf("gtsc_dmago: pa %p->%lx dmacmd %x", 248 dev->sc_cur->dc_addr, 249 (u_int)dev->sc_cur->dc_addr & ~dev->sc_dmamask, 250 dev->sc_dmacmd); 251 #endif 252 sdp->ACR = 0x00f80000; /***********************************/ 253 } else 254 sdp->ACR = (u_int) dev->sc_cur->dc_addr; 255 if (dev->gtsc_bankmask) 256 sdp->bank = 257 dev->gtsc_bankmask & (((u_int)dev->sc_cur->dc_addr) >> 18); 258 sdp->ST_DMA = 1; 259 260 /* 261 * restrict transfer count to maximum 262 */ 263 if (dev->sc_tcnt > gtsc_maxdma) 264 dev->sc_tcnt = gtsc_maxdma; 265 #if 1 266 if((u_int)dev->sc_cur->dc_addr & dev->sc_dmamask) 267 printf(" tcnt %ld\n", dev->sc_tcnt); 268 #endif 269 return(dev->sc_tcnt); 270 } 271 272 void 273 gtsc_dmastop(dev) 274 struct sbic_softc *dev; 275 { 276 volatile struct sdmac *sdp; 277 int s; 278 279 sdp = dev->sc_cregs; 280 281 #ifdef DEBUG 282 if (gtsc_debug & DDB_FOLLOW) 283 printf("gtsc_dmastop()\n"); 284 #endif 285 if (dev->sc_dmacmd) { 286 /* 287 * clear possible interrupt and stop dma 288 */ 289 s = splbio(); 290 sdp->CNTR &= ~GVP_CNTR_INT_P; 291 sdp->SP_DMA = 1; 292 dev->sc_dmacmd = 0; 293 splx(s); 294 } 295 } 296 297 int 298 gtsc_dmaintr(arg) 299 void *arg; 300 { 301 struct sbic_softc *dev = arg; 302 volatile struct sdmac *sdp; 303 int stat; 304 305 sdp = dev->sc_cregs; 306 stat = sdp->CNTR; 307 if ((stat & GVP_CNTR_INT_P) == 0) 308 return (0); 309 #ifdef DEBUG 310 if (gtsc_debug & DDB_FOLLOW) 311 printf("%s: dmaintr 0x%x\n", dev->sc_dev.dv_xname, stat); 312 #endif 313 if (dev->sc_flags & SBICF_INTR) 314 if (sbicintr(dev)) 315 return (1); 316 return(0); 317 } 318 319 320 int 321 gtsc_dmanext(dev) 322 struct sbic_softc *dev; 323 { 324 volatile struct sdmac *sdp; 325 326 sdp = dev->sc_cregs; 327 328 if (dev->sc_cur > dev->sc_last) { 329 /* shouldn't happen !! */ 330 printf("gtsc_dmanext at end !!!\n"); 331 gtsc_dmastop(dev); 332 return(0); 333 } 334 /* 335 * clear possible interrupt and stop dma 336 */ 337 sdp->CNTR &= ~GVP_CNTR_INT_P; 338 sdp->SP_DMA = 1; 339 340 sdp->CNTR = dev->sc_dmacmd; 341 sdp->ACR = (u_int) dev->sc_cur->dc_addr; 342 if (dev->gtsc_bankmask) 343 sdp->bank = 344 dev->gtsc_bankmask & ((u_int)dev->sc_cur->dc_addr >> 18); 345 sdp->ST_DMA = 1; 346 347 dev->sc_tcnt = dev->sc_cur->dc_count << 1; 348 if (dev->sc_tcnt > gtsc_maxdma) 349 dev->sc_tcnt = gtsc_maxdma; 350 #ifdef DEBUG 351 if (gtsc_debug & DDB_FOLLOW) 352 printf("gtsc_dmanext ret: %ld\n", dev->sc_tcnt); 353 #endif 354 return(dev->sc_tcnt); 355 } 356 357 #ifdef DEBUG 358 void 359 gtsc_dump() 360 { 361 int i; 362 363 for (i = 0; i < gtsc_cd.cd_ndevs; ++i) 364 if (gtsc_cd.cd_devs[i]) 365 sbic_dump(gtsc_cd.cd_devs[i]); 366 } 367 #endif 368