1 /* $NetBSD: flscvar.h,v 1.6 2008/04/13 04:55:52 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project 18 * by Michael L. Hitch. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 struct flsc_softc { 35 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 36 37 struct isr sc_isr; /* Interrupt chain struct */ 38 39 volatile uint8_t *sc_reg; /* the registers */ 40 volatile uint8_t *sc_dmabase; 41 42 int sc_active; /* Pseudo-DMA state vars */ 43 int sc_piomode; 44 int sc_datain; 45 int sc_tc; 46 size_t sc_dmasize; 47 size_t sc_dmatrans; 48 uint8_t **sc_dmaaddr; 49 size_t *sc_pdmalen; 50 paddr_t sc_pa; 51 52 uint8_t *sc_alignbuf; 53 uint8_t sc_pad1[2]; /* XXX */ 54 uint8_t sc_unalignbuf[256]; 55 uint8_t sc_pad2[16]; 56 uint8_t sc_hardbits; 57 uint8_t sc_portbits; 58 uint8_t sc_csr; 59 uint8_t sc_xfr_align; 60 }; 61 62 #define FLSC_HB_DISABLED 0x01 63 #define FLSC_HB_BUSID6 0x02 64 #define FLSC_HB_SEAGATE 0x04 65 #define FLSC_HB_SLOW 0x08 66 #define FLSC_HB_SYNCHRON 0x10 67 #define FLSC_HB_CREQ 0x20 68 #define FLSC_HB_IACT 0x40 69 #define FLSC_HB_MINT 0x80 70 71 #define FLSC_PB_ESI 0x01 72 #define FLSC_PB_EDI 0x02 73 #define FLSC_PB_ENABLE_DMA 0x04 74 #define FLSC_PB_DISABLE_DMA 0x00 /* Symmetric reasons */ 75 #define FLSC_PB_DMA_WRITE 0x08 76 #define FLSC_PB_DMA_READ 0x00 /* Symmetric reasons */ 77 #define FLSC_PB_LED 0x10 78 79 #define FLSC_PB_INT_BITS (FLSC_PB_ESI | FLSC_PB_EDI) 80 #define FLSC_PB_DMA_BITS (FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE) 81