1*78f74058Ssnj /* $NetBSD: flscvar.h,v 1.7 2009/10/21 23:53:38 snj Exp $ */ 2974e9f6eSveego 321d667c8Schopps /* 466e9e901Smhitch * Copyright (c) 1997 Michael L. Hitch. 566e9e901Smhitch * All rights reserved. 621d667c8Schopps * 721d667c8Schopps * Redistribution and use in source and binary forms, with or without 821d667c8Schopps * modification, are permitted provided that the following conditions 921d667c8Schopps * are met: 1021d667c8Schopps * 1. Redistributions of source code must retain the above copyright 1121d667c8Schopps * notice, this list of conditions and the following disclaimer. 1221d667c8Schopps * 2. Redistributions in binary form must reproduce the above copyright 1321d667c8Schopps * notice, this list of conditions and the following disclaimer in the 1421d667c8Schopps * documentation and/or other materials provided with the distribution. 1521d667c8Schopps * 1621d667c8Schopps * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1721d667c8Schopps * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1821d667c8Schopps * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1921d667c8Schopps * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2021d667c8Schopps * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2121d667c8Schopps * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2221d667c8Schopps * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2321d667c8Schopps * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2421d667c8Schopps * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2521d667c8Schopps * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2621d667c8Schopps */ 2721d667c8Schopps 2821d667c8Schopps struct flsc_softc { 2966e9e901Smhitch struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 3066e9e901Smhitch 3166e9e901Smhitch struct isr sc_isr; /* Interrupt chain struct */ 3266e9e901Smhitch 3378a1d236Stsutsui volatile uint8_t *sc_reg; /* the registers */ 3478a1d236Stsutsui volatile uint8_t *sc_dmabase; 3566e9e901Smhitch 3666e9e901Smhitch int sc_active; /* Pseudo-DMA state vars */ 3766e9e901Smhitch int sc_piomode; 3866e9e901Smhitch int sc_datain; 3966e9e901Smhitch int sc_tc; 4066e9e901Smhitch size_t sc_dmasize; 4166e9e901Smhitch size_t sc_dmatrans; 4278a1d236Stsutsui uint8_t **sc_dmaaddr; 4366e9e901Smhitch size_t *sc_pdmalen; 44744246faSis paddr_t sc_pa; 4566e9e901Smhitch 4678a1d236Stsutsui uint8_t *sc_alignbuf; 4778a1d236Stsutsui uint8_t sc_pad1[2]; /* XXX */ 4878a1d236Stsutsui uint8_t sc_unalignbuf[256]; 4978a1d236Stsutsui uint8_t sc_pad2[16]; 5078a1d236Stsutsui uint8_t sc_hardbits; 5178a1d236Stsutsui uint8_t sc_portbits; 5278a1d236Stsutsui uint8_t sc_csr; 5378a1d236Stsutsui uint8_t sc_xfr_align; 5421d667c8Schopps }; 5521d667c8Schopps 5666e9e901Smhitch #define FLSC_HB_DISABLED 0x01 5766e9e901Smhitch #define FLSC_HB_BUSID6 0x02 5866e9e901Smhitch #define FLSC_HB_SEAGATE 0x04 5966e9e901Smhitch #define FLSC_HB_SLOW 0x08 6066e9e901Smhitch #define FLSC_HB_SYNCHRON 0x10 6166e9e901Smhitch #define FLSC_HB_CREQ 0x20 6266e9e901Smhitch #define FLSC_HB_IACT 0x40 6366e9e901Smhitch #define FLSC_HB_MINT 0x80 6466e9e901Smhitch 6566e9e901Smhitch #define FLSC_PB_ESI 0x01 6666e9e901Smhitch #define FLSC_PB_EDI 0x02 6766e9e901Smhitch #define FLSC_PB_ENABLE_DMA 0x04 6866e9e901Smhitch #define FLSC_PB_DISABLE_DMA 0x00 /* Symmetric reasons */ 6966e9e901Smhitch #define FLSC_PB_DMA_WRITE 0x08 7066e9e901Smhitch #define FLSC_PB_DMA_READ 0x00 /* Symmetric reasons */ 7166e9e901Smhitch #define FLSC_PB_LED 0x10 7266e9e901Smhitch 7366e9e901Smhitch #define FLSC_PB_INT_BITS (FLSC_PB_ESI | FLSC_PB_EDI) 7466e9e901Smhitch #define FLSC_PB_DMA_BITS (FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE) 75