1 /* $NetBSD: drsc.c,v 1.32 2012/10/27 17:17:28 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Ignatios Souvatzis 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * @(#)dma.c 33 */ 34 35 /* 36 * Copyright (c) 1994 Michael L. Hitch 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 * @(#)dma.c 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: drsc.c,v 1.32 2012/10/27 17:17:28 chs Exp $"); 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/kernel.h> 67 #include <sys/device.h> 68 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 #include <amiga/amiga/custom.h> 73 #include <amiga/amiga/cc.h> 74 #include <amiga/amiga/device.h> 75 #include <amiga/amiga/isr.h> 76 #include <amiga/dev/siopreg.h> 77 #include <amiga/dev/siopvar.h> 78 #include <amiga/amiga/drcustom.h> 79 #include <m68k/include/asm_single.h> 80 81 #include <machine/cpu.h> /* is_xxx(), */ 82 83 void drscattach(device_t, device_t, void *); 84 int drscmatch(device_t, cfdata_t, void *); 85 int drsc_dmaintr(struct siop_softc *); 86 #ifdef DEBUG 87 void drsc_dump(void); 88 #endif 89 90 #ifdef DEBUG 91 #endif 92 93 CFATTACH_DECL_NEW(drsc, sizeof(struct siop_softc), 94 drscmatch, drscattach, NULL, NULL); 95 96 static struct siop_softc *drsc_softc; 97 98 /* 99 * One of us is on every DraCo motherboard, 100 */ 101 int 102 drscmatch(device_t parent, cfdata_t cf, void *aux) 103 { 104 static int drsc_matched = 0; 105 106 /* Allow only one instance. */ 107 if (!is_draco() || !matchname(aux, "drsc") || drsc_matched) 108 return (0); 109 110 drsc_matched = 1; 111 return(1); 112 } 113 114 void 115 drscattach(device_t parent, device_t self, void *aux) 116 { 117 struct siop_softc *sc = device_private(self); 118 struct zbus_args *zap; 119 siop_regmap_p rp; 120 struct scsipi_adapter *adapt = &sc->sc_adapter; 121 struct scsipi_channel *chan = &sc->sc_channel; 122 123 printf("\n"); 124 125 zap = aux; 126 127 sc->sc_dev = self; 128 sc->sc_siopp = rp = (siop_regmap_p)(DRCCADDR+PAGE_SIZE*DRSCSIPG); 129 130 /* 131 * CTEST7 = TT1 132 */ 133 sc->sc_clock_freq = 50; /* Clock = 50MHz */ 134 sc->sc_ctest7 = 0x02; 135 136 sc->sc_siop_si = softint_establish(SOFTINT_BIO, 137 (void (*)(void *))siopintr, sc); 138 139 /* 140 * Fill in the scsipi_adapter. 141 */ 142 memset(adapt, 0, sizeof(*adapt)); 143 adapt->adapt_dev = self; 144 adapt->adapt_nchannels = 1; 145 adapt->adapt_openings = 7; 146 adapt->adapt_max_periph = 1; 147 adapt->adapt_request = siop_scsipi_request; 148 adapt->adapt_minphys = siop_minphys; 149 150 /* 151 * Fill in the scsipi_channel. 152 */ 153 memset(chan, 0, sizeof(*chan)); 154 chan->chan_adapter = adapt; 155 chan->chan_bustype = &scsi_bustype; 156 chan->chan_channel = 0; 157 chan->chan_ntargets = 8; 158 chan->chan_nluns = 8; 159 chan->chan_id = 7; 160 161 siopinitialize(sc); 162 163 #if 0 164 sc->sc_isr.isr_intr = drsc_dmaintr; 165 sc->sc_isr.isr_arg = sc; 166 sc->sc_isr.isr_ipl = 4; 167 add_isr(&sc->sc_isr); 168 #else 169 drsc_softc = sc; 170 single_inst_bclr_b(*draco_intpen, DRIRQ_SCSI); 171 single_inst_bset_b(*draco_intena, DRIRQ_SCSI); 172 #endif 173 /* 174 * attach all scsi units on us 175 */ 176 config_found(self, chan, scsiprint); 177 } 178 179 /* 180 * Level 4 interrupt processing for the MacroSystem DraCo mainboard 181 * SCSI. Because the level 4 interrupt is above splbio, the 182 * interrupt status is saved and a softint scheduled. This way, 183 * the actual processing of the interrupt can be deferred until 184 * splbio is unblocked. 185 */ 186 187 void 188 drsc_handler(void) 189 { 190 struct siop_softc *sc = drsc_softc; 191 192 siop_regmap_p rp; 193 int istat; 194 195 if (sc->sc_flags & SIOP_INTSOFF) 196 return; /* interrupts are not active */ 197 198 rp = sc->sc_siopp; 199 istat = rp->siop_istat; 200 201 if ((istat & (SIOP_ISTAT_SIP | SIOP_ISTAT_DIP)) == 0) 202 return; 203 204 /* 205 * save interrupt status, DMA status, and SCSI status 0 206 * (may need to deal with stacked interrupts?) 207 */ 208 sc->sc_sstat0 = rp->siop_sstat0; 209 sc->sc_istat = istat; 210 sc->sc_dstat = rp->siop_dstat; 211 /* 212 * disable interrupts until the callback can process this 213 * interrupt. 214 */ 215 #ifdef DRSC_NOCALLBACK 216 (void)spl1(); 217 siopintr(sc); 218 #else 219 rp->siop_sien = 0; 220 rp->siop_dien = 0; 221 sc->sc_flags |= SIOP_INTDEFER | SIOP_INTSOFF; 222 single_inst_bclr_b(*draco_intpen, DRIRQ_SCSI); 223 #ifdef DEBUG 224 if (*draco_intpen & DRIRQ_SCSI) 225 printf("%s: intpen still 0x%x\n", device_xname(sc->sc_dev), 226 *draco_intpen); 227 #endif 228 softint_schedule(sc->sc_siop_si); 229 #endif 230 return; 231 } 232 233 #ifdef DEBUG 234 void 235 drsc_dump(void) 236 { 237 extern struct cfdriver drsc_cd; 238 struct siop_softc *sc; 239 int i; 240 241 for (i = 0; i < drsc_cd.cd_ndevs; ++i) { 242 sc = device_lookup_private(&drsc_cd, i); 243 if (sc != NULL) 244 siop_dump(sc); 245 } 246 } 247 #endif 248