1 /* $NetBSD: cbsc.c,v 1.28 2008/04/13 04:55:52 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cbsc.c,v 1.28 2008/04/13 04:55:52 tsutsui Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/cpu.h> 61 #include <machine/param.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <amiga/amiga/isr.h> 67 #include <amiga/dev/cbscvar.h> 68 #include <amiga/dev/zbusvar.h> 69 70 #ifdef __powerpc__ 71 #define badaddr(a) badaddr_read(a, 2, NULL) 72 #endif 73 74 int cbscmatch(device_t, cfdata_t, void *); 75 void cbscattach(device_t, device_t, void *); 76 77 /* Linkup to the rest of the kernel */ 78 CFATTACH_DECL_NEW(cbsc, sizeof(struct cbsc_softc), 79 cbscmatch, cbscattach, NULL, NULL); 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 uint8_t cbsc_read_reg(struct ncr53c9x_softc *, int); 85 void cbsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 86 int cbsc_dma_isintr(struct ncr53c9x_softc *); 87 void cbsc_dma_reset(struct ncr53c9x_softc *); 88 int cbsc_dma_intr(struct ncr53c9x_softc *); 89 int cbsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 90 size_t *, int, size_t *); 91 void cbsc_dma_go(struct ncr53c9x_softc *); 92 void cbsc_dma_stop(struct ncr53c9x_softc *); 93 int cbsc_dma_isactive(struct ncr53c9x_softc *); 94 95 struct ncr53c9x_glue cbsc_glue = { 96 cbsc_read_reg, 97 cbsc_write_reg, 98 cbsc_dma_isintr, 99 cbsc_dma_reset, 100 cbsc_dma_intr, 101 cbsc_dma_setup, 102 cbsc_dma_go, 103 cbsc_dma_stop, 104 cbsc_dma_isactive, 105 NULL, 106 }; 107 108 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 109 u_long cbsc_max_dma = 1024; 110 extern int ser_open_speed; 111 112 u_long cbsc_cnt_pio = 0; /* number of PIO transfers */ 113 u_long cbsc_cnt_dma = 0; /* number of DMA transfers */ 114 u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 115 u_long cbsc_cnt_dma3 = 0; /* number of pages combined */ 116 117 #ifdef DEBUG 118 struct { 119 uint8_t hardbits; 120 uint8_t status; 121 uint8_t xx; 122 uint8_t yy; 123 } cbsc_trace[128]; 124 int cbsc_trace_ptr = 0; 125 int cbsc_trace_enable = 1; 126 void cbsc_dump(void); 127 #endif 128 129 /* 130 * if we are a Phase5 CyberSCSI [mark I?] 131 */ 132 int 133 cbscmatch(device_t parent, cfdata_t cf, void *aux) 134 { 135 struct zbus_args *zap; 136 volatile uint8_t *regs; 137 138 zap = aux; 139 if (zap->manid != 0x2140) 140 return 0; /* It's not Phase5 */ 141 if (zap->prodid != 12 && zap->prodid != 11) 142 return 0; /* Not CyberStorm MKI SCSI */ 143 if (zap->prodid == 11 && iszthreepa(zap->pa)) 144 return 0; /* Fastlane Z3! */ 145 regs = &((volatile uint8_t *)zap->va)[0xf400]; 146 if (badaddr((void *)__UNVOLATILE(regs))) 147 return 0; 148 regs[NCR_CFG1 * 4] = 0; 149 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 150 delay(5); 151 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 152 return 0; 153 return 1; 154 } 155 156 /* 157 * Attach this instance, and then all the sub-devices 158 */ 159 void 160 cbscattach(device_t parent, device_t self, void *aux) 161 { 162 struct cbsc_softc *csc = device_private(self); 163 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 164 struct zbus_args *zap; 165 extern u_long scsi_nosync; 166 extern int shift_nosync; 167 extern int ncr53c9x_debug; 168 169 /* 170 * Set up the glue for MI code early; we use some of it here. 171 */ 172 sc->sc_dev = self; 173 sc->sc_glue = &cbsc_glue; 174 175 /* 176 * Save the regs 177 */ 178 zap = aux; 179 csc->sc_reg = &((volatile uint8_t *)zap->va)[0xf400]; 180 csc->sc_dmabase = &csc->sc_reg[0x400]; 181 182 sc->sc_freq = 40; /* Clocked at 40 MHz */ 183 184 aprint_normal(": address %p", csc->sc_reg); 185 186 sc->sc_id = 7; 187 188 /* 189 * It is necessary to try to load the 2nd config register here, 190 * to find out what rev the FAS chip is, else the ncr53c9x_reset 191 * will not set up the defaults correctly. 192 */ 193 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 194 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 195 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 196 sc->sc_rev = NCR_VARIANT_FAS216; 197 198 /* 199 * This is the value used to start sync negotiations 200 * Note that the NCR register "SYNCTP" is programmed 201 * in "clocks per byte", and has a minimum value of 4. 202 * The SCSI period used in negotiation is one-fourth 203 * of the time (in nanoseconds) needed to transfer one byte. 204 * Since the chip's clock is given in MHz, we have the following 205 * formula: 4 * period = (1000 / freq) * 4 206 */ 207 sc->sc_minsync = 1000 / sc->sc_freq; 208 209 /* 210 * get flags from -I argument and set cf_flags. 211 * NOTE: low 8 bits are to disable disconnect, and the next 212 * 8 bits are to disable sync. 213 */ 214 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 215 & 0xffff; 216 shift_nosync += 16; 217 218 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 219 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 220 shift_nosync += 16; 221 222 #if 1 223 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 224 sc->sc_minsync = 0; 225 #endif 226 227 /* Really no limit, but since we want to fit into the TCR... */ 228 sc->sc_maxxfer = 64 * 1024; 229 230 /* 231 * Configure interrupts. 232 */ 233 csc->sc_isr.isr_intr = ncr53c9x_intr; 234 csc->sc_isr.isr_arg = sc; 235 csc->sc_isr.isr_ipl = 2; 236 add_isr(&csc->sc_isr); 237 238 /* 239 * Now try to attach all the sub-devices 240 */ 241 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 242 sc->sc_adapter.adapt_minphys = minphys; 243 ncr53c9x_attach(sc); 244 } 245 246 /* 247 * Glue functions. 248 */ 249 250 uint8_t 251 cbsc_read_reg(struct ncr53c9x_softc *sc, int reg) 252 { 253 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 254 255 return csc->sc_reg[reg * 4]; 256 } 257 258 void 259 cbsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 260 { 261 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 262 uint8_t v = val; 263 264 csc->sc_reg[reg * 4] = v; 265 #ifdef DEBUG 266 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 267 reg == NCR_CMD/* && csc->sc_active*/) { 268 cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v; 269 /* printf(" cmd %x", v);*/ 270 } 271 #endif 272 } 273 274 int 275 cbsc_dma_isintr(struct ncr53c9x_softc *sc) 276 { 277 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 278 279 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 280 return 0; 281 282 if (sc->sc_state == NCR_CONNECTED) 283 csc->sc_portbits |= CBSC_PB_LED; 284 else 285 csc->sc_portbits &= ~CBSC_PB_LED; 286 csc->sc_reg[0x802] = csc->sc_portbits; 287 288 if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0) 289 return 0; 290 #ifdef DEBUG 291 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) { 292 cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 293 cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 294 cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active; 295 cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127; 296 } 297 #endif 298 return 1; 299 } 300 301 void 302 cbsc_dma_reset(struct ncr53c9x_softc *sc) 303 { 304 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 305 306 csc->sc_active = 0; 307 } 308 309 int 310 cbsc_dma_intr(struct ncr53c9x_softc *sc) 311 { 312 register struct cbsc_softc *csc = (struct cbsc_softc *)sc; 313 register int cnt; 314 315 NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ", 316 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 317 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 318 if (csc->sc_active == 0) { 319 printf("cbsc_intr--inactive DMA\n"); 320 return -1; 321 } 322 323 /* update sc_dmaaddr and sc_pdmalen */ 324 cnt = csc->sc_reg[NCR_TCL * 4]; 325 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 326 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 327 if (!csc->sc_datain) { 328 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 329 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 330 } 331 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 332 NCR_DMA(("DMA xferred %d\n", cnt)); 333 if (csc->sc_xfr_align) { 334 memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt); 335 csc->sc_xfr_align = 0; 336 } 337 *csc->sc_dmaaddr += cnt; 338 *csc->sc_pdmalen -= cnt; 339 csc->sc_active = 0; 340 return 0; 341 } 342 343 int 344 cbsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 345 int datain, size_t *dmasize) 346 { 347 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 348 paddr_t pa; 349 uint8_t *ptr; 350 size_t xfer; 351 352 csc->sc_dmaaddr = addr; 353 csc->sc_pdmalen = len; 354 csc->sc_datain = datain; 355 csc->sc_dmasize = *dmasize; 356 /* 357 * DMA can be nasty for high-speed serial input, so limit the 358 * size of this DMA operation if the serial port is running at 359 * a high speed (higher than 19200 for now - should be adjusted 360 * based on CPU type and speed?). 361 * XXX - add serial speed check XXX 362 */ 363 if (ser_open_speed > 19200 && cbsc_max_dma != 0 && 364 csc->sc_dmasize > cbsc_max_dma) 365 csc->sc_dmasize = cbsc_max_dma; 366 ptr = *addr; /* Kernel virtual address */ 367 pa = kvtop(ptr); /* Physical address of DMA */ 368 xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 369 csc->sc_xfr_align = 0; 370 /* 371 * If output and unaligned, stuff odd byte into FIFO 372 */ 373 if (datain == 0 && (int)ptr & 1) { 374 NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n")); 375 pa++; 376 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 377 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 378 } 379 /* 380 * If unaligned address, read unaligned bytes into alignment buffer 381 */ 382 else if ((int)ptr & 1) { 383 pa = kvtop((void *)&csc->sc_alignbuf); 384 xfer = csc->sc_dmasize = min(xfer, sizeof(csc->sc_alignbuf)); 385 NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer)); 386 csc->sc_xfr_align = 1; 387 } 388 ++cbsc_cnt_dma; /* number of DMA operations */ 389 390 while (xfer < csc->sc_dmasize) { 391 if ((pa + xfer) != kvtop(*addr + xfer)) 392 break; 393 if ((csc->sc_dmasize - xfer) < PAGE_SIZE) 394 xfer = csc->sc_dmasize; 395 else 396 xfer += PAGE_SIZE; 397 ++cbsc_cnt_dma3; 398 } 399 if (xfer != *len) 400 ++cbsc_cnt_dma2; 401 402 csc->sc_dmasize = xfer; 403 *dmasize = csc->sc_dmasize; 404 csc->sc_pa = pa; 405 #if defined(M68040) || defined(M68060) 406 if (mmutype == MMU_68040) { 407 if (csc->sc_xfr_align) { 408 dma_cachectl(csc->sc_alignbuf, 409 sizeof(csc->sc_alignbuf)); 410 } 411 else 412 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 413 } 414 #endif 415 416 if (csc->sc_datain) 417 pa &= ~1; 418 else 419 pa |= 1; 420 csc->sc_dmabase[0] = (uint8_t)(pa >> 24); 421 csc->sc_dmabase[2] = (uint8_t)(pa >> 16); 422 csc->sc_dmabase[4] = (uint8_t)(pa >> 8); 423 csc->sc_dmabase[6] = (uint8_t)(pa); 424 if (csc->sc_datain) 425 csc->sc_portbits &= ~CBSC_PB_WRITE; 426 else 427 csc->sc_portbits |= CBSC_PB_WRITE; 428 csc->sc_reg[0x802] = csc->sc_portbits; 429 csc->sc_active = 1; 430 return 0; 431 } 432 433 void 434 cbsc_dma_go(struct ncr53c9x_softc *sc) 435 { 436 } 437 438 void 439 cbsc_dma_stop(struct ncr53c9x_softc *sc) 440 { 441 } 442 443 int 444 cbsc_dma_isactive(struct ncr53c9x_softc *sc) 445 { 446 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 447 448 return csc->sc_active; 449 } 450 451 #ifdef DEBUG 452 void 453 cbsc_dump(void) 454 { 455 int i; 456 457 i = cbsc_trace_ptr; 458 printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr); 459 do { 460 if (cbsc_trace[i].hardbits == 0) { 461 i = (i + 1) & 127; 462 continue; 463 } 464 printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits, 465 cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy); 466 if (cbsc_trace[i].status & NCRSTAT_INT) 467 printf("NCRINT/"); 468 if (cbsc_trace[i].status & NCRSTAT_TC) 469 printf("NCRTC/"); 470 switch(cbsc_trace[i].status & NCRSTAT_PHASE) { 471 case 0: 472 printf("dataout"); break; 473 case 1: 474 printf("datain"); break; 475 case 2: 476 printf("cmdout"); break; 477 case 3: 478 printf("status"); break; 479 case 6: 480 printf("msgout"); break; 481 case 7: 482 printf("msgin"); break; 483 default: 484 printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE); 485 } 486 printf(") "); 487 i = (i + 1) & 127; 488 } while (i != cbsc_trace_ptr); 489 printf("\n"); 490 } 491 #endif 492