1 /* $NetBSD: cbsc.c,v 1.27 2007/10/17 19:53:15 garbled Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cbsc.c,v 1.27 2007/10/17 19:53:15 garbled Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/cpu.h> 61 #include <machine/param.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <amiga/amiga/isr.h> 67 #include <amiga/dev/cbscvar.h> 68 #include <amiga/dev/zbusvar.h> 69 70 #ifdef __powerpc__ 71 #define badaddr(a) badaddr_read(a, 2, NULL) 72 #endif 73 74 void cbscattach(struct device *, struct device *, void *); 75 int cbscmatch(struct device *, struct cfdata *, void *); 76 77 /* Linkup to the rest of the kernel */ 78 CFATTACH_DECL(cbsc, sizeof(struct cbsc_softc), 79 cbscmatch, cbscattach, NULL, NULL); 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 u_char cbsc_read_reg(struct ncr53c9x_softc *, int); 85 void cbsc_write_reg(struct ncr53c9x_softc *, int, u_char); 86 int cbsc_dma_isintr(struct ncr53c9x_softc *); 87 void cbsc_dma_reset(struct ncr53c9x_softc *); 88 int cbsc_dma_intr(struct ncr53c9x_softc *); 89 int cbsc_dma_setup(struct ncr53c9x_softc *, void **, 90 size_t *, int, size_t *); 91 void cbsc_dma_go(struct ncr53c9x_softc *); 92 void cbsc_dma_stop(struct ncr53c9x_softc *); 93 int cbsc_dma_isactive(struct ncr53c9x_softc *); 94 95 struct ncr53c9x_glue cbsc_glue = { 96 cbsc_read_reg, 97 cbsc_write_reg, 98 cbsc_dma_isintr, 99 cbsc_dma_reset, 100 cbsc_dma_intr, 101 cbsc_dma_setup, 102 cbsc_dma_go, 103 cbsc_dma_stop, 104 cbsc_dma_isactive, 105 0, 106 }; 107 108 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 109 u_long cbsc_max_dma = 1024; 110 extern int ser_open_speed; 111 112 u_long cbsc_cnt_pio = 0; /* number of PIO transfers */ 113 u_long cbsc_cnt_dma = 0; /* number of DMA transfers */ 114 u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 115 u_long cbsc_cnt_dma3 = 0; /* number of pages combined */ 116 117 #ifdef DEBUG 118 struct { 119 u_char hardbits; 120 u_char status; 121 u_char xx; 122 u_char yy; 123 } cbsc_trace[128]; 124 int cbsc_trace_ptr = 0; 125 int cbsc_trace_enable = 1; 126 void cbsc_dump(void); 127 #endif 128 129 /* 130 * if we are a Phase5 CyberSCSI [mark I?] 131 */ 132 int 133 cbscmatch(struct device *parent, struct cfdata *cf, void *aux) 134 { 135 struct zbus_args *zap; 136 volatile u_char *regs; 137 138 zap = aux; 139 if (zap->manid != 0x2140) 140 return(0); /* It's not Phase5 */ 141 if (zap->prodid != 12 && zap->prodid != 11) 142 return(0); /* Not CyberStorm MKI SCSI */ 143 if (zap->prodid == 11 && iszthreepa(zap->pa)) 144 return(0); /* Fastlane Z3! */ 145 regs = &((volatile u_char *)zap->va)[0xf400]; 146 if (badaddr((void *)__UNVOLATILE(regs))) 147 return(0); 148 regs[NCR_CFG1 * 4] = 0; 149 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 150 delay(5); 151 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 152 return(0); 153 return(1); 154 } 155 156 /* 157 * Attach this instance, and then all the sub-devices 158 */ 159 void 160 cbscattach(struct device *parent, struct device *self, void *aux) 161 { 162 struct cbsc_softc *csc = (void *)self; 163 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 164 struct zbus_args *zap; 165 extern u_long scsi_nosync; 166 extern int shift_nosync; 167 extern int ncr53c9x_debug; 168 169 /* 170 * Set up the glue for MI code early; we use some of it here. 171 */ 172 sc->sc_glue = &cbsc_glue; 173 174 /* 175 * Save the regs 176 */ 177 zap = aux; 178 csc->sc_reg = &((volatile u_char *)zap->va)[0xf400]; 179 csc->sc_dmabase = &csc->sc_reg[0x400]; 180 181 sc->sc_freq = 40; /* Clocked at 40 MHz */ 182 183 printf(": address %p", csc->sc_reg); 184 185 sc->sc_id = 7; 186 187 /* 188 * It is necessary to try to load the 2nd config register here, 189 * to find out what rev the FAS chip is, else the ncr53c9x_reset 190 * will not set up the defaults correctly. 191 */ 192 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 193 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 194 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 195 sc->sc_rev = NCR_VARIANT_FAS216; 196 197 /* 198 * This is the value used to start sync negotiations 199 * Note that the NCR register "SYNCTP" is programmed 200 * in "clocks per byte", and has a minimum value of 4. 201 * The SCSI period used in negotiation is one-fourth 202 * of the time (in nanoseconds) needed to transfer one byte. 203 * Since the chip's clock is given in MHz, we have the following 204 * formula: 4 * period = (1000 / freq) * 4 205 */ 206 sc->sc_minsync = 1000 / sc->sc_freq; 207 208 /* 209 * get flags from -I argument and set cf_flags. 210 * NOTE: low 8 bits are to disable disconnect, and the next 211 * 8 bits are to disable sync. 212 */ 213 device_cfdata(&sc->sc_dev)->cf_flags |= (scsi_nosync >> shift_nosync) 214 & 0xffff; 215 shift_nosync += 16; 216 217 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 218 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 219 shift_nosync += 16; 220 221 #if 1 222 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 223 sc->sc_minsync = 0; 224 #endif 225 226 /* Really no limit, but since we want to fit into the TCR... */ 227 sc->sc_maxxfer = 64 * 1024; 228 229 /* 230 * Configure interrupts. 231 */ 232 csc->sc_isr.isr_intr = ncr53c9x_intr; 233 csc->sc_isr.isr_arg = sc; 234 csc->sc_isr.isr_ipl = 2; 235 add_isr(&csc->sc_isr); 236 237 /* 238 * Now try to attach all the sub-devices 239 */ 240 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 241 sc->sc_adapter.adapt_minphys = minphys; 242 ncr53c9x_attach(sc); 243 } 244 245 /* 246 * Glue functions. 247 */ 248 249 u_char 250 cbsc_read_reg(struct ncr53c9x_softc *sc, int reg) 251 { 252 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 253 254 return csc->sc_reg[reg * 4]; 255 } 256 257 void 258 cbsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 259 { 260 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 261 u_char v = val; 262 263 csc->sc_reg[reg * 4] = v; 264 #ifdef DEBUG 265 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 266 reg == NCR_CMD/* && csc->sc_active*/) { 267 cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v; 268 /* printf(" cmd %x", v);*/ 269 } 270 #endif 271 } 272 273 int 274 cbsc_dma_isintr(struct ncr53c9x_softc *sc) 275 { 276 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 277 278 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 279 return 0; 280 281 if (sc->sc_state == NCR_CONNECTED) 282 csc->sc_portbits |= CBSC_PB_LED; 283 else 284 csc->sc_portbits &= ~CBSC_PB_LED; 285 csc->sc_reg[0x802] = csc->sc_portbits; 286 287 if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0) 288 return 0; 289 #ifdef DEBUG 290 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) { 291 cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 292 cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 293 cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active; 294 cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127; 295 } 296 #endif 297 return 1; 298 } 299 300 void 301 cbsc_dma_reset(struct ncr53c9x_softc *sc) 302 { 303 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 304 305 csc->sc_active = 0; 306 } 307 308 int 309 cbsc_dma_intr(struct ncr53c9x_softc *sc) 310 { 311 register struct cbsc_softc *csc = (struct cbsc_softc *)sc; 312 register int cnt; 313 314 NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ", 315 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 316 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 317 if (csc->sc_active == 0) { 318 printf("cbsc_intr--inactive DMA\n"); 319 return -1; 320 } 321 322 /* update sc_dmaaddr and sc_pdmalen */ 323 cnt = csc->sc_reg[NCR_TCL * 4]; 324 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 325 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 326 if (!csc->sc_datain) { 327 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 328 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 329 } 330 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 331 NCR_DMA(("DMA xferred %d\n", cnt)); 332 if (csc->sc_xfr_align) { 333 bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt); 334 csc->sc_xfr_align = 0; 335 } 336 *csc->sc_dmaaddr += cnt; 337 *csc->sc_pdmalen -= cnt; 338 csc->sc_active = 0; 339 return 0; 340 } 341 342 int 343 cbsc_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len, 344 int datain, size_t *dmasize) 345 { 346 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 347 paddr_t pa; 348 u_char *ptr; 349 size_t xfer; 350 351 csc->sc_dmaaddr = (char **)addr; 352 csc->sc_pdmalen = len; 353 csc->sc_datain = datain; 354 csc->sc_dmasize = *dmasize; 355 /* 356 * DMA can be nasty for high-speed serial input, so limit the 357 * size of this DMA operation if the serial port is running at 358 * a high speed (higher than 19200 for now - should be adjusted 359 * based on CPU type and speed?). 360 * XXX - add serial speed check XXX 361 */ 362 if (ser_open_speed > 19200 && cbsc_max_dma != 0 && 363 csc->sc_dmasize > cbsc_max_dma) 364 csc->sc_dmasize = cbsc_max_dma; 365 ptr = *addr; /* Kernel virtual address */ 366 pa = kvtop(ptr); /* Physical address of DMA */ 367 xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 368 csc->sc_xfr_align = 0; 369 /* 370 * If output and unaligned, stuff odd byte into FIFO 371 */ 372 if (datain == 0 && (int)ptr & 1) { 373 NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n")); 374 pa++; 375 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 376 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 377 } 378 /* 379 * If unaligned address, read unaligned bytes into alignment buffer 380 */ 381 else if ((int)ptr & 1) { 382 pa = kvtop((void *)&csc->sc_alignbuf); 383 xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf)); 384 NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer)); 385 csc->sc_xfr_align = 1; 386 } 387 ++cbsc_cnt_dma; /* number of DMA operations */ 388 389 while (xfer < csc->sc_dmasize) { 390 if ((pa + xfer) != kvtop((char*)*addr + xfer)) 391 break; 392 if ((csc->sc_dmasize - xfer) < PAGE_SIZE) 393 xfer = csc->sc_dmasize; 394 else 395 xfer += PAGE_SIZE; 396 ++cbsc_cnt_dma3; 397 } 398 if (xfer != *len) 399 ++cbsc_cnt_dma2; 400 401 csc->sc_dmasize = xfer; 402 *dmasize = csc->sc_dmasize; 403 csc->sc_pa = pa; 404 #if defined(M68040) || defined(M68060) 405 if (mmutype == MMU_68040) { 406 if (csc->sc_xfr_align) { 407 dma_cachectl(csc->sc_alignbuf, 408 sizeof(csc->sc_alignbuf)); 409 } 410 else 411 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 412 } 413 #endif 414 415 if (csc->sc_datain) 416 pa &= ~1; 417 else 418 pa |= 1; 419 csc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 420 csc->sc_dmabase[2] = (u_int8_t)(pa >> 16); 421 csc->sc_dmabase[4] = (u_int8_t)(pa >> 8); 422 csc->sc_dmabase[6] = (u_int8_t)(pa); 423 if (csc->sc_datain) 424 csc->sc_portbits &= ~CBSC_PB_WRITE; 425 else 426 csc->sc_portbits |= CBSC_PB_WRITE; 427 csc->sc_reg[0x802] = csc->sc_portbits; 428 csc->sc_active = 1; 429 return 0; 430 } 431 432 void 433 cbsc_dma_go(struct ncr53c9x_softc *sc) 434 { 435 } 436 437 void 438 cbsc_dma_stop(struct ncr53c9x_softc *sc) 439 { 440 } 441 442 int 443 cbsc_dma_isactive(struct ncr53c9x_softc *sc) 444 { 445 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 446 447 return csc->sc_active; 448 } 449 450 #ifdef DEBUG 451 void 452 cbsc_dump(void) 453 { 454 int i; 455 456 i = cbsc_trace_ptr; 457 printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr); 458 do { 459 if (cbsc_trace[i].hardbits == 0) { 460 i = (i + 1) & 127; 461 continue; 462 } 463 printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits, 464 cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy); 465 if (cbsc_trace[i].status & NCRSTAT_INT) 466 printf("NCRINT/"); 467 if (cbsc_trace[i].status & NCRSTAT_TC) 468 printf("NCRTC/"); 469 switch(cbsc_trace[i].status & NCRSTAT_PHASE) { 470 case 0: 471 printf("dataout"); break; 472 case 1: 473 printf("datain"); break; 474 case 2: 475 printf("cmdout"); break; 476 case 3: 477 printf("status"); break; 478 case 6: 479 printf("msgout"); break; 480 case 7: 481 printf("msgin"); break; 482 default: 483 printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE); 484 } 485 printf(") "); 486 i = (i + 1) & 127; 487 } while (i != cbsc_trace_ptr); 488 printf("\n"); 489 } 490 #endif 491