xref: /netbsd-src/sys/arch/amiga/dev/cbsc.c (revision 89c5a767f8fc7a4633b2d409966e2becbb98ff92) 
1 /*	$NetBSD: cbsc.c,v 1.10 1999/09/30 22:59:52 thorpej Exp $	*/
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/errno.h>
43 #include <sys/ioctl.h>
44 #include <sys/device.h>
45 #include <sys/buf.h>
46 #include <sys/proc.h>
47 #include <sys/user.h>
48 #include <sys/queue.h>
49 
50 #include <dev/scsipi/scsi_all.h>
51 #include <dev/scsipi/scsipi_all.h>
52 #include <dev/scsipi/scsiconf.h>
53 #include <dev/scsipi/scsi_message.h>
54 
55 #include <machine/cpu.h>
56 #include <machine/param.h>
57 
58 #include <dev/ic/ncr53c9xreg.h>
59 #include <dev/ic/ncr53c9xvar.h>
60 
61 #include <amiga/amiga/isr.h>
62 #include <amiga/dev/cbscvar.h>
63 #include <amiga/dev/zbusvar.h>
64 
65 void	cbscattach	__P((struct device *, struct device *, void *));
66 int	cbscmatch	__P((struct device *, struct cfdata *, void *));
67 
68 /* Linkup to the rest of the kernel */
69 struct cfattach cbsc_ca = {
70 	sizeof(struct cbsc_softc), cbscmatch, cbscattach
71 };
72 
73 struct scsipi_device cbsc_dev = {
74 	NULL,			/* Use default error handler */
75 	NULL,			/* have a queue, served by this */
76 	NULL,			/* have no async handler */
77 	NULL,			/* Use default 'done' routine */
78 };
79 
80 /*
81  * Functions and the switch for the MI code.
82  */
83 u_char	cbsc_read_reg __P((struct ncr53c9x_softc *, int));
84 void	cbsc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
85 int	cbsc_dma_isintr __P((struct ncr53c9x_softc *));
86 void	cbsc_dma_reset __P((struct ncr53c9x_softc *));
87 int	cbsc_dma_intr __P((struct ncr53c9x_softc *));
88 int	cbsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
89 	    size_t *, int, size_t *));
90 void	cbsc_dma_go __P((struct ncr53c9x_softc *));
91 void	cbsc_dma_stop __P((struct ncr53c9x_softc *));
92 int	cbsc_dma_isactive __P((struct ncr53c9x_softc *));
93 
94 struct ncr53c9x_glue cbsc_glue = {
95 	cbsc_read_reg,
96 	cbsc_write_reg,
97 	cbsc_dma_isintr,
98 	cbsc_dma_reset,
99 	cbsc_dma_intr,
100 	cbsc_dma_setup,
101 	cbsc_dma_go,
102 	cbsc_dma_stop,
103 	cbsc_dma_isactive,
104 	0,
105 };
106 
107 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
108 u_long cbsc_max_dma = 1024;
109 extern int ser_open_speed;
110 
111 u_long cbsc_cnt_pio = 0;	/* number of PIO transfers */
112 u_long cbsc_cnt_dma = 0;	/* number of DMA transfers */
113 u_long cbsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
114 u_long cbsc_cnt_dma3 = 0;	/* number of pages combined */
115 
116 #ifdef DEBUG
117 struct {
118 	u_char hardbits;
119 	u_char status;
120 	u_char xx;
121 	u_char yy;
122 } cbsc_trace[128];
123 int cbsc_trace_ptr = 0;
124 int cbsc_trace_enable = 1;
125 void cbsc_dump __P((void));
126 #endif
127 
128 /*
129  * if we are a Phase5 CyberSCSI [mark I?]
130  */
131 int
132 cbscmatch(parent, cf, aux)
133 	struct device *parent;
134 	struct cfdata *cf;
135 	void *aux;
136 {
137 	struct zbus_args *zap;
138 	volatile u_char *regs;
139 
140 	zap = aux;
141 	if (zap->manid != 0x2140)
142 		return(0);		/* It's not Phase5 */
143 	if (zap->prodid != 12 && zap->prodid != 11)
144 		return(0);		/* Not CyberStorm MKI SCSI */
145 	if (zap->prodid == 11 && iszthreepa(zap->pa))
146 		return(0);		/* Fastlane Z3! */
147 	regs = &((volatile u_char *)zap->va)[0xf400];
148 	if (badaddr((caddr_t)regs))
149 		return(0);
150 	regs[NCR_CFG1 * 4] = 0;
151 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
152 	delay(5);
153 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
154 		return(0);
155 	return(1);
156 }
157 
158 /*
159  * Attach this instance, and then all the sub-devices
160  */
161 void
162 cbscattach(parent, self, aux)
163 	struct device *parent, *self;
164 	void *aux;
165 {
166 	struct cbsc_softc *csc = (void *)self;
167 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
168 	struct zbus_args  *zap;
169 	extern u_long scsi_nosync;
170 	extern int shift_nosync;
171 	extern int ncr53c9x_debug;
172 
173 	/*
174 	 * Set up the glue for MI code early; we use some of it here.
175 	 */
176 	sc->sc_glue = &cbsc_glue;
177 
178 	/*
179 	 * Save the regs
180 	 */
181 	zap = aux;
182 	csc->sc_reg = &((volatile u_char *)zap->va)[0xf400];
183 	csc->sc_dmabase = &csc->sc_reg[0x400];
184 
185 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
186 
187 	printf(": address %p", csc->sc_reg);
188 
189 	sc->sc_id = 7;
190 
191 	/*
192 	 * It is necessary to try to load the 2nd config register here,
193 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
194 	 * will not set up the defaults correctly.
195 	 */
196 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
197 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
198 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
199 	sc->sc_rev = NCR_VARIANT_FAS216;
200 
201 	/*
202 	 * This is the value used to start sync negotiations
203 	 * Note that the NCR register "SYNCTP" is programmed
204 	 * in "clocks per byte", and has a minimum value of 4.
205 	 * The SCSI period used in negotiation is one-fourth
206 	 * of the time (in nanoseconds) needed to transfer one byte.
207 	 * Since the chip's clock is given in MHz, we have the following
208 	 * formula: 4 * period = (1000 / freq) * 4
209 	 */
210 	sc->sc_minsync = 1000 / sc->sc_freq;
211 
212 	/*
213 	 * get flags from -I argument and set cf_flags.
214 	 * NOTE: low 8 bits are to disable disconnect, and the next
215 	 *       8 bits are to disable sync.
216 	 */
217 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
218 	    & 0xffff;
219 	shift_nosync += 16;
220 
221 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
222 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
223 	shift_nosync += 16;
224 
225 #if 1
226 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
227 		sc->sc_minsync = 0;
228 #endif
229 
230 	/* Really no limit, but since we want to fit into the TCR... */
231 	sc->sc_maxxfer = 64 * 1024;
232 
233 	/*
234 	 * Configure interrupts.
235 	 */
236 	csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
237 	csc->sc_isr.isr_arg  = sc;
238 	csc->sc_isr.isr_ipl  = 2;
239 	add_isr(&csc->sc_isr);
240 
241 	/*
242 	 * Now try to attach all the sub-devices
243 	 */
244 	sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
245 	sc->sc_adapter.scsipi_minphys = minphys;
246 	ncr53c9x_attach(sc, &cbsc_dev);
247 }
248 
249 /*
250  * Glue functions.
251  */
252 
253 u_char
254 cbsc_read_reg(sc, reg)
255 	struct ncr53c9x_softc *sc;
256 	int reg;
257 {
258 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
259 
260 	return csc->sc_reg[reg * 4];
261 }
262 
263 void
264 cbsc_write_reg(sc, reg, val)
265 	struct ncr53c9x_softc *sc;
266 	int reg;
267 	u_char val;
268 {
269 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
270 	u_char v = val;
271 
272 	csc->sc_reg[reg * 4] = v;
273 #ifdef DEBUG
274 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
275   reg == NCR_CMD/* && csc->sc_active*/) {
276   cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v;
277 /*  printf(" cmd %x", v);*/
278 }
279 #endif
280 }
281 
282 int
283 cbsc_dma_isintr(sc)
284 	struct ncr53c9x_softc *sc;
285 {
286 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
287 
288 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
289 		return 0;
290 
291 	if (sc->sc_state == NCR_CONNECTED)
292 		csc->sc_portbits |= CBSC_PB_LED;
293 	else
294 		csc->sc_portbits &= ~CBSC_PB_LED;
295 	csc->sc_reg[0x802] = csc->sc_portbits;
296 
297 	if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0)
298 		return 0;
299 #ifdef DEBUG
300 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) {
301   cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
302   cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
303   cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active;
304   cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127;
305 }
306 #endif
307 	return 1;
308 }
309 
310 void
311 cbsc_dma_reset(sc)
312 	struct ncr53c9x_softc *sc;
313 {
314 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
315 
316 	csc->sc_active = 0;
317 }
318 
319 int
320 cbsc_dma_intr(sc)
321 	struct ncr53c9x_softc *sc;
322 {
323 	register struct cbsc_softc *csc = (struct cbsc_softc *)sc;
324 	register int	cnt;
325 
326 	NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ",
327 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
328 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
329 	if (csc->sc_active == 0) {
330 		printf("cbsc_intr--inactive DMA\n");
331 		return -1;
332 	}
333 
334 	/* update sc_dmaaddr and sc_pdmalen */
335 	cnt = csc->sc_reg[NCR_TCL * 4];
336 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
337 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
338 	if (!csc->sc_datain) {
339 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
340 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
341 	}
342 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
343 	NCR_DMA(("DMA xferred %d\n", cnt));
344 	if (csc->sc_xfr_align) {
345 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
346 		csc->sc_xfr_align = 0;
347 	}
348 	*csc->sc_dmaaddr += cnt;
349 	*csc->sc_pdmalen -= cnt;
350 	csc->sc_active = 0;
351 	return 0;
352 }
353 
354 int
355 cbsc_dma_setup(sc, addr, len, datain, dmasize)
356 	struct ncr53c9x_softc *sc;
357 	caddr_t *addr;
358 	size_t *len;
359 	int datain;
360 	size_t *dmasize;
361 {
362 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
363 	paddr_t pa;
364 	u_char *ptr;
365 	size_t xfer;
366 
367 	csc->sc_dmaaddr = addr;
368 	csc->sc_pdmalen = len;
369 	csc->sc_datain = datain;
370 	csc->sc_dmasize = *dmasize;
371 	/*
372 	 * DMA can be nasty for high-speed serial input, so limit the
373 	 * size of this DMA operation if the serial port is running at
374 	 * a high speed (higher than 19200 for now - should be adjusted
375 	 * based on cpu type and speed?).
376 	 * XXX - add serial speed check XXX
377 	 */
378 	if (ser_open_speed > 19200 && cbsc_max_dma != 0 &&
379 	    csc->sc_dmasize > cbsc_max_dma)
380 		csc->sc_dmasize = cbsc_max_dma;
381 	ptr = *addr;			/* Kernel virtual address */
382 	pa = kvtop(ptr);		/* Physical address of DMA */
383 	xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
384 	csc->sc_xfr_align = 0;
385 	/*
386 	 * If output and unaligned, stuff odd byte into FIFO
387 	 */
388 	if (datain == 0 && (int)ptr & 1) {
389 		NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n"));
390 		pa++;
391 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
392 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
393 	}
394 	/*
395 	 * If unaligned address, read unaligned bytes into alignment buffer
396 	 */
397 	else if ((int)ptr & 1) {
398 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
399 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
400 		NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer));
401 		csc->sc_xfr_align = 1;
402 	}
403 ++cbsc_cnt_dma;		/* number of DMA operations */
404 
405 	while (xfer < csc->sc_dmasize) {
406 		if ((pa + xfer) != kvtop(*addr + xfer))
407 			break;
408 		if ((csc->sc_dmasize - xfer) < NBPG)
409 			xfer = csc->sc_dmasize;
410 		else
411 			xfer += NBPG;
412 ++cbsc_cnt_dma3;
413 	}
414 if (xfer != *len)
415   ++cbsc_cnt_dma2;
416 
417 	csc->sc_dmasize = xfer;
418 	*dmasize = csc->sc_dmasize;
419 	csc->sc_pa = pa;
420 #if defined(M68040) || defined(M68060)
421 	if (mmutype == MMU_68040) {
422 		if (csc->sc_xfr_align) {
423 			dma_cachectl(csc->sc_alignbuf,
424 			    sizeof(csc->sc_alignbuf));
425 		}
426 		else
427 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
428 	}
429 #endif
430 
431 	if (csc->sc_datain)
432 		pa &= ~1;
433 	else
434 		pa |= 1;
435 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
436 	csc->sc_dmabase[2] = (u_int8_t)(pa >> 16);
437 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 8);
438 	csc->sc_dmabase[6] = (u_int8_t)(pa);
439 	if (csc->sc_datain)
440 		csc->sc_portbits &= ~CBSC_PB_WRITE;
441 	else
442 		csc->sc_portbits |= CBSC_PB_WRITE;
443 	csc->sc_reg[0x802] = csc->sc_portbits;
444 	csc->sc_active = 1;
445 	return 0;
446 }
447 
448 void
449 cbsc_dma_go(sc)
450 	struct ncr53c9x_softc *sc;
451 {
452 }
453 
454 void
455 cbsc_dma_stop(sc)
456 	struct ncr53c9x_softc *sc;
457 {
458 }
459 
460 int
461 cbsc_dma_isactive(sc)
462 	struct ncr53c9x_softc *sc;
463 {
464 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
465 
466 	return csc->sc_active;
467 }
468 
469 #ifdef DEBUG
470 void
471 cbsc_dump()
472 {
473 	int i;
474 
475 	i = cbsc_trace_ptr;
476 	printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr);
477 	do {
478 		if (cbsc_trace[i].hardbits == 0) {
479 			i = (i + 1) & 127;
480 			continue;
481 		}
482 		printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits,
483 		    cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy);
484 		if (cbsc_trace[i].status & NCRSTAT_INT)
485 			printf("NCRINT/");
486 		if (cbsc_trace[i].status & NCRSTAT_TC)
487 			printf("NCRTC/");
488 		switch(cbsc_trace[i].status & NCRSTAT_PHASE) {
489 		case 0:
490 			printf("dataout"); break;
491 		case 1:
492 			printf("datain"); break;
493 		case 2:
494 			printf("cmdout"); break;
495 		case 3:
496 			printf("status"); break;
497 		case 6:
498 			printf("msgout"); break;
499 		case 7:
500 			printf("msgin"); break;
501 		default:
502 			printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE);
503 		}
504 		printf(") ");
505 		i = (i + 1) & 127;
506 	} while (i != cbsc_trace_ptr);
507 	printf("\n");
508 }
509 #endif
510