xref: /netbsd-src/sys/arch/amiga/dev/cbsc.c (revision 4472dbe5e3bd91ef2540bada7a7ca7384627ff9b) 
1 /*	$NetBSD: cbsc.c,v 1.11 2000/06/05 15:08:03 tsutsui Exp $	*/
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/errno.h>
43 #include <sys/ioctl.h>
44 #include <sys/device.h>
45 #include <sys/buf.h>
46 #include <sys/proc.h>
47 #include <sys/user.h>
48 #include <sys/queue.h>
49 
50 #include <dev/scsipi/scsi_all.h>
51 #include <dev/scsipi/scsipi_all.h>
52 #include <dev/scsipi/scsiconf.h>
53 #include <dev/scsipi/scsi_message.h>
54 
55 #include <machine/cpu.h>
56 #include <machine/param.h>
57 
58 #include <dev/ic/ncr53c9xreg.h>
59 #include <dev/ic/ncr53c9xvar.h>
60 
61 #include <amiga/amiga/isr.h>
62 #include <amiga/dev/cbscvar.h>
63 #include <amiga/dev/zbusvar.h>
64 
65 void	cbscattach	__P((struct device *, struct device *, void *));
66 int	cbscmatch	__P((struct device *, struct cfdata *, void *));
67 
68 /* Linkup to the rest of the kernel */
69 struct cfattach cbsc_ca = {
70 	sizeof(struct cbsc_softc), cbscmatch, cbscattach
71 };
72 
73 /*
74  * Functions and the switch for the MI code.
75  */
76 u_char	cbsc_read_reg __P((struct ncr53c9x_softc *, int));
77 void	cbsc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
78 int	cbsc_dma_isintr __P((struct ncr53c9x_softc *));
79 void	cbsc_dma_reset __P((struct ncr53c9x_softc *));
80 int	cbsc_dma_intr __P((struct ncr53c9x_softc *));
81 int	cbsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
82 	    size_t *, int, size_t *));
83 void	cbsc_dma_go __P((struct ncr53c9x_softc *));
84 void	cbsc_dma_stop __P((struct ncr53c9x_softc *));
85 int	cbsc_dma_isactive __P((struct ncr53c9x_softc *));
86 
87 struct ncr53c9x_glue cbsc_glue = {
88 	cbsc_read_reg,
89 	cbsc_write_reg,
90 	cbsc_dma_isintr,
91 	cbsc_dma_reset,
92 	cbsc_dma_intr,
93 	cbsc_dma_setup,
94 	cbsc_dma_go,
95 	cbsc_dma_stop,
96 	cbsc_dma_isactive,
97 	0,
98 };
99 
100 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
101 u_long cbsc_max_dma = 1024;
102 extern int ser_open_speed;
103 
104 u_long cbsc_cnt_pio = 0;	/* number of PIO transfers */
105 u_long cbsc_cnt_dma = 0;	/* number of DMA transfers */
106 u_long cbsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
107 u_long cbsc_cnt_dma3 = 0;	/* number of pages combined */
108 
109 #ifdef DEBUG
110 struct {
111 	u_char hardbits;
112 	u_char status;
113 	u_char xx;
114 	u_char yy;
115 } cbsc_trace[128];
116 int cbsc_trace_ptr = 0;
117 int cbsc_trace_enable = 1;
118 void cbsc_dump __P((void));
119 #endif
120 
121 /*
122  * if we are a Phase5 CyberSCSI [mark I?]
123  */
124 int
125 cbscmatch(parent, cf, aux)
126 	struct device *parent;
127 	struct cfdata *cf;
128 	void *aux;
129 {
130 	struct zbus_args *zap;
131 	volatile u_char *regs;
132 
133 	zap = aux;
134 	if (zap->manid != 0x2140)
135 		return(0);		/* It's not Phase5 */
136 	if (zap->prodid != 12 && zap->prodid != 11)
137 		return(0);		/* Not CyberStorm MKI SCSI */
138 	if (zap->prodid == 11 && iszthreepa(zap->pa))
139 		return(0);		/* Fastlane Z3! */
140 	regs = &((volatile u_char *)zap->va)[0xf400];
141 	if (badaddr((caddr_t)regs))
142 		return(0);
143 	regs[NCR_CFG1 * 4] = 0;
144 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
145 	delay(5);
146 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
147 		return(0);
148 	return(1);
149 }
150 
151 /*
152  * Attach this instance, and then all the sub-devices
153  */
154 void
155 cbscattach(parent, self, aux)
156 	struct device *parent, *self;
157 	void *aux;
158 {
159 	struct cbsc_softc *csc = (void *)self;
160 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
161 	struct zbus_args  *zap;
162 	extern u_long scsi_nosync;
163 	extern int shift_nosync;
164 	extern int ncr53c9x_debug;
165 
166 	/*
167 	 * Set up the glue for MI code early; we use some of it here.
168 	 */
169 	sc->sc_glue = &cbsc_glue;
170 
171 	/*
172 	 * Save the regs
173 	 */
174 	zap = aux;
175 	csc->sc_reg = &((volatile u_char *)zap->va)[0xf400];
176 	csc->sc_dmabase = &csc->sc_reg[0x400];
177 
178 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
179 
180 	printf(": address %p", csc->sc_reg);
181 
182 	sc->sc_id = 7;
183 
184 	/*
185 	 * It is necessary to try to load the 2nd config register here,
186 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
187 	 * will not set up the defaults correctly.
188 	 */
189 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
190 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
191 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
192 	sc->sc_rev = NCR_VARIANT_FAS216;
193 
194 	/*
195 	 * This is the value used to start sync negotiations
196 	 * Note that the NCR register "SYNCTP" is programmed
197 	 * in "clocks per byte", and has a minimum value of 4.
198 	 * The SCSI period used in negotiation is one-fourth
199 	 * of the time (in nanoseconds) needed to transfer one byte.
200 	 * Since the chip's clock is given in MHz, we have the following
201 	 * formula: 4 * period = (1000 / freq) * 4
202 	 */
203 	sc->sc_minsync = 1000 / sc->sc_freq;
204 
205 	/*
206 	 * get flags from -I argument and set cf_flags.
207 	 * NOTE: low 8 bits are to disable disconnect, and the next
208 	 *       8 bits are to disable sync.
209 	 */
210 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
211 	    & 0xffff;
212 	shift_nosync += 16;
213 
214 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
215 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
216 	shift_nosync += 16;
217 
218 #if 1
219 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
220 		sc->sc_minsync = 0;
221 #endif
222 
223 	/* Really no limit, but since we want to fit into the TCR... */
224 	sc->sc_maxxfer = 64 * 1024;
225 
226 	/*
227 	 * Configure interrupts.
228 	 */
229 	csc->sc_isr.isr_intr = ncr53c9x_intr;
230 	csc->sc_isr.isr_arg  = sc;
231 	csc->sc_isr.isr_ipl  = 2;
232 	add_isr(&csc->sc_isr);
233 
234 	/*
235 	 * Now try to attach all the sub-devices
236 	 */
237 	ncr53c9x_attach(sc, NULL, NULL);
238 }
239 
240 /*
241  * Glue functions.
242  */
243 
244 u_char
245 cbsc_read_reg(sc, reg)
246 	struct ncr53c9x_softc *sc;
247 	int reg;
248 {
249 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
250 
251 	return csc->sc_reg[reg * 4];
252 }
253 
254 void
255 cbsc_write_reg(sc, reg, val)
256 	struct ncr53c9x_softc *sc;
257 	int reg;
258 	u_char val;
259 {
260 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
261 	u_char v = val;
262 
263 	csc->sc_reg[reg * 4] = v;
264 #ifdef DEBUG
265 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
266   reg == NCR_CMD/* && csc->sc_active*/) {
267   cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v;
268 /*  printf(" cmd %x", v);*/
269 }
270 #endif
271 }
272 
273 int
274 cbsc_dma_isintr(sc)
275 	struct ncr53c9x_softc *sc;
276 {
277 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
278 
279 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
280 		return 0;
281 
282 	if (sc->sc_state == NCR_CONNECTED)
283 		csc->sc_portbits |= CBSC_PB_LED;
284 	else
285 		csc->sc_portbits &= ~CBSC_PB_LED;
286 	csc->sc_reg[0x802] = csc->sc_portbits;
287 
288 	if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0)
289 		return 0;
290 #ifdef DEBUG
291 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) {
292   cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
293   cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
294   cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active;
295   cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127;
296 }
297 #endif
298 	return 1;
299 }
300 
301 void
302 cbsc_dma_reset(sc)
303 	struct ncr53c9x_softc *sc;
304 {
305 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
306 
307 	csc->sc_active = 0;
308 }
309 
310 int
311 cbsc_dma_intr(sc)
312 	struct ncr53c9x_softc *sc;
313 {
314 	register struct cbsc_softc *csc = (struct cbsc_softc *)sc;
315 	register int	cnt;
316 
317 	NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ",
318 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
319 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
320 	if (csc->sc_active == 0) {
321 		printf("cbsc_intr--inactive DMA\n");
322 		return -1;
323 	}
324 
325 	/* update sc_dmaaddr and sc_pdmalen */
326 	cnt = csc->sc_reg[NCR_TCL * 4];
327 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
328 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
329 	if (!csc->sc_datain) {
330 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
331 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
332 	}
333 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
334 	NCR_DMA(("DMA xferred %d\n", cnt));
335 	if (csc->sc_xfr_align) {
336 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
337 		csc->sc_xfr_align = 0;
338 	}
339 	*csc->sc_dmaaddr += cnt;
340 	*csc->sc_pdmalen -= cnt;
341 	csc->sc_active = 0;
342 	return 0;
343 }
344 
345 int
346 cbsc_dma_setup(sc, addr, len, datain, dmasize)
347 	struct ncr53c9x_softc *sc;
348 	caddr_t *addr;
349 	size_t *len;
350 	int datain;
351 	size_t *dmasize;
352 {
353 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
354 	paddr_t pa;
355 	u_char *ptr;
356 	size_t xfer;
357 
358 	csc->sc_dmaaddr = addr;
359 	csc->sc_pdmalen = len;
360 	csc->sc_datain = datain;
361 	csc->sc_dmasize = *dmasize;
362 	/*
363 	 * DMA can be nasty for high-speed serial input, so limit the
364 	 * size of this DMA operation if the serial port is running at
365 	 * a high speed (higher than 19200 for now - should be adjusted
366 	 * based on cpu type and speed?).
367 	 * XXX - add serial speed check XXX
368 	 */
369 	if (ser_open_speed > 19200 && cbsc_max_dma != 0 &&
370 	    csc->sc_dmasize > cbsc_max_dma)
371 		csc->sc_dmasize = cbsc_max_dma;
372 	ptr = *addr;			/* Kernel virtual address */
373 	pa = kvtop(ptr);		/* Physical address of DMA */
374 	xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
375 	csc->sc_xfr_align = 0;
376 	/*
377 	 * If output and unaligned, stuff odd byte into FIFO
378 	 */
379 	if (datain == 0 && (int)ptr & 1) {
380 		NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n"));
381 		pa++;
382 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
383 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
384 	}
385 	/*
386 	 * If unaligned address, read unaligned bytes into alignment buffer
387 	 */
388 	else if ((int)ptr & 1) {
389 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
390 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
391 		NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer));
392 		csc->sc_xfr_align = 1;
393 	}
394 ++cbsc_cnt_dma;		/* number of DMA operations */
395 
396 	while (xfer < csc->sc_dmasize) {
397 		if ((pa + xfer) != kvtop(*addr + xfer))
398 			break;
399 		if ((csc->sc_dmasize - xfer) < NBPG)
400 			xfer = csc->sc_dmasize;
401 		else
402 			xfer += NBPG;
403 ++cbsc_cnt_dma3;
404 	}
405 if (xfer != *len)
406   ++cbsc_cnt_dma2;
407 
408 	csc->sc_dmasize = xfer;
409 	*dmasize = csc->sc_dmasize;
410 	csc->sc_pa = pa;
411 #if defined(M68040) || defined(M68060)
412 	if (mmutype == MMU_68040) {
413 		if (csc->sc_xfr_align) {
414 			dma_cachectl(csc->sc_alignbuf,
415 			    sizeof(csc->sc_alignbuf));
416 		}
417 		else
418 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
419 	}
420 #endif
421 
422 	if (csc->sc_datain)
423 		pa &= ~1;
424 	else
425 		pa |= 1;
426 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
427 	csc->sc_dmabase[2] = (u_int8_t)(pa >> 16);
428 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 8);
429 	csc->sc_dmabase[6] = (u_int8_t)(pa);
430 	if (csc->sc_datain)
431 		csc->sc_portbits &= ~CBSC_PB_WRITE;
432 	else
433 		csc->sc_portbits |= CBSC_PB_WRITE;
434 	csc->sc_reg[0x802] = csc->sc_portbits;
435 	csc->sc_active = 1;
436 	return 0;
437 }
438 
439 void
440 cbsc_dma_go(sc)
441 	struct ncr53c9x_softc *sc;
442 {
443 }
444 
445 void
446 cbsc_dma_stop(sc)
447 	struct ncr53c9x_softc *sc;
448 {
449 }
450 
451 int
452 cbsc_dma_isactive(sc)
453 	struct ncr53c9x_softc *sc;
454 {
455 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
456 
457 	return csc->sc_active;
458 }
459 
460 #ifdef DEBUG
461 void
462 cbsc_dump()
463 {
464 	int i;
465 
466 	i = cbsc_trace_ptr;
467 	printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr);
468 	do {
469 		if (cbsc_trace[i].hardbits == 0) {
470 			i = (i + 1) & 127;
471 			continue;
472 		}
473 		printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits,
474 		    cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy);
475 		if (cbsc_trace[i].status & NCRSTAT_INT)
476 			printf("NCRINT/");
477 		if (cbsc_trace[i].status & NCRSTAT_TC)
478 			printf("NCRTC/");
479 		switch(cbsc_trace[i].status & NCRSTAT_PHASE) {
480 		case 0:
481 			printf("dataout"); break;
482 		case 1:
483 			printf("datain"); break;
484 		case 2:
485 			printf("cmdout"); break;
486 		case 3:
487 			printf("status"); break;
488 		case 6:
489 			printf("msgout"); break;
490 		case 7:
491 			printf("msgin"); break;
492 		default:
493 			printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE);
494 		}
495 		printf(") ");
496 		i = (i + 1) & 127;
497 	} while (i != cbsc_trace_ptr);
498 	printf("\n");
499 }
500 #endif
501