xref: /netbsd-src/sys/arch/amiga/dev/cbsc.c (revision 2a399c6883d870daece976daec6ffa7bb7f934ce) 
1 /*	$NetBSD: cbsc.c,v 1.2 1997/10/24 01:43:57 mhitch Exp $	*/
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/errno.h>
43 #include <sys/ioctl.h>
44 #include <sys/device.h>
45 #include <sys/buf.h>
46 #include <sys/proc.h>
47 #include <sys/user.h>
48 #include <sys/queue.h>
49 
50 #include <dev/scsipi/scsi_all.h>
51 #include <dev/scsipi/scsipi_all.h>
52 #include <dev/scsipi/scsiconf.h>
53 #include <dev/scsipi/scsi_message.h>
54 
55 #include <machine/cpu.h>
56 #include <machine/param.h>
57 
58 #include <dev/ic/ncr53c9xreg.h>
59 #include <dev/ic/ncr53c9xvar.h>
60 
61 #include <amiga/amiga/isr.h>
62 #include <amiga/dev/cbscvar.h>
63 #include <amiga/dev/zbusvar.h>
64 
65 void	cbscattach	__P((struct device *, struct device *, void *));
66 int	cbscmatch	__P((struct device *, struct cfdata *, void *));
67 
68 /* Linkup to the rest of the kernel */
69 struct cfattach cbsc_ca = {
70 	sizeof(struct cbsc_softc), cbscmatch, cbscattach
71 };
72 
73 struct cfdriver cbsc_cd = {
74 	NULL, "cbsc", DV_DULL
75 };
76 
77 struct scsipi_adapter cbsc_switch = {
78 	ncr53c9x_scsi_cmd,
79 	minphys,		/* no max at this level; handled by DMA code */
80 	NULL,
81 	NULL,
82 };
83 
84 struct scsipi_device cbsc_dev = {
85 	NULL,			/* Use default error handler */
86 	NULL,			/* have a queue, served by this */
87 	NULL,			/* have no async handler */
88 	NULL,			/* Use default 'done' routine */
89 };
90 
91 /*
92  * Functions and the switch for the MI code.
93  */
94 u_char	cbsc_read_reg __P((struct ncr53c9x_softc *, int));
95 void	cbsc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
96 int	cbsc_dma_isintr __P((struct ncr53c9x_softc *));
97 void	cbsc_dma_reset __P((struct ncr53c9x_softc *));
98 int	cbsc_dma_intr __P((struct ncr53c9x_softc *));
99 int	cbsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
100 	    size_t *, int, size_t *));
101 void	cbsc_dma_go __P((struct ncr53c9x_softc *));
102 void	cbsc_dma_stop __P((struct ncr53c9x_softc *));
103 int	cbsc_dma_isactive __P((struct ncr53c9x_softc *));
104 
105 struct ncr53c9x_glue cbsc_glue = {
106 	cbsc_read_reg,
107 	cbsc_write_reg,
108 	cbsc_dma_isintr,
109 	cbsc_dma_reset,
110 	cbsc_dma_intr,
111 	cbsc_dma_setup,
112 	cbsc_dma_go,
113 	cbsc_dma_stop,
114 	cbsc_dma_isactive,
115 	0,
116 };
117 
118 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
119 u_long cbsc_max_dma = 1024;
120 extern int ser_open_speed;
121 
122 u_long cbsc_cnt_pio = 0;	/* number of PIO transfers */
123 u_long cbsc_cnt_dma = 0;	/* number of DMA transfers */
124 u_long cbsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
125 u_long cbsc_cnt_dma3 = 0;	/* number of pages combined */
126 
127 #ifdef DEBUG
128 struct {
129 	u_char hardbits;
130 	u_char status;
131 	u_char xx;
132 	u_char yy;
133 } cbsc_trace[128];
134 int cbsc_trace_ptr = 0;
135 int cbsc_trace_enable = 1;
136 void cbsc_dump __P((void));
137 #endif
138 
139 /*
140  * if we are a Phase5 CyberSCSI [mark I?]
141  */
142 int
143 cbscmatch(parent, cf, aux)
144 	struct device *parent;
145 	struct cfdata *cf;
146 	void *aux;
147 {
148 	struct zbus_args *zap;
149 	volatile u_char *regs;
150 
151 	zap = aux;
152 	if (zap->manid != 0x2140 || zap->prodid != 12)
153 		return(0);
154 	regs = &((volatile u_char *)zap->va)[0xf400];
155 	if (badaddr((caddr_t)regs))
156 		return(0);
157 	regs[NCR_CFG1 * 4] = 0;
158 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
159 	delay(5);
160 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
161 		return(0);
162 	return(1);
163 }
164 
165 /*
166  * Attach this instance, and then all the sub-devices
167  */
168 void
169 cbscattach(parent, self, aux)
170 	struct device *parent, *self;
171 	void *aux;
172 {
173 	struct cbsc_softc *csc = (void *)self;
174 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
175 	struct zbus_args  *zap;
176 	extern u_long scsi_nosync;
177 	extern int shift_nosync;
178 	extern int ncr53c9x_debug;
179 
180 	/*
181 	 * Set up the glue for MI code early; we use some of it here.
182 	 */
183 	sc->sc_glue = &cbsc_glue;
184 
185 	/*
186 	 * Save the regs
187 	 */
188 	zap = aux;
189 	csc->sc_reg = &((volatile u_char *)zap->va)[0xf400];
190 	csc->sc_dmabase = &csc->sc_reg[0x400];
191 
192 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
193 
194 	printf(": address %p", csc->sc_reg);
195 
196 	sc->sc_id = 7;
197 
198 	/*
199 	 * It is necessary to try to load the 2nd config register here,
200 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
201 	 * will not set up the defaults correctly.
202 	 */
203 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
204 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
205 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
206 	sc->sc_rev = NCR_VARIANT_FAS216;
207 
208 	/*
209 	 * This is the value used to start sync negotiations
210 	 * Note that the NCR register "SYNCTP" is programmed
211 	 * in "clocks per byte", and has a minimum value of 4.
212 	 * The SCSI period used in negotiation is one-fourth
213 	 * of the time (in nanoseconds) needed to transfer one byte.
214 	 * Since the chip's clock is given in MHz, we have the following
215 	 * formula: 4 * period = (1000 / freq) * 4
216 	 */
217 	sc->sc_minsync = 1000 / sc->sc_freq;
218 
219 	/*
220 	 * get flags from -I argument and set cf_flags.
221 	 * NOTE: low 8 bits are to disable disconnect, and the next
222 	 *       8 bits are to disable sync.
223 	 */
224 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
225 	    & 0xffff;
226 	shift_nosync += 16;
227 
228 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
229 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
230 	shift_nosync += 16;
231 
232 #if 1
233 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
234 		sc->sc_minsync = 0;
235 #endif
236 
237 	/* Really no limit, but since we want to fit into the TCR... */
238 	sc->sc_maxxfer = 64 * 1024;
239 
240 	/*
241 	 * Configure interrupts.
242 	 */
243 	csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
244 	csc->sc_isr.isr_arg  = sc;
245 	csc->sc_isr.isr_ipl  = 2;
246 	add_isr(&csc->sc_isr);
247 
248 	/*
249 	 * Now try to attach all the sub-devices
250 	 */
251 	ncr53c9x_attach(sc, &cbsc_switch, &cbsc_dev);
252 }
253 
254 /*
255  * Glue functions.
256  */
257 
258 u_char
259 cbsc_read_reg(sc, reg)
260 	struct ncr53c9x_softc *sc;
261 	int reg;
262 {
263 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
264 
265 	return csc->sc_reg[reg * 4];
266 }
267 
268 void
269 cbsc_write_reg(sc, reg, val)
270 	struct ncr53c9x_softc *sc;
271 	int reg;
272 	u_char val;
273 {
274 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
275 	u_char v = val;
276 
277 	csc->sc_reg[reg * 4] = v;
278 #ifdef DEBUG
279 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ &&
280   reg == NCR_CMD/* && csc->sc_active*/) {
281   cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v;
282 /*  printf(" cmd %x", v);*/
283 }
284 #endif
285 }
286 
287 int
288 cbsc_dma_isintr(sc)
289 	struct ncr53c9x_softc *sc;
290 {
291 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
292 
293 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
294 		return 0;
295 
296 	if (sc->sc_state == NCR_CONNECTED)
297 		csc->sc_portbits |= CBSC_PB_LED;
298 	else
299 		csc->sc_portbits &= ~CBSC_PB_LED;
300 	csc->sc_reg[0x802] = csc->sc_portbits;
301 
302 	if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0)
303 		return 0;
304 #ifdef DEBUG
305 if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ cbsc_trace_enable) {
306   cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
307   cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
308   cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active;
309   cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127;
310 }
311 #endif
312 	return 1;
313 }
314 
315 void
316 cbsc_dma_reset(sc)
317 	struct ncr53c9x_softc *sc;
318 {
319 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
320 
321 	csc->sc_active = 0;
322 }
323 
324 int
325 cbsc_dma_intr(sc)
326 	struct ncr53c9x_softc *sc;
327 {
328 	register struct cbsc_softc *csc = (struct cbsc_softc *)sc;
329 	register int	cnt;
330 
331 	NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ",
332 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
333 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
334 	if (csc->sc_active == 0) {
335 		printf("cbsc_intr--inactive DMA\n");
336 		return -1;
337 	}
338 
339 	/* update sc_dmaaddr and sc_pdmalen */
340 	cnt = csc->sc_reg[NCR_TCL * 4];
341 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
342 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
343 	if (!csc->sc_datain) {
344 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
345 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
346 	}
347 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
348 	NCR_DMA(("DMA xferred %d\n", cnt));
349 	if (csc->sc_xfr_align) {
350 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
351 		csc->sc_xfr_align = 0;
352 	}
353 	*csc->sc_dmaaddr += cnt;
354 	*csc->sc_pdmalen -= cnt;
355 	csc->sc_active = 0;
356 	return 0;
357 }
358 
359 int
360 cbsc_dma_setup(sc, addr, len, datain, dmasize)
361 	struct ncr53c9x_softc *sc;
362 	caddr_t *addr;
363 	size_t *len;
364 	int datain;
365 	size_t *dmasize;
366 {
367 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
368 	vm_offset_t pa;
369 	u_char *ptr;
370 	size_t xfer;
371 
372 	csc->sc_dmaaddr = addr;
373 	csc->sc_pdmalen = len;
374 	csc->sc_datain = datain;
375 	csc->sc_dmasize = *dmasize;
376 	/*
377 	 * DMA can be nasty for high-speed serial input, so limit the
378 	 * size of this DMA operation if the serial port is running at
379 	 * a high speed (higher than 19200 for now - should be adjusted
380 	 * based on cpu type and speed?).
381 	 * XXX - add serial speed check XXX
382 	 */
383 	if (ser_open_speed > 19200 && cbsc_max_dma != 0 &&
384 	    csc->sc_dmasize > cbsc_max_dma)
385 		csc->sc_dmasize = cbsc_max_dma;
386 	ptr = *addr;			/* Kernel virtual address */
387 	pa = kvtop(ptr);		/* Physical address of DMA */
388 	xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
389 	csc->sc_xfr_align = 0;
390 	/*
391 	 * If output and unaligned, stuff odd byte into FIFO
392 	 */
393 	if (datain == 0 && (int)ptr & 1) {
394 		NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n"));
395 		pa++;
396 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
397 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
398 	}
399 	/*
400 	 * If unaligned address, read unaligned bytes into alignment buffer
401 	 */
402 	else if ((int)ptr & 1) {
403 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
404 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
405 		NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer));
406 		csc->sc_xfr_align = 1;
407 	}
408 ++cbsc_cnt_dma;		/* number of DMA operations */
409 
410 	while (xfer < csc->sc_dmasize) {
411 		if ((pa + xfer) != kvtop(*addr + xfer))
412 			break;
413 		if ((csc->sc_dmasize - xfer) < NBPG)
414 			xfer = csc->sc_dmasize;
415 		else
416 			xfer += NBPG;
417 ++cbsc_cnt_dma3;
418 	}
419 if (xfer != *len)
420   ++cbsc_cnt_dma2;
421 
422 	csc->sc_dmasize = xfer;
423 	*dmasize = csc->sc_dmasize;
424 	csc->sc_pa = pa;
425 #if defined(M68040) || defined(M68060)
426 	if (mmutype == MMU_68040) {
427 		if (csc->sc_xfr_align) {
428 			dma_cachectl(csc->sc_alignbuf,
429 			    sizeof(csc->sc_alignbuf));
430 		}
431 		else
432 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
433 	}
434 #endif
435 
436 	if (csc->sc_datain)
437 		pa &= ~1;
438 	else
439 		pa |= 1;
440 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
441 	csc->sc_dmabase[2] = (u_int8_t)(pa >> 16);
442 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 8);
443 	csc->sc_dmabase[6] = (u_int8_t)(pa);
444 	if (csc->sc_datain)
445 		csc->sc_portbits &= ~CBSC_PB_WRITE;
446 	else
447 		csc->sc_portbits |= CBSC_PB_WRITE;
448 	csc->sc_reg[0x802] = csc->sc_portbits;
449 	csc->sc_active = 1;
450 	return 0;
451 }
452 
453 void
454 cbsc_dma_go(sc)
455 	struct ncr53c9x_softc *sc;
456 {
457 }
458 
459 void
460 cbsc_dma_stop(sc)
461 	struct ncr53c9x_softc *sc;
462 {
463 }
464 
465 int
466 cbsc_dma_isactive(sc)
467 	struct ncr53c9x_softc *sc;
468 {
469 	struct cbsc_softc *csc = (struct cbsc_softc *)sc;
470 
471 	return csc->sc_active;
472 }
473 
474 #ifdef DEBUG
475 void
476 cbsc_dump()
477 {
478 	int i;
479 
480 	i = cbsc_trace_ptr;
481 	printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr);
482 	do {
483 		if (cbsc_trace[i].hardbits == 0) {
484 			i = (i + 1) & 127;
485 			continue;
486 		}
487 		printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits,
488 		    cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy);
489 		if (cbsc_trace[i].status & NCRSTAT_INT)
490 			printf("NCRINT/");
491 		if (cbsc_trace[i].status & NCRSTAT_TC)
492 			printf("NCRTC/");
493 		switch(cbsc_trace[i].status & NCRSTAT_PHASE) {
494 		case 0:
495 			printf("dataout"); break;
496 		case 1:
497 			printf("datain"); break;
498 		case 2:
499 			printf("cmdout"); break;
500 		case 3:
501 			printf("status"); break;
502 		case 6:
503 			printf("msgout"); break;
504 		case 7:
505 			printf("msgin"); break;
506 		default:
507 			printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE);
508 		}
509 		printf(") ");
510 		i = (i + 1) & 127;
511 	} while (i != cbsc_trace_ptr);
512 	printf("\n");
513 }
514 #endif
515