1 /* $NetBSD: cbsc.c,v 1.12 2001/04/25 17:53:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/ioctl.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/queue.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsipi_all.h> 52 #include <dev/scsipi/scsiconf.h> 53 #include <dev/scsipi/scsi_message.h> 54 55 #include <machine/cpu.h> 56 #include <machine/param.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 #include <amiga/amiga/isr.h> 62 #include <amiga/dev/cbscvar.h> 63 #include <amiga/dev/zbusvar.h> 64 65 void cbscattach __P((struct device *, struct device *, void *)); 66 int cbscmatch __P((struct device *, struct cfdata *, void *)); 67 68 /* Linkup to the rest of the kernel */ 69 struct cfattach cbsc_ca = { 70 sizeof(struct cbsc_softc), cbscmatch, cbscattach 71 }; 72 73 /* 74 * Functions and the switch for the MI code. 75 */ 76 u_char cbsc_read_reg __P((struct ncr53c9x_softc *, int)); 77 void cbsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 78 int cbsc_dma_isintr __P((struct ncr53c9x_softc *)); 79 void cbsc_dma_reset __P((struct ncr53c9x_softc *)); 80 int cbsc_dma_intr __P((struct ncr53c9x_softc *)); 81 int cbsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 82 size_t *, int, size_t *)); 83 void cbsc_dma_go __P((struct ncr53c9x_softc *)); 84 void cbsc_dma_stop __P((struct ncr53c9x_softc *)); 85 int cbsc_dma_isactive __P((struct ncr53c9x_softc *)); 86 87 struct ncr53c9x_glue cbsc_glue = { 88 cbsc_read_reg, 89 cbsc_write_reg, 90 cbsc_dma_isintr, 91 cbsc_dma_reset, 92 cbsc_dma_intr, 93 cbsc_dma_setup, 94 cbsc_dma_go, 95 cbsc_dma_stop, 96 cbsc_dma_isactive, 97 0, 98 }; 99 100 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 101 u_long cbsc_max_dma = 1024; 102 extern int ser_open_speed; 103 104 u_long cbsc_cnt_pio = 0; /* number of PIO transfers */ 105 u_long cbsc_cnt_dma = 0; /* number of DMA transfers */ 106 u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 107 u_long cbsc_cnt_dma3 = 0; /* number of pages combined */ 108 109 #ifdef DEBUG 110 struct { 111 u_char hardbits; 112 u_char status; 113 u_char xx; 114 u_char yy; 115 } cbsc_trace[128]; 116 int cbsc_trace_ptr = 0; 117 int cbsc_trace_enable = 1; 118 void cbsc_dump __P((void)); 119 #endif 120 121 /* 122 * if we are a Phase5 CyberSCSI [mark I?] 123 */ 124 int 125 cbscmatch(parent, cf, aux) 126 struct device *parent; 127 struct cfdata *cf; 128 void *aux; 129 { 130 struct zbus_args *zap; 131 volatile u_char *regs; 132 133 zap = aux; 134 if (zap->manid != 0x2140) 135 return(0); /* It's not Phase5 */ 136 if (zap->prodid != 12 && zap->prodid != 11) 137 return(0); /* Not CyberStorm MKI SCSI */ 138 if (zap->prodid == 11 && iszthreepa(zap->pa)) 139 return(0); /* Fastlane Z3! */ 140 regs = &((volatile u_char *)zap->va)[0xf400]; 141 if (badaddr((caddr_t)regs)) 142 return(0); 143 regs[NCR_CFG1 * 4] = 0; 144 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 145 delay(5); 146 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 147 return(0); 148 return(1); 149 } 150 151 /* 152 * Attach this instance, and then all the sub-devices 153 */ 154 void 155 cbscattach(parent, self, aux) 156 struct device *parent, *self; 157 void *aux; 158 { 159 struct cbsc_softc *csc = (void *)self; 160 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 161 struct zbus_args *zap; 162 extern u_long scsi_nosync; 163 extern int shift_nosync; 164 extern int ncr53c9x_debug; 165 166 /* 167 * Set up the glue for MI code early; we use some of it here. 168 */ 169 sc->sc_glue = &cbsc_glue; 170 171 /* 172 * Save the regs 173 */ 174 zap = aux; 175 csc->sc_reg = &((volatile u_char *)zap->va)[0xf400]; 176 csc->sc_dmabase = &csc->sc_reg[0x400]; 177 178 sc->sc_freq = 40; /* Clocked at 40Mhz */ 179 180 printf(": address %p", csc->sc_reg); 181 182 sc->sc_id = 7; 183 184 /* 185 * It is necessary to try to load the 2nd config register here, 186 * to find out what rev the FAS chip is, else the ncr53c9x_reset 187 * will not set up the defaults correctly. 188 */ 189 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 190 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 191 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 192 sc->sc_rev = NCR_VARIANT_FAS216; 193 194 /* 195 * This is the value used to start sync negotiations 196 * Note that the NCR register "SYNCTP" is programmed 197 * in "clocks per byte", and has a minimum value of 4. 198 * The SCSI period used in negotiation is one-fourth 199 * of the time (in nanoseconds) needed to transfer one byte. 200 * Since the chip's clock is given in MHz, we have the following 201 * formula: 4 * period = (1000 / freq) * 4 202 */ 203 sc->sc_minsync = 1000 / sc->sc_freq; 204 205 /* 206 * get flags from -I argument and set cf_flags. 207 * NOTE: low 8 bits are to disable disconnect, and the next 208 * 8 bits are to disable sync. 209 */ 210 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 211 & 0xffff; 212 shift_nosync += 16; 213 214 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 215 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 216 shift_nosync += 16; 217 218 #if 1 219 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 220 sc->sc_minsync = 0; 221 #endif 222 223 /* Really no limit, but since we want to fit into the TCR... */ 224 sc->sc_maxxfer = 64 * 1024; 225 226 /* 227 * Configure interrupts. 228 */ 229 csc->sc_isr.isr_intr = ncr53c9x_intr; 230 csc->sc_isr.isr_arg = sc; 231 csc->sc_isr.isr_ipl = 2; 232 add_isr(&csc->sc_isr); 233 234 /* 235 * Now try to attach all the sub-devices 236 */ 237 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 238 sc->sc_adapter.adapt_minphys = minphys; 239 ncr53c9x_attach(sc); 240 } 241 242 /* 243 * Glue functions. 244 */ 245 246 u_char 247 cbsc_read_reg(sc, reg) 248 struct ncr53c9x_softc *sc; 249 int reg; 250 { 251 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 252 253 return csc->sc_reg[reg * 4]; 254 } 255 256 void 257 cbsc_write_reg(sc, reg, val) 258 struct ncr53c9x_softc *sc; 259 int reg; 260 u_char val; 261 { 262 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 263 u_char v = val; 264 265 csc->sc_reg[reg * 4] = v; 266 #ifdef DEBUG 267 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 268 reg == NCR_CMD/* && csc->sc_active*/) { 269 cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v; 270 /* printf(" cmd %x", v);*/ 271 } 272 #endif 273 } 274 275 int 276 cbsc_dma_isintr(sc) 277 struct ncr53c9x_softc *sc; 278 { 279 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 280 281 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 282 return 0; 283 284 if (sc->sc_state == NCR_CONNECTED) 285 csc->sc_portbits |= CBSC_PB_LED; 286 else 287 csc->sc_portbits &= ~CBSC_PB_LED; 288 csc->sc_reg[0x802] = csc->sc_portbits; 289 290 if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0) 291 return 0; 292 #ifdef DEBUG 293 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) { 294 cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 295 cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 296 cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active; 297 cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127; 298 } 299 #endif 300 return 1; 301 } 302 303 void 304 cbsc_dma_reset(sc) 305 struct ncr53c9x_softc *sc; 306 { 307 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 308 309 csc->sc_active = 0; 310 } 311 312 int 313 cbsc_dma_intr(sc) 314 struct ncr53c9x_softc *sc; 315 { 316 register struct cbsc_softc *csc = (struct cbsc_softc *)sc; 317 register int cnt; 318 319 NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ", 320 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 321 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 322 if (csc->sc_active == 0) { 323 printf("cbsc_intr--inactive DMA\n"); 324 return -1; 325 } 326 327 /* update sc_dmaaddr and sc_pdmalen */ 328 cnt = csc->sc_reg[NCR_TCL * 4]; 329 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 330 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 331 if (!csc->sc_datain) { 332 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 333 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 334 } 335 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 336 NCR_DMA(("DMA xferred %d\n", cnt)); 337 if (csc->sc_xfr_align) { 338 bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt); 339 csc->sc_xfr_align = 0; 340 } 341 *csc->sc_dmaaddr += cnt; 342 *csc->sc_pdmalen -= cnt; 343 csc->sc_active = 0; 344 return 0; 345 } 346 347 int 348 cbsc_dma_setup(sc, addr, len, datain, dmasize) 349 struct ncr53c9x_softc *sc; 350 caddr_t *addr; 351 size_t *len; 352 int datain; 353 size_t *dmasize; 354 { 355 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 356 paddr_t pa; 357 u_char *ptr; 358 size_t xfer; 359 360 csc->sc_dmaaddr = addr; 361 csc->sc_pdmalen = len; 362 csc->sc_datain = datain; 363 csc->sc_dmasize = *dmasize; 364 /* 365 * DMA can be nasty for high-speed serial input, so limit the 366 * size of this DMA operation if the serial port is running at 367 * a high speed (higher than 19200 for now - should be adjusted 368 * based on cpu type and speed?). 369 * XXX - add serial speed check XXX 370 */ 371 if (ser_open_speed > 19200 && cbsc_max_dma != 0 && 372 csc->sc_dmasize > cbsc_max_dma) 373 csc->sc_dmasize = cbsc_max_dma; 374 ptr = *addr; /* Kernel virtual address */ 375 pa = kvtop(ptr); /* Physical address of DMA */ 376 xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 377 csc->sc_xfr_align = 0; 378 /* 379 * If output and unaligned, stuff odd byte into FIFO 380 */ 381 if (datain == 0 && (int)ptr & 1) { 382 NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n")); 383 pa++; 384 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 385 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 386 } 387 /* 388 * If unaligned address, read unaligned bytes into alignment buffer 389 */ 390 else if ((int)ptr & 1) { 391 pa = kvtop((caddr_t)&csc->sc_alignbuf); 392 xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf)); 393 NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer)); 394 csc->sc_xfr_align = 1; 395 } 396 ++cbsc_cnt_dma; /* number of DMA operations */ 397 398 while (xfer < csc->sc_dmasize) { 399 if ((pa + xfer) != kvtop(*addr + xfer)) 400 break; 401 if ((csc->sc_dmasize - xfer) < NBPG) 402 xfer = csc->sc_dmasize; 403 else 404 xfer += NBPG; 405 ++cbsc_cnt_dma3; 406 } 407 if (xfer != *len) 408 ++cbsc_cnt_dma2; 409 410 csc->sc_dmasize = xfer; 411 *dmasize = csc->sc_dmasize; 412 csc->sc_pa = pa; 413 #if defined(M68040) || defined(M68060) 414 if (mmutype == MMU_68040) { 415 if (csc->sc_xfr_align) { 416 dma_cachectl(csc->sc_alignbuf, 417 sizeof(csc->sc_alignbuf)); 418 } 419 else 420 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 421 } 422 #endif 423 424 if (csc->sc_datain) 425 pa &= ~1; 426 else 427 pa |= 1; 428 csc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 429 csc->sc_dmabase[2] = (u_int8_t)(pa >> 16); 430 csc->sc_dmabase[4] = (u_int8_t)(pa >> 8); 431 csc->sc_dmabase[6] = (u_int8_t)(pa); 432 if (csc->sc_datain) 433 csc->sc_portbits &= ~CBSC_PB_WRITE; 434 else 435 csc->sc_portbits |= CBSC_PB_WRITE; 436 csc->sc_reg[0x802] = csc->sc_portbits; 437 csc->sc_active = 1; 438 return 0; 439 } 440 441 void 442 cbsc_dma_go(sc) 443 struct ncr53c9x_softc *sc; 444 { 445 } 446 447 void 448 cbsc_dma_stop(sc) 449 struct ncr53c9x_softc *sc; 450 { 451 } 452 453 int 454 cbsc_dma_isactive(sc) 455 struct ncr53c9x_softc *sc; 456 { 457 struct cbsc_softc *csc = (struct cbsc_softc *)sc; 458 459 return csc->sc_active; 460 } 461 462 #ifdef DEBUG 463 void 464 cbsc_dump() 465 { 466 int i; 467 468 i = cbsc_trace_ptr; 469 printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr); 470 do { 471 if (cbsc_trace[i].hardbits == 0) { 472 i = (i + 1) & 127; 473 continue; 474 } 475 printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits, 476 cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy); 477 if (cbsc_trace[i].status & NCRSTAT_INT) 478 printf("NCRINT/"); 479 if (cbsc_trace[i].status & NCRSTAT_TC) 480 printf("NCRTC/"); 481 switch(cbsc_trace[i].status & NCRSTAT_PHASE) { 482 case 0: 483 printf("dataout"); break; 484 case 1: 485 printf("datain"); break; 486 case 2: 487 printf("cmdout"); break; 488 case 3: 489 printf("status"); break; 490 case 6: 491 printf("msgout"); break; 492 case 7: 493 printf("msgin"); break; 494 default: 495 printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE); 496 } 497 printf(") "); 498 i = (i + 1) & 127; 499 } while (i != cbsc_trace_ptr); 500 printf("\n"); 501 } 502 #endif 503