1 /* $NetBSD: cbiisc.c,v 1.27 2008/04/13 04:55:52 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cbiisc.c,v 1.27 2008/04/13 04:55:52 tsutsui Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/cpu.h> 61 #include <machine/param.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <amiga/amiga/isr.h> 67 #include <amiga/dev/cbiiscvar.h> 68 #include <amiga/dev/zbusvar.h> 69 70 #ifdef __powerpc__ 71 #define badaddr(a) badaddr_read(a, 2, NULL) 72 #endif 73 74 int cbiiscmatch(device_t, cfdata_t, void *); 75 void cbiiscattach(device_t, device_t, void *); 76 77 /* Linkup to the rest of the kernel */ 78 CFATTACH_DECL_NEW(cbiisc, sizeof(struct cbiisc_softc), 79 cbiiscmatch, cbiiscattach, NULL, NULL); 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 uint8_t cbiisc_read_reg(struct ncr53c9x_softc *, int); 85 void cbiisc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 86 int cbiisc_dma_isintr(struct ncr53c9x_softc *); 87 void cbiisc_dma_reset(struct ncr53c9x_softc *); 88 int cbiisc_dma_intr(struct ncr53c9x_softc *); 89 int cbiisc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 90 size_t *, int, size_t *); 91 void cbiisc_dma_go(struct ncr53c9x_softc *); 92 void cbiisc_dma_stop(struct ncr53c9x_softc *); 93 int cbiisc_dma_isactive(struct ncr53c9x_softc *); 94 95 struct ncr53c9x_glue cbiisc_glue = { 96 cbiisc_read_reg, 97 cbiisc_write_reg, 98 cbiisc_dma_isintr, 99 cbiisc_dma_reset, 100 cbiisc_dma_intr, 101 cbiisc_dma_setup, 102 cbiisc_dma_go, 103 cbiisc_dma_stop, 104 cbiisc_dma_isactive, 105 NULL, 106 }; 107 108 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 109 u_long cbiisc_max_dma = 1024; 110 extern int ser_open_speed; 111 112 u_long cbiisc_cnt_pio = 0; /* number of PIO transfers */ 113 u_long cbiisc_cnt_dma = 0; /* number of DMA transfers */ 114 u_long cbiisc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 115 u_long cbiisc_cnt_dma3 = 0; /* number of pages combined */ 116 117 #ifdef DEBUG 118 struct { 119 uint8_t hardbits; 120 uint8_t status; 121 uint8_t xx; 122 uint8_t yy; 123 } cbiisc_trace[128]; 124 int cbiisc_trace_ptr = 0; 125 int cbiisc_trace_enable = 1; 126 void cbiisc_dump(void); 127 #endif 128 129 /* 130 * if we are a Phase5 CyberSCSI II 131 */ 132 int 133 cbiiscmatch(device_t parent, cfdata_t cf, void *aux) 134 { 135 struct zbus_args *zap; 136 volatile uint8_t *regs; 137 138 zap = aux; 139 if (zap->manid != 0x2140 || zap->prodid != 25) 140 return 0; 141 regs = &((volatile uint8_t *)zap->va)[0x1ff03]; 142 if (badaddr((void *)__UNVOLATILE(regs))) 143 return 0; 144 regs[NCR_CFG1 * 4] = 0; 145 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 146 delay(5); 147 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 148 return 0; 149 return 1; 150 } 151 152 /* 153 * Attach this instance, and then all the sub-devices 154 */ 155 void 156 cbiiscattach(device_t parent, device_t self, void *aux) 157 { 158 struct cbiisc_softc *csc = device_private(self); 159 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 160 struct zbus_args *zap; 161 extern u_long scsi_nosync; 162 extern int shift_nosync; 163 extern int ncr53c9x_debug; 164 165 /* 166 * Set up the glue for MI code early; we use some of it here. 167 */ 168 sc->sc_dev = self; 169 sc->sc_glue = &cbiisc_glue; 170 171 /* 172 * Save the regs 173 */ 174 zap = aux; 175 csc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff03]; 176 csc->sc_dmabase = &csc->sc_reg[0x80]; 177 178 sc->sc_freq = 40; /* Clocked at 40 MHz */ 179 180 aprint_normal(": address %p", csc->sc_reg); 181 182 sc->sc_id = 7; 183 184 /* 185 * It is necessary to try to load the 2nd config register here, 186 * to find out what rev the FAS chip is, else the ncr53c9x_reset 187 * will not set up the defaults correctly. 188 */ 189 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 190 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 191 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 192 sc->sc_rev = NCR_VARIANT_FAS216; 193 194 /* 195 * This is the value used to start sync negotiations 196 * Note that the NCR register "SYNCTP" is programmed 197 * in "clocks per byte", and has a minimum value of 4. 198 * The SCSI period used in negotiation is one-fourth 199 * of the time (in nanoseconds) needed to transfer one byte. 200 * Since the chip's clock is given in MHz, we have the following 201 * formula: 4 * period = (1000 / freq) * 4 202 */ 203 sc->sc_minsync = 1000 / sc->sc_freq; 204 205 /* 206 * get flags from -I argument and set cf_flags. 207 * NOTE: low 8 bits are to disable disconnect, and the next 208 * 8 bits are to disable sync. 209 */ 210 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 211 & 0xffff; 212 shift_nosync += 16; 213 214 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 215 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 216 shift_nosync += 16; 217 218 #if 1 219 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 220 sc->sc_minsync = 0; 221 #endif 222 223 /* Really no limit, but since we want to fit into the TCR... */ 224 sc->sc_maxxfer = 64 * 1024; 225 226 /* 227 * Configure interrupts. 228 */ 229 csc->sc_isr.isr_intr = ncr53c9x_intr; 230 csc->sc_isr.isr_arg = sc; 231 csc->sc_isr.isr_ipl = 2; 232 add_isr(&csc->sc_isr); 233 234 /* 235 * Now try to attach all the sub-devices 236 */ 237 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 238 sc->sc_adapter.adapt_minphys = minphys; 239 ncr53c9x_attach(sc); 240 } 241 242 /* 243 * Glue functions. 244 */ 245 246 uint8_t 247 cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg) 248 { 249 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 250 251 return csc->sc_reg[reg * 4]; 252 } 253 254 void 255 cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 256 { 257 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 258 uint8_t v = val; 259 260 csc->sc_reg[reg * 4] = v; 261 #ifdef DEBUG 262 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 263 reg == NCR_CMD/* && csc->sc_active*/) { 264 cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v; 265 /* printf(" cmd %x", v);*/ 266 } 267 #endif 268 } 269 270 int 271 cbiisc_dma_isintr(struct ncr53c9x_softc *sc) 272 { 273 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 274 275 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 276 return 0; 277 278 if (sc->sc_state == NCR_CONNECTED) 279 csc->sc_reg[0x40] = CBIISC_PB_LED; 280 else 281 csc->sc_reg[0x40] = 0; 282 283 #ifdef DEBUG 284 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) { 285 cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 286 cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 287 cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active; 288 cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127; 289 } 290 #endif 291 return 1; 292 } 293 294 void 295 cbiisc_dma_reset(struct ncr53c9x_softc *sc) 296 { 297 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 298 299 csc->sc_active = 0; 300 } 301 302 int 303 cbiisc_dma_intr(struct ncr53c9x_softc *sc) 304 { 305 register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 306 register int cnt; 307 308 NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ", 309 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 310 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 311 if (csc->sc_active == 0) { 312 printf("cbiisc_intr--inactive DMA\n"); 313 return -1; 314 } 315 316 /* update sc_dmaaddr and sc_pdmalen */ 317 cnt = csc->sc_reg[NCR_TCL * 4]; 318 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 319 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 320 if (!csc->sc_datain) { 321 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 322 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 323 } 324 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 325 NCR_DMA(("DMA xferred %d\n", cnt)); 326 if (csc->sc_xfr_align) { 327 memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt); 328 csc->sc_xfr_align = 0; 329 } 330 *csc->sc_dmaaddr += cnt; 331 *csc->sc_pdmalen -= cnt; 332 csc->sc_active = 0; 333 return 0; 334 } 335 336 int 337 cbiisc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 338 int datain, size_t *dmasize) 339 { 340 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 341 paddr_t pa; 342 uint8_t *ptr; 343 size_t xfer; 344 345 csc->sc_dmaaddr = addr; 346 csc->sc_pdmalen = len; 347 csc->sc_datain = datain; 348 csc->sc_dmasize = *dmasize; 349 /* 350 * DMA can be nasty for high-speed serial input, so limit the 351 * size of this DMA operation if the serial port is running at 352 * a high speed (higher than 19200 for now - should be adjusted 353 * based on CPU type and speed?). 354 * XXX - add serial speed check XXX 355 */ 356 if (ser_open_speed > 19200 && cbiisc_max_dma != 0 && 357 csc->sc_dmasize > cbiisc_max_dma) 358 csc->sc_dmasize = cbiisc_max_dma; 359 ptr = *addr; /* Kernel virtual address */ 360 pa = kvtop(ptr); /* Physical address of DMA */ 361 xfer = min(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 362 csc->sc_xfr_align = 0; 363 /* 364 * If output and unaligned, stuff odd byte into FIFO 365 */ 366 if (datain == 0 && (int)ptr & 1) { 367 NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n")); 368 pa++; 369 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 370 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 371 } 372 /* 373 * If unaligned address, read unaligned bytes into alignment buffer 374 */ 375 else if ((int)ptr & 1) { 376 pa = kvtop((void *)&csc->sc_alignbuf); 377 xfer = csc->sc_dmasize = min(xfer, sizeof(csc->sc_alignbuf)); 378 NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer)); 379 csc->sc_xfr_align = 1; 380 } 381 ++cbiisc_cnt_dma; /* number of DMA operations */ 382 383 while (xfer < csc->sc_dmasize) { 384 if ((pa + xfer) != kvtop(*addr + xfer)) 385 break; 386 if ((csc->sc_dmasize - xfer) < PAGE_SIZE) 387 xfer = csc->sc_dmasize; 388 else 389 xfer += PAGE_SIZE; 390 ++cbiisc_cnt_dma3; 391 } 392 if (xfer != *len) 393 ++cbiisc_cnt_dma2; 394 395 csc->sc_dmasize = xfer; 396 *dmasize = csc->sc_dmasize; 397 csc->sc_pa = pa; 398 #if defined(M68040) || defined(M68060) 399 if (mmutype == MMU_68040) { 400 if (csc->sc_xfr_align) { 401 dma_cachectl(csc->sc_alignbuf, 402 sizeof(csc->sc_alignbuf)); 403 } 404 else 405 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 406 } 407 #endif 408 409 if (csc->sc_datain) 410 pa &= ~1; 411 else 412 pa |= 1; 413 csc->sc_dmabase[0] = (uint8_t)(pa >> 24); 414 csc->sc_dmabase[4] = (uint8_t)(pa >> 16); 415 csc->sc_dmabase[8] = (uint8_t)(pa >> 8); 416 csc->sc_dmabase[12] = (uint8_t)(pa); 417 csc->sc_active = 1; 418 return 0; 419 } 420 421 void 422 cbiisc_dma_go(struct ncr53c9x_softc *sc) 423 { 424 } 425 426 void 427 cbiisc_dma_stop(struct ncr53c9x_softc *sc) 428 { 429 } 430 431 int 432 cbiisc_dma_isactive(struct ncr53c9x_softc *sc) 433 { 434 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 435 436 return csc->sc_active; 437 } 438 439 #ifdef DEBUG 440 void 441 cbiisc_dump(void) 442 { 443 int i; 444 445 i = cbiisc_trace_ptr; 446 printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr); 447 do { 448 if (cbiisc_trace[i].hardbits == 0) { 449 i = (i + 1) & 127; 450 continue; 451 } 452 printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits, 453 cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy); 454 if (cbiisc_trace[i].status & NCRSTAT_INT) 455 printf("NCRINT/"); 456 if (cbiisc_trace[i].status & NCRSTAT_TC) 457 printf("NCRTC/"); 458 switch(cbiisc_trace[i].status & NCRSTAT_PHASE) { 459 case 0: 460 printf("dataout"); break; 461 case 1: 462 printf("datain"); break; 463 case 2: 464 printf("cmdout"); break; 465 case 3: 466 printf("status"); break; 467 case 6: 468 printf("msgout"); break; 469 case 7: 470 printf("msgin"); break; 471 default: 472 printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE); 473 } 474 printf(") "); 475 i = (i + 1) & 127; 476 } while (i != cbiisc_trace_ptr); 477 printf("\n"); 478 } 479 #endif 480