xref: /netbsd-src/sys/arch/amiga/dev/cbiisc.c (revision 3b01aba77a7a698587faaae455bbfe740923c1f5) 
1 /*	$NetBSD: cbiisc.c,v 1.11 2001/04/25 17:53:06 bouyer Exp $	*/
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/errno.h>
43 #include <sys/ioctl.h>
44 #include <sys/device.h>
45 #include <sys/buf.h>
46 #include <sys/proc.h>
47 #include <sys/user.h>
48 #include <sys/queue.h>
49 
50 #include <dev/scsipi/scsi_all.h>
51 #include <dev/scsipi/scsipi_all.h>
52 #include <dev/scsipi/scsiconf.h>
53 #include <dev/scsipi/scsi_message.h>
54 
55 #include <machine/cpu.h>
56 #include <machine/param.h>
57 
58 #include <dev/ic/ncr53c9xreg.h>
59 #include <dev/ic/ncr53c9xvar.h>
60 
61 #include <amiga/amiga/isr.h>
62 #include <amiga/dev/cbiiscvar.h>
63 #include <amiga/dev/zbusvar.h>
64 
65 void	cbiiscattach	__P((struct device *, struct device *, void *));
66 int	cbiiscmatch	__P((struct device *, struct cfdata *, void *));
67 
68 /* Linkup to the rest of the kernel */
69 struct cfattach cbiisc_ca = {
70 	sizeof(struct cbiisc_softc), cbiiscmatch, cbiiscattach
71 };
72 
73 /*
74  * Functions and the switch for the MI code.
75  */
76 u_char	cbiisc_read_reg __P((struct ncr53c9x_softc *, int));
77 void	cbiisc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
78 int	cbiisc_dma_isintr __P((struct ncr53c9x_softc *));
79 void	cbiisc_dma_reset __P((struct ncr53c9x_softc *));
80 int	cbiisc_dma_intr __P((struct ncr53c9x_softc *));
81 int	cbiisc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
82 	    size_t *, int, size_t *));
83 void	cbiisc_dma_go __P((struct ncr53c9x_softc *));
84 void	cbiisc_dma_stop __P((struct ncr53c9x_softc *));
85 int	cbiisc_dma_isactive __P((struct ncr53c9x_softc *));
86 
87 struct ncr53c9x_glue cbiisc_glue = {
88 	cbiisc_read_reg,
89 	cbiisc_write_reg,
90 	cbiisc_dma_isintr,
91 	cbiisc_dma_reset,
92 	cbiisc_dma_intr,
93 	cbiisc_dma_setup,
94 	cbiisc_dma_go,
95 	cbiisc_dma_stop,
96 	cbiisc_dma_isactive,
97 	0,
98 };
99 
100 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
101 u_long cbiisc_max_dma = 1024;
102 extern int ser_open_speed;
103 
104 u_long cbiisc_cnt_pio = 0;	/* number of PIO transfers */
105 u_long cbiisc_cnt_dma = 0;	/* number of DMA transfers */
106 u_long cbiisc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
107 u_long cbiisc_cnt_dma3 = 0;	/* number of pages combined */
108 
109 #ifdef DEBUG
110 struct {
111 	u_char hardbits;
112 	u_char status;
113 	u_char xx;
114 	u_char yy;
115 } cbiisc_trace[128];
116 int cbiisc_trace_ptr = 0;
117 int cbiisc_trace_enable = 1;
118 void cbiisc_dump __P((void));
119 #endif
120 
121 /*
122  * if we are a Phase5 CyberSCSI II
123  */
124 int
125 cbiiscmatch(parent, cf, aux)
126 	struct device *parent;
127 	struct cfdata *cf;
128 	void *aux;
129 {
130 	struct zbus_args *zap;
131 	volatile u_char *regs;
132 
133 	zap = aux;
134 	if (zap->manid != 0x2140 || zap->prodid != 25)
135 		return(0);
136 	regs = &((volatile u_char *)zap->va)[0x1ff03];
137 	if (badaddr((caddr_t)regs))
138 		return(0);
139 	regs[NCR_CFG1 * 4] = 0;
140 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
141 	delay(5);
142 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
143 		return(0);
144 	return(1);
145 }
146 
147 /*
148  * Attach this instance, and then all the sub-devices
149  */
150 void
151 cbiiscattach(parent, self, aux)
152 	struct device *parent, *self;
153 	void *aux;
154 {
155 	struct cbiisc_softc *csc = (void *)self;
156 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
157 	struct zbus_args  *zap;
158 	extern u_long scsi_nosync;
159 	extern int shift_nosync;
160 	extern int ncr53c9x_debug;
161 
162 	/*
163 	 * Set up the glue for MI code early; we use some of it here.
164 	 */
165 	sc->sc_glue = &cbiisc_glue;
166 
167 	/*
168 	 * Save the regs
169 	 */
170 	zap = aux;
171 	csc->sc_reg = &((volatile u_char *)zap->va)[0x1ff03];
172 	csc->sc_dmabase = &csc->sc_reg[0x80];
173 
174 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
175 
176 	printf(": address %p", csc->sc_reg);
177 
178 	sc->sc_id = 7;
179 
180 	/*
181 	 * It is necessary to try to load the 2nd config register here,
182 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
183 	 * will not set up the defaults correctly.
184 	 */
185 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
186 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
187 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
188 	sc->sc_rev = NCR_VARIANT_FAS216;
189 
190 	/*
191 	 * This is the value used to start sync negotiations
192 	 * Note that the NCR register "SYNCTP" is programmed
193 	 * in "clocks per byte", and has a minimum value of 4.
194 	 * The SCSI period used in negotiation is one-fourth
195 	 * of the time (in nanoseconds) needed to transfer one byte.
196 	 * Since the chip's clock is given in MHz, we have the following
197 	 * formula: 4 * period = (1000 / freq) * 4
198 	 */
199 	sc->sc_minsync = 1000 / sc->sc_freq;
200 
201 	/*
202 	 * get flags from -I argument and set cf_flags.
203 	 * NOTE: low 8 bits are to disable disconnect, and the next
204 	 *       8 bits are to disable sync.
205 	 */
206 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
207 	    & 0xffff;
208 	shift_nosync += 16;
209 
210 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
211 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
212 	shift_nosync += 16;
213 
214 #if 1
215 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
216 		sc->sc_minsync = 0;
217 #endif
218 
219 	/* Really no limit, but since we want to fit into the TCR... */
220 	sc->sc_maxxfer = 64 * 1024;
221 
222 	/*
223 	 * Configure interrupts.
224 	 */
225 	csc->sc_isr.isr_intr = ncr53c9x_intr;
226 	csc->sc_isr.isr_arg  = sc;
227 	csc->sc_isr.isr_ipl  = 2;
228 	add_isr(&csc->sc_isr);
229 
230 	/*
231 	 * Now try to attach all the sub-devices
232 	 */
233 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
234 	sc->sc_adapter.adapt_minphys = minphys;
235 	ncr53c9x_attach(sc);
236 }
237 
238 /*
239  * Glue functions.
240  */
241 
242 u_char
243 cbiisc_read_reg(sc, reg)
244 	struct ncr53c9x_softc *sc;
245 	int reg;
246 {
247 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
248 
249 	return csc->sc_reg[reg * 4];
250 }
251 
252 void
253 cbiisc_write_reg(sc, reg, val)
254 	struct ncr53c9x_softc *sc;
255 	int reg;
256 	u_char val;
257 {
258 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
259 	u_char v = val;
260 
261 	csc->sc_reg[reg * 4] = v;
262 #ifdef DEBUG
263 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
264   reg == NCR_CMD/* && csc->sc_active*/) {
265   cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
266 /*  printf(" cmd %x", v);*/
267 }
268 #endif
269 }
270 
271 int
272 cbiisc_dma_isintr(sc)
273 	struct ncr53c9x_softc *sc;
274 {
275 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
276 
277 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
278 		return 0;
279 
280 	if (sc->sc_state == NCR_CONNECTED)
281 		csc->sc_reg[0x40] = CBIISC_PB_LED;
282 	else
283 		csc->sc_reg[0x40] = 0;
284 
285 #ifdef DEBUG
286 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) {
287   cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
288   cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
289   cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
290   cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
291 }
292 #endif
293 	return 1;
294 }
295 
296 void
297 cbiisc_dma_reset(sc)
298 	struct ncr53c9x_softc *sc;
299 {
300 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
301 
302 	csc->sc_active = 0;
303 }
304 
305 int
306 cbiisc_dma_intr(sc)
307 	struct ncr53c9x_softc *sc;
308 {
309 	register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
310 	register int	cnt;
311 
312 	NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
313 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
314 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
315 	if (csc->sc_active == 0) {
316 		printf("cbiisc_intr--inactive DMA\n");
317 		return -1;
318 	}
319 
320 	/* update sc_dmaaddr and sc_pdmalen */
321 	cnt = csc->sc_reg[NCR_TCL * 4];
322 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
323 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
324 	if (!csc->sc_datain) {
325 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
326 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
327 	}
328 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
329 	NCR_DMA(("DMA xferred %d\n", cnt));
330 	if (csc->sc_xfr_align) {
331 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
332 		csc->sc_xfr_align = 0;
333 	}
334 	*csc->sc_dmaaddr += cnt;
335 	*csc->sc_pdmalen -= cnt;
336 	csc->sc_active = 0;
337 	return 0;
338 }
339 
340 int
341 cbiisc_dma_setup(sc, addr, len, datain, dmasize)
342 	struct ncr53c9x_softc *sc;
343 	caddr_t *addr;
344 	size_t *len;
345 	int datain;
346 	size_t *dmasize;
347 {
348 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
349 	paddr_t pa;
350 	u_char *ptr;
351 	size_t xfer;
352 
353 	csc->sc_dmaaddr = addr;
354 	csc->sc_pdmalen = len;
355 	csc->sc_datain = datain;
356 	csc->sc_dmasize = *dmasize;
357 	/*
358 	 * DMA can be nasty for high-speed serial input, so limit the
359 	 * size of this DMA operation if the serial port is running at
360 	 * a high speed (higher than 19200 for now - should be adjusted
361 	 * based on cpu type and speed?).
362 	 * XXX - add serial speed check XXX
363 	 */
364 	if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
365 	    csc->sc_dmasize > cbiisc_max_dma)
366 		csc->sc_dmasize = cbiisc_max_dma;
367 	ptr = *addr;			/* Kernel virtual address */
368 	pa = kvtop(ptr);		/* Physical address of DMA */
369 	xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
370 	csc->sc_xfr_align = 0;
371 	/*
372 	 * If output and unaligned, stuff odd byte into FIFO
373 	 */
374 	if (datain == 0 && (int)ptr & 1) {
375 		NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
376 		pa++;
377 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
378 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
379 	}
380 	/*
381 	 * If unaligned address, read unaligned bytes into alignment buffer
382 	 */
383 	else if ((int)ptr & 1) {
384 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
385 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
386 		NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
387 		csc->sc_xfr_align = 1;
388 	}
389 ++cbiisc_cnt_dma;		/* number of DMA operations */
390 
391 	while (xfer < csc->sc_dmasize) {
392 		if ((pa + xfer) != kvtop(*addr + xfer))
393 			break;
394 		if ((csc->sc_dmasize - xfer) < NBPG)
395 			xfer = csc->sc_dmasize;
396 		else
397 			xfer += NBPG;
398 ++cbiisc_cnt_dma3;
399 	}
400 if (xfer != *len)
401   ++cbiisc_cnt_dma2;
402 
403 	csc->sc_dmasize = xfer;
404 	*dmasize = csc->sc_dmasize;
405 	csc->sc_pa = pa;
406 #if defined(M68040) || defined(M68060)
407 	if (mmutype == MMU_68040) {
408 		if (csc->sc_xfr_align) {
409 			dma_cachectl(csc->sc_alignbuf,
410 			    sizeof(csc->sc_alignbuf));
411 		}
412 		else
413 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
414 	}
415 #endif
416 
417 	if (csc->sc_datain)
418 		pa &= ~1;
419 	else
420 		pa |= 1;
421 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
422 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
423 	csc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
424 	csc->sc_dmabase[12] = (u_int8_t)(pa);
425 	csc->sc_active = 1;
426 	return 0;
427 }
428 
429 void
430 cbiisc_dma_go(sc)
431 	struct ncr53c9x_softc *sc;
432 {
433 }
434 
435 void
436 cbiisc_dma_stop(sc)
437 	struct ncr53c9x_softc *sc;
438 {
439 }
440 
441 int
442 cbiisc_dma_isactive(sc)
443 	struct ncr53c9x_softc *sc;
444 {
445 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
446 
447 	return csc->sc_active;
448 }
449 
450 #ifdef DEBUG
451 void
452 cbiisc_dump()
453 {
454 	int i;
455 
456 	i = cbiisc_trace_ptr;
457 	printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
458 	do {
459 		if (cbiisc_trace[i].hardbits == 0) {
460 			i = (i + 1) & 127;
461 			continue;
462 		}
463 		printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
464 		    cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
465 		if (cbiisc_trace[i].status & NCRSTAT_INT)
466 			printf("NCRINT/");
467 		if (cbiisc_trace[i].status & NCRSTAT_TC)
468 			printf("NCRTC/");
469 		switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
470 		case 0:
471 			printf("dataout"); break;
472 		case 1:
473 			printf("datain"); break;
474 		case 2:
475 			printf("cmdout"); break;
476 		case 3:
477 			printf("status"); break;
478 		case 6:
479 			printf("msgout"); break;
480 		case 7:
481 			printf("msgin"); break;
482 		default:
483 			printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
484 		}
485 		printf(") ");
486 		i = (i + 1) & 127;
487 	} while (i != cbiisc_trace_ptr);
488 	printf("\n");
489 }
490 #endif
491