1 /* $NetBSD: cbiisc.c,v 1.15 2002/10/02 04:55:49 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: cbiisc.c,v 1.15 2002/10/02 04:55:49 thorpej Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <dev/scsipi/scsi_all.h> 54 #include <dev/scsipi/scsipi_all.h> 55 #include <dev/scsipi/scsiconf.h> 56 #include <dev/scsipi/scsi_message.h> 57 58 #include <machine/cpu.h> 59 #include <machine/param.h> 60 61 #include <dev/ic/ncr53c9xreg.h> 62 #include <dev/ic/ncr53c9xvar.h> 63 64 #include <amiga/amiga/isr.h> 65 #include <amiga/dev/cbiiscvar.h> 66 #include <amiga/dev/zbusvar.h> 67 68 void cbiiscattach(struct device *, struct device *, void *); 69 int cbiiscmatch(struct device *, struct cfdata *, void *); 70 71 /* Linkup to the rest of the kernel */ 72 CFATTACH_DECL(cbiisc, sizeof(struct cbiisc_softc), 73 cbiiscmatch, cbiiscattach, NULL, NULL); 74 75 /* 76 * Functions and the switch for the MI code. 77 */ 78 u_char cbiisc_read_reg(struct ncr53c9x_softc *, int); 79 void cbiisc_write_reg(struct ncr53c9x_softc *, int, u_char); 80 int cbiisc_dma_isintr(struct ncr53c9x_softc *); 81 void cbiisc_dma_reset(struct ncr53c9x_softc *); 82 int cbiisc_dma_intr(struct ncr53c9x_softc *); 83 int cbiisc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 84 size_t *, int, size_t *); 85 void cbiisc_dma_go(struct ncr53c9x_softc *); 86 void cbiisc_dma_stop(struct ncr53c9x_softc *); 87 int cbiisc_dma_isactive(struct ncr53c9x_softc *); 88 89 struct ncr53c9x_glue cbiisc_glue = { 90 cbiisc_read_reg, 91 cbiisc_write_reg, 92 cbiisc_dma_isintr, 93 cbiisc_dma_reset, 94 cbiisc_dma_intr, 95 cbiisc_dma_setup, 96 cbiisc_dma_go, 97 cbiisc_dma_stop, 98 cbiisc_dma_isactive, 99 0, 100 }; 101 102 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 103 u_long cbiisc_max_dma = 1024; 104 extern int ser_open_speed; 105 106 u_long cbiisc_cnt_pio = 0; /* number of PIO transfers */ 107 u_long cbiisc_cnt_dma = 0; /* number of DMA transfers */ 108 u_long cbiisc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 109 u_long cbiisc_cnt_dma3 = 0; /* number of pages combined */ 110 111 #ifdef DEBUG 112 struct { 113 u_char hardbits; 114 u_char status; 115 u_char xx; 116 u_char yy; 117 } cbiisc_trace[128]; 118 int cbiisc_trace_ptr = 0; 119 int cbiisc_trace_enable = 1; 120 void cbiisc_dump(void); 121 #endif 122 123 /* 124 * if we are a Phase5 CyberSCSI II 125 */ 126 int 127 cbiiscmatch(struct device *parent, struct cfdata *cf, void *aux) 128 { 129 struct zbus_args *zap; 130 volatile u_char *regs; 131 132 zap = aux; 133 if (zap->manid != 0x2140 || zap->prodid != 25) 134 return(0); 135 regs = &((volatile u_char *)zap->va)[0x1ff03]; 136 if (badaddr((caddr_t)regs)) 137 return(0); 138 regs[NCR_CFG1 * 4] = 0; 139 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 140 delay(5); 141 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 142 return(0); 143 return(1); 144 } 145 146 /* 147 * Attach this instance, and then all the sub-devices 148 */ 149 void 150 cbiiscattach(struct device *parent, struct device *self, void *aux) 151 { 152 struct cbiisc_softc *csc = (void *)self; 153 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x; 154 struct zbus_args *zap; 155 extern u_long scsi_nosync; 156 extern int shift_nosync; 157 extern int ncr53c9x_debug; 158 159 /* 160 * Set up the glue for MI code early; we use some of it here. 161 */ 162 sc->sc_glue = &cbiisc_glue; 163 164 /* 165 * Save the regs 166 */ 167 zap = aux; 168 csc->sc_reg = &((volatile u_char *)zap->va)[0x1ff03]; 169 csc->sc_dmabase = &csc->sc_reg[0x80]; 170 171 sc->sc_freq = 40; /* Clocked at 40Mhz */ 172 173 printf(": address %p", csc->sc_reg); 174 175 sc->sc_id = 7; 176 177 /* 178 * It is necessary to try to load the 2nd config register here, 179 * to find out what rev the FAS chip is, else the ncr53c9x_reset 180 * will not set up the defaults correctly. 181 */ 182 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 183 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 184 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 185 sc->sc_rev = NCR_VARIANT_FAS216; 186 187 /* 188 * This is the value used to start sync negotiations 189 * Note that the NCR register "SYNCTP" is programmed 190 * in "clocks per byte", and has a minimum value of 4. 191 * The SCSI period used in negotiation is one-fourth 192 * of the time (in nanoseconds) needed to transfer one byte. 193 * Since the chip's clock is given in MHz, we have the following 194 * formula: 4 * period = (1000 / freq) * 4 195 */ 196 sc->sc_minsync = 1000 / sc->sc_freq; 197 198 /* 199 * get flags from -I argument and set cf_flags. 200 * NOTE: low 8 bits are to disable disconnect, and the next 201 * 8 bits are to disable sync. 202 */ 203 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 204 & 0xffff; 205 shift_nosync += 16; 206 207 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 208 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 209 shift_nosync += 16; 210 211 #if 1 212 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 213 sc->sc_minsync = 0; 214 #endif 215 216 /* Really no limit, but since we want to fit into the TCR... */ 217 sc->sc_maxxfer = 64 * 1024; 218 219 /* 220 * Configure interrupts. 221 */ 222 csc->sc_isr.isr_intr = ncr53c9x_intr; 223 csc->sc_isr.isr_arg = sc; 224 csc->sc_isr.isr_ipl = 2; 225 add_isr(&csc->sc_isr); 226 227 /* 228 * Now try to attach all the sub-devices 229 */ 230 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 231 sc->sc_adapter.adapt_minphys = minphys; 232 ncr53c9x_attach(sc); 233 } 234 235 /* 236 * Glue functions. 237 */ 238 239 u_char 240 cbiisc_read_reg(struct ncr53c9x_softc *sc, int reg) 241 { 242 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 243 244 return csc->sc_reg[reg * 4]; 245 } 246 247 void 248 cbiisc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 249 { 250 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 251 u_char v = val; 252 253 csc->sc_reg[reg * 4] = v; 254 #ifdef DEBUG 255 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 256 reg == NCR_CMD/* && csc->sc_active*/) { 257 cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v; 258 /* printf(" cmd %x", v);*/ 259 } 260 #endif 261 } 262 263 int 264 cbiisc_dma_isintr(struct ncr53c9x_softc *sc) 265 { 266 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 267 268 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 269 return 0; 270 271 if (sc->sc_state == NCR_CONNECTED) 272 csc->sc_reg[0x40] = CBIISC_PB_LED; 273 else 274 csc->sc_reg[0x40] = 0; 275 276 #ifdef DEBUG 277 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbiisc_trace_enable) { 278 cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4]; 279 cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4]; 280 cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active; 281 cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127; 282 } 283 #endif 284 return 1; 285 } 286 287 void 288 cbiisc_dma_reset(struct ncr53c9x_softc *sc) 289 { 290 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 291 292 csc->sc_active = 0; 293 } 294 295 int 296 cbiisc_dma_intr(struct ncr53c9x_softc *sc) 297 { 298 register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 299 register int cnt; 300 301 NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ", 302 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 303 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 304 if (csc->sc_active == 0) { 305 printf("cbiisc_intr--inactive DMA\n"); 306 return -1; 307 } 308 309 /* update sc_dmaaddr and sc_pdmalen */ 310 cnt = csc->sc_reg[NCR_TCL * 4]; 311 cnt += csc->sc_reg[NCR_TCM * 4] << 8; 312 cnt += csc->sc_reg[NCR_TCH * 4] << 16; 313 if (!csc->sc_datain) { 314 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 315 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 316 } 317 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */ 318 NCR_DMA(("DMA xferred %d\n", cnt)); 319 if (csc->sc_xfr_align) { 320 bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt); 321 csc->sc_xfr_align = 0; 322 } 323 *csc->sc_dmaaddr += cnt; 324 *csc->sc_pdmalen -= cnt; 325 csc->sc_active = 0; 326 return 0; 327 } 328 329 int 330 cbiisc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 331 int datain, size_t *dmasize) 332 { 333 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 334 paddr_t pa; 335 u_char *ptr; 336 size_t xfer; 337 338 csc->sc_dmaaddr = addr; 339 csc->sc_pdmalen = len; 340 csc->sc_datain = datain; 341 csc->sc_dmasize = *dmasize; 342 /* 343 * DMA can be nasty for high-speed serial input, so limit the 344 * size of this DMA operation if the serial port is running at 345 * a high speed (higher than 19200 for now - should be adjusted 346 * based on cpu type and speed?). 347 * XXX - add serial speed check XXX 348 */ 349 if (ser_open_speed > 19200 && cbiisc_max_dma != 0 && 350 csc->sc_dmasize > cbiisc_max_dma) 351 csc->sc_dmasize = cbiisc_max_dma; 352 ptr = *addr; /* Kernel virtual address */ 353 pa = kvtop(ptr); /* Physical address of DMA */ 354 xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 355 csc->sc_xfr_align = 0; 356 /* 357 * If output and unaligned, stuff odd byte into FIFO 358 */ 359 if (datain == 0 && (int)ptr & 1) { 360 NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n")); 361 pa++; 362 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 363 csc->sc_reg[NCR_FIFO * 4] = *ptr++; 364 } 365 /* 366 * If unaligned address, read unaligned bytes into alignment buffer 367 */ 368 else if ((int)ptr & 1) { 369 pa = kvtop((caddr_t)&csc->sc_alignbuf); 370 xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf)); 371 NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer)); 372 csc->sc_xfr_align = 1; 373 } 374 ++cbiisc_cnt_dma; /* number of DMA operations */ 375 376 while (xfer < csc->sc_dmasize) { 377 if ((pa + xfer) != kvtop(*addr + xfer)) 378 break; 379 if ((csc->sc_dmasize - xfer) < NBPG) 380 xfer = csc->sc_dmasize; 381 else 382 xfer += NBPG; 383 ++cbiisc_cnt_dma3; 384 } 385 if (xfer != *len) 386 ++cbiisc_cnt_dma2; 387 388 csc->sc_dmasize = xfer; 389 *dmasize = csc->sc_dmasize; 390 csc->sc_pa = pa; 391 #if defined(M68040) || defined(M68060) 392 if (mmutype == MMU_68040) { 393 if (csc->sc_xfr_align) { 394 dma_cachectl(csc->sc_alignbuf, 395 sizeof(csc->sc_alignbuf)); 396 } 397 else 398 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize); 399 } 400 #endif 401 402 if (csc->sc_datain) 403 pa &= ~1; 404 else 405 pa |= 1; 406 csc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 407 csc->sc_dmabase[4] = (u_int8_t)(pa >> 16); 408 csc->sc_dmabase[8] = (u_int8_t)(pa >> 8); 409 csc->sc_dmabase[12] = (u_int8_t)(pa); 410 csc->sc_active = 1; 411 return 0; 412 } 413 414 void 415 cbiisc_dma_go(struct ncr53c9x_softc *sc) 416 { 417 } 418 419 void 420 cbiisc_dma_stop(struct ncr53c9x_softc *sc) 421 { 422 } 423 424 int 425 cbiisc_dma_isactive(struct ncr53c9x_softc *sc) 426 { 427 struct cbiisc_softc *csc = (struct cbiisc_softc *)sc; 428 429 return csc->sc_active; 430 } 431 432 #ifdef DEBUG 433 void 434 cbiisc_dump(void) 435 { 436 int i; 437 438 i = cbiisc_trace_ptr; 439 printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr); 440 do { 441 if (cbiisc_trace[i].hardbits == 0) { 442 i = (i + 1) & 127; 443 continue; 444 } 445 printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits, 446 cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy); 447 if (cbiisc_trace[i].status & NCRSTAT_INT) 448 printf("NCRINT/"); 449 if (cbiisc_trace[i].status & NCRSTAT_TC) 450 printf("NCRTC/"); 451 switch(cbiisc_trace[i].status & NCRSTAT_PHASE) { 452 case 0: 453 printf("dataout"); break; 454 case 1: 455 printf("datain"); break; 456 case 2: 457 printf("cmdout"); break; 458 case 3: 459 printf("status"); break; 460 case 6: 461 printf("msgout"); break; 462 case 7: 463 printf("msgin"); break; 464 default: 465 printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE); 466 } 467 printf(") "); 468 i = (i + 1) & 127; 469 } while (i != cbiisc_trace_ptr); 470 printf("\n"); 471 } 472 #endif 473