xref: /netbsd-src/sys/arch/amiga/dev/cbiisc.c (revision 2a399c6883d870daece976daec6ffa7bb7f934ce) 
1 /*	$NetBSD: cbiisc.c,v 1.2 1997/10/24 01:43:53 mhitch Exp $	*/
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1982, 1990 The Regents of the University of California.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product contains software written by Michael L. Hitch for
19  *	the NetBSD project.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  */
37 
38 #include <sys/types.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/kernel.h>
42 #include <sys/errno.h>
43 #include <sys/ioctl.h>
44 #include <sys/device.h>
45 #include <sys/buf.h>
46 #include <sys/proc.h>
47 #include <sys/user.h>
48 #include <sys/queue.h>
49 
50 #include <dev/scsipi/scsi_all.h>
51 #include <dev/scsipi/scsipi_all.h>
52 #include <dev/scsipi/scsiconf.h>
53 #include <dev/scsipi/scsi_message.h>
54 
55 #include <machine/cpu.h>
56 #include <machine/param.h>
57 
58 #include <dev/ic/ncr53c9xreg.h>
59 #include <dev/ic/ncr53c9xvar.h>
60 
61 #include <amiga/amiga/isr.h>
62 #include <amiga/dev/cbiiscvar.h>
63 #include <amiga/dev/zbusvar.h>
64 
65 void	cbiiscattach	__P((struct device *, struct device *, void *));
66 int	cbiiscmatch	__P((struct device *, struct cfdata *, void *));
67 
68 /* Linkup to the rest of the kernel */
69 struct cfattach cbiisc_ca = {
70 	sizeof(struct cbiisc_softc), cbiiscmatch, cbiiscattach
71 };
72 
73 struct cfdriver cbiisc_cd = {
74 	NULL, "cbiisc", DV_DULL
75 };
76 
77 struct scsipi_adapter cbiisc_switch = {
78 	ncr53c9x_scsi_cmd,
79 	minphys,		/* no max at this level; handled by DMA code */
80 	NULL,
81 	NULL,
82 };
83 
84 struct scsipi_device cbiisc_dev = {
85 	NULL,			/* Use default error handler */
86 	NULL,			/* have a queue, served by this */
87 	NULL,			/* have no async handler */
88 	NULL,			/* Use default 'done' routine */
89 };
90 
91 /*
92  * Functions and the switch for the MI code.
93  */
94 u_char	cbiisc_read_reg __P((struct ncr53c9x_softc *, int));
95 void	cbiisc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
96 int	cbiisc_dma_isintr __P((struct ncr53c9x_softc *));
97 void	cbiisc_dma_reset __P((struct ncr53c9x_softc *));
98 int	cbiisc_dma_intr __P((struct ncr53c9x_softc *));
99 int	cbiisc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
100 	    size_t *, int, size_t *));
101 void	cbiisc_dma_go __P((struct ncr53c9x_softc *));
102 void	cbiisc_dma_stop __P((struct ncr53c9x_softc *));
103 int	cbiisc_dma_isactive __P((struct ncr53c9x_softc *));
104 
105 struct ncr53c9x_glue cbiisc_glue = {
106 	cbiisc_read_reg,
107 	cbiisc_write_reg,
108 	cbiisc_dma_isintr,
109 	cbiisc_dma_reset,
110 	cbiisc_dma_intr,
111 	cbiisc_dma_setup,
112 	cbiisc_dma_go,
113 	cbiisc_dma_stop,
114 	cbiisc_dma_isactive,
115 	0,
116 };
117 
118 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
119 u_long cbiisc_max_dma = 1024;
120 extern int ser_open_speed;
121 
122 u_long cbiisc_cnt_pio = 0;	/* number of PIO transfers */
123 u_long cbiisc_cnt_dma = 0;	/* number of DMA transfers */
124 u_long cbiisc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
125 u_long cbiisc_cnt_dma3 = 0;	/* number of pages combined */
126 
127 #ifdef DEBUG
128 struct {
129 	u_char hardbits;
130 	u_char status;
131 	u_char xx;
132 	u_char yy;
133 } cbiisc_trace[128];
134 int cbiisc_trace_ptr = 0;
135 int cbiisc_trace_enable = 1;
136 void cbiisc_dump __P((void));
137 #endif
138 
139 /*
140  * if we are a Phase5 CyberSCSI II
141  */
142 int
143 cbiiscmatch(parent, cf, aux)
144 	struct device *parent;
145 	struct cfdata *cf;
146 	void *aux;
147 {
148 	struct zbus_args *zap;
149 	volatile u_char *regs;
150 
151 	zap = aux;
152 	if (zap->manid != 0x2140 || zap->prodid != 25)
153 		return(0);
154 	regs = &((volatile u_char *)zap->va)[0x1ff03];
155 	if (badaddr((caddr_t)regs))
156 		return(0);
157 	regs[NCR_CFG1 * 4] = 0;
158 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
159 	delay(5);
160 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
161 		return(0);
162 	return(1);
163 }
164 
165 /*
166  * Attach this instance, and then all the sub-devices
167  */
168 void
169 cbiiscattach(parent, self, aux)
170 	struct device *parent, *self;
171 	void *aux;
172 {
173 	struct cbiisc_softc *csc = (void *)self;
174 	struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
175 	struct zbus_args  *zap;
176 	extern u_long scsi_nosync;
177 	extern int shift_nosync;
178 	extern int ncr53c9x_debug;
179 
180 	/*
181 	 * Set up the glue for MI code early; we use some of it here.
182 	 */
183 	sc->sc_glue = &cbiisc_glue;
184 
185 	/*
186 	 * Save the regs
187 	 */
188 	zap = aux;
189 	csc->sc_reg = &((volatile u_char *)zap->va)[0x1ff03];
190 	csc->sc_dmabase = &csc->sc_reg[0x80];
191 
192 	sc->sc_freq = 40;		/* Clocked at 40Mhz */
193 
194 	printf(": address %p", csc->sc_reg);
195 
196 	sc->sc_id = 7;
197 
198 	/*
199 	 * It is necessary to try to load the 2nd config register here,
200 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
201 	 * will not set up the defaults correctly.
202 	 */
203 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
204 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
205 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
206 	sc->sc_rev = NCR_VARIANT_FAS216;
207 
208 	/*
209 	 * This is the value used to start sync negotiations
210 	 * Note that the NCR register "SYNCTP" is programmed
211 	 * in "clocks per byte", and has a minimum value of 4.
212 	 * The SCSI period used in negotiation is one-fourth
213 	 * of the time (in nanoseconds) needed to transfer one byte.
214 	 * Since the chip's clock is given in MHz, we have the following
215 	 * formula: 4 * period = (1000 / freq) * 4
216 	 */
217 	sc->sc_minsync = 1000 / sc->sc_freq;
218 
219 	/*
220 	 * get flags from -I argument and set cf_flags.
221 	 * NOTE: low 8 bits are to disable disconnect, and the next
222 	 *       8 bits are to disable sync.
223 	 */
224 	sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync)
225 	    & 0xffff;
226 	shift_nosync += 16;
227 
228 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
229 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
230 	shift_nosync += 16;
231 
232 #if 1
233 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
234 		sc->sc_minsync = 0;
235 #endif
236 
237 	/* Really no limit, but since we want to fit into the TCR... */
238 	sc->sc_maxxfer = 64 * 1024;
239 
240 	/*
241 	 * Configure interrupts.
242 	 */
243 	csc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr;
244 	csc->sc_isr.isr_arg  = sc;
245 	csc->sc_isr.isr_ipl  = 2;
246 	add_isr(&csc->sc_isr);
247 
248 	/*
249 	 * Now try to attach all the sub-devices
250 	 */
251 	ncr53c9x_attach(sc, &cbiisc_switch, &cbiisc_dev);
252 }
253 
254 /*
255  * Glue functions.
256  */
257 
258 u_char
259 cbiisc_read_reg(sc, reg)
260 	struct ncr53c9x_softc *sc;
261 	int reg;
262 {
263 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
264 
265 	return csc->sc_reg[reg * 4];
266 }
267 
268 void
269 cbiisc_write_reg(sc, reg, val)
270 	struct ncr53c9x_softc *sc;
271 	int reg;
272 	u_char val;
273 {
274 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
275 	u_char v = val;
276 
277 	csc->sc_reg[reg * 4] = v;
278 #ifdef DEBUG
279 if (cbiisc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ &&
280   reg == NCR_CMD/* && csc->sc_active*/) {
281   cbiisc_trace[(cbiisc_trace_ptr - 1) & 127].yy = v;
282 /*  printf(" cmd %x", v);*/
283 }
284 #endif
285 }
286 
287 int
288 cbiisc_dma_isintr(sc)
289 	struct ncr53c9x_softc *sc;
290 {
291 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
292 
293 	if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
294 		return 0;
295 
296 	if (sc->sc_state == NCR_CONNECTED)
297 		csc->sc_reg[0x40] = CBIISC_PB_LED;
298 	else
299 		csc->sc_reg[0x40] = 0;
300 
301 #ifdef DEBUG
302 if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ cbiisc_trace_enable) {
303   cbiisc_trace[cbiisc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
304   cbiisc_trace[cbiisc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
305   cbiisc_trace[cbiisc_trace_ptr].yy = csc->sc_active;
306   cbiisc_trace_ptr = (cbiisc_trace_ptr + 1) & 127;
307 }
308 #endif
309 	return 1;
310 }
311 
312 void
313 cbiisc_dma_reset(sc)
314 	struct ncr53c9x_softc *sc;
315 {
316 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
317 
318 	csc->sc_active = 0;
319 }
320 
321 int
322 cbiisc_dma_intr(sc)
323 	struct ncr53c9x_softc *sc;
324 {
325 	register struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
326 	register int	cnt;
327 
328 	NCR_DMA(("cbiisc_dma_intr: cnt %d int %x stat %x fifo %d ",
329 	    csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
330 	    csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
331 	if (csc->sc_active == 0) {
332 		printf("cbiisc_intr--inactive DMA\n");
333 		return -1;
334 	}
335 
336 	/* update sc_dmaaddr and sc_pdmalen */
337 	cnt = csc->sc_reg[NCR_TCL * 4];
338 	cnt += csc->sc_reg[NCR_TCM * 4] << 8;
339 	cnt += csc->sc_reg[NCR_TCH * 4] << 16;
340 	if (!csc->sc_datain) {
341 		cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
342 		csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
343 	}
344 	cnt = csc->sc_dmasize - cnt;	/* number of bytes transferred */
345 	NCR_DMA(("DMA xferred %d\n", cnt));
346 	if (csc->sc_xfr_align) {
347 		bcopy(csc->sc_alignbuf, *csc->sc_dmaaddr, cnt);
348 		csc->sc_xfr_align = 0;
349 	}
350 	*csc->sc_dmaaddr += cnt;
351 	*csc->sc_pdmalen -= cnt;
352 	csc->sc_active = 0;
353 	return 0;
354 }
355 
356 int
357 cbiisc_dma_setup(sc, addr, len, datain, dmasize)
358 	struct ncr53c9x_softc *sc;
359 	caddr_t *addr;
360 	size_t *len;
361 	int datain;
362 	size_t *dmasize;
363 {
364 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
365 	vm_offset_t pa;
366 	u_char *ptr;
367 	size_t xfer;
368 
369 	csc->sc_dmaaddr = addr;
370 	csc->sc_pdmalen = len;
371 	csc->sc_datain = datain;
372 	csc->sc_dmasize = *dmasize;
373 	/*
374 	 * DMA can be nasty for high-speed serial input, so limit the
375 	 * size of this DMA operation if the serial port is running at
376 	 * a high speed (higher than 19200 for now - should be adjusted
377 	 * based on cpu type and speed?).
378 	 * XXX - add serial speed check XXX
379 	 */
380 	if (ser_open_speed > 19200 && cbiisc_max_dma != 0 &&
381 	    csc->sc_dmasize > cbiisc_max_dma)
382 		csc->sc_dmasize = cbiisc_max_dma;
383 	ptr = *addr;			/* Kernel virtual address */
384 	pa = kvtop(ptr);		/* Physical address of DMA */
385 	xfer = min(csc->sc_dmasize, NBPG - (pa & (NBPG - 1)));
386 	csc->sc_xfr_align = 0;
387 	/*
388 	 * If output and unaligned, stuff odd byte into FIFO
389 	 */
390 	if (datain == 0 && (int)ptr & 1) {
391 		NCR_DMA(("cbiisc_dma_setup: align byte written to fifo\n"));
392 		pa++;
393 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
394 		csc->sc_reg[NCR_FIFO * 4] = *ptr++;
395 	}
396 	/*
397 	 * If unaligned address, read unaligned bytes into alignment buffer
398 	 */
399 	else if ((int)ptr & 1) {
400 		pa = kvtop((caddr_t)&csc->sc_alignbuf);
401 		xfer = csc->sc_dmasize = min(xfer, sizeof (csc->sc_alignbuf));
402 		NCR_DMA(("cbiisc_dma_setup: align read by %d bytes\n", xfer));
403 		csc->sc_xfr_align = 1;
404 	}
405 ++cbiisc_cnt_dma;		/* number of DMA operations */
406 
407 	while (xfer < csc->sc_dmasize) {
408 		if ((pa + xfer) != kvtop(*addr + xfer))
409 			break;
410 		if ((csc->sc_dmasize - xfer) < NBPG)
411 			xfer = csc->sc_dmasize;
412 		else
413 			xfer += NBPG;
414 ++cbiisc_cnt_dma3;
415 	}
416 if (xfer != *len)
417   ++cbiisc_cnt_dma2;
418 
419 	csc->sc_dmasize = xfer;
420 	*dmasize = csc->sc_dmasize;
421 	csc->sc_pa = pa;
422 #if defined(M68040) || defined(M68060)
423 	if (mmutype == MMU_68040) {
424 		if (csc->sc_xfr_align) {
425 			dma_cachectl(csc->sc_alignbuf,
426 			    sizeof(csc->sc_alignbuf));
427 		}
428 		else
429 			dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
430 	}
431 #endif
432 
433 	if (csc->sc_datain)
434 		pa &= ~1;
435 	else
436 		pa |= 1;
437 	csc->sc_dmabase[0] = (u_int8_t)(pa >> 24);
438 	csc->sc_dmabase[4] = (u_int8_t)(pa >> 16);
439 	csc->sc_dmabase[8] = (u_int8_t)(pa >> 8);
440 	csc->sc_dmabase[12] = (u_int8_t)(pa);
441 	csc->sc_active = 1;
442 	return 0;
443 }
444 
445 void
446 cbiisc_dma_go(sc)
447 	struct ncr53c9x_softc *sc;
448 {
449 }
450 
451 void
452 cbiisc_dma_stop(sc)
453 	struct ncr53c9x_softc *sc;
454 {
455 }
456 
457 int
458 cbiisc_dma_isactive(sc)
459 	struct ncr53c9x_softc *sc;
460 {
461 	struct cbiisc_softc *csc = (struct cbiisc_softc *)sc;
462 
463 	return csc->sc_active;
464 }
465 
466 #ifdef DEBUG
467 void
468 cbiisc_dump()
469 {
470 	int i;
471 
472 	i = cbiisc_trace_ptr;
473 	printf("cbiisc_trace dump: ptr %x\n", cbiisc_trace_ptr);
474 	do {
475 		if (cbiisc_trace[i].hardbits == 0) {
476 			i = (i + 1) & 127;
477 			continue;
478 		}
479 		printf("%02x%02x%02x%02x(", cbiisc_trace[i].hardbits,
480 		    cbiisc_trace[i].status, cbiisc_trace[i].xx, cbiisc_trace[i].yy);
481 		if (cbiisc_trace[i].status & NCRSTAT_INT)
482 			printf("NCRINT/");
483 		if (cbiisc_trace[i].status & NCRSTAT_TC)
484 			printf("NCRTC/");
485 		switch(cbiisc_trace[i].status & NCRSTAT_PHASE) {
486 		case 0:
487 			printf("dataout"); break;
488 		case 1:
489 			printf("datain"); break;
490 		case 2:
491 			printf("cmdout"); break;
492 		case 3:
493 			printf("status"); break;
494 		case 6:
495 			printf("msgout"); break;
496 		case 7:
497 			printf("msgin"); break;
498 		default:
499 			printf("phase%d?", cbiisc_trace[i].status & NCRSTAT_PHASE);
500 		}
501 		printf(") ");
502 		i = (i + 1) & 127;
503 	} while (i != cbiisc_trace_ptr);
504 	printf("\n");
505 }
506 #endif
507