1 /* $NetBSD: bztzsc.c,v 1.36 2010/12/20 00:25:25 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1996 Ignatios Souvatzis 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to 37 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 38 */ 39 40 #ifdef __m68k__ 41 #include "opt_m68k_arch.h" 42 #endif 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: bztzsc.c,v 1.36 2010/12/20 00:25:25 matt Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/queue.h> 57 58 #include <dev/scsipi/scsi_all.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 #include <dev/scsipi/scsi_message.h> 62 63 #include <machine/cpu.h> 64 #include <machine/param.h> 65 66 #include <dev/ic/ncr53c9xreg.h> 67 #include <dev/ic/ncr53c9xvar.h> 68 69 #include <amiga/amiga/isr.h> 70 #include <amiga/dev/bztzscvar.h> 71 #include <amiga/dev/zbusvar.h> 72 73 #ifdef __powerpc__ 74 #define badaddr(a) badaddr_read(a, 2, NULL) 75 #endif 76 77 int bztzscmatch(device_t, cfdata_t, void *); 78 void bztzscattach(device_t, device_t, void *); 79 80 /* Linkup to the rest of the kernel */ 81 CFATTACH_DECL_NEW(bztzsc, sizeof(struct bztzsc_softc), 82 bztzscmatch, bztzscattach, NULL, NULL); 83 84 /* 85 * Functions and the switch for the MI code. 86 */ 87 uint8_t bztzsc_read_reg(struct ncr53c9x_softc *, int); 88 void bztzsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 89 int bztzsc_dma_isintr(struct ncr53c9x_softc *); 90 void bztzsc_dma_reset(struct ncr53c9x_softc *); 91 int bztzsc_dma_intr(struct ncr53c9x_softc *); 92 int bztzsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 93 size_t *, int, size_t *); 94 void bztzsc_dma_go(struct ncr53c9x_softc *); 95 void bztzsc_dma_stop(struct ncr53c9x_softc *); 96 int bztzsc_dma_isactive(struct ncr53c9x_softc *); 97 98 struct ncr53c9x_glue bztzsc_glue = { 99 bztzsc_read_reg, 100 bztzsc_write_reg, 101 bztzsc_dma_isintr, 102 bztzsc_dma_reset, 103 bztzsc_dma_intr, 104 bztzsc_dma_setup, 105 bztzsc_dma_go, 106 bztzsc_dma_stop, 107 bztzsc_dma_isactive, 108 NULL, 109 }; 110 111 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 112 u_long bztzsc_max_dma = 1024; 113 extern int ser_open_speed; 114 115 u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */ 116 u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */ 117 u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 118 u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */ 119 120 #ifdef DEBUG 121 struct { 122 uint8_t hardbits; 123 uint8_t status; 124 uint8_t xx; 125 uint8_t yy; 126 } bztzsc_trace[128]; 127 int bztzsc_trace_ptr = 0; 128 int bztzsc_trace_enable = 1; 129 void bztzsc_dump(void); 130 #endif 131 132 /* 133 * if we are a Phase5 Blizzard 2060 SCSI 134 */ 135 int 136 bztzscmatch(device_t parent, cfdata_t cf, void *aux) 137 { 138 struct zbus_args *zap; 139 volatile uint8_t *regs; 140 141 zap = aux; 142 if (zap->manid != 0x2140 || zap->prodid != 24) 143 return 0; 144 regs = &((volatile uint8_t *)zap->va)[0x1ff00]; 145 if (badaddr((void *)__UNVOLATILE(regs))) 146 return 0; 147 regs[NCR_CFG1 * 4] = 0; 148 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 149 delay(5); 150 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 151 return 0; 152 return 1; 153 } 154 155 /* 156 * Attach this instance, and then all the sub-devices 157 */ 158 void 159 bztzscattach(device_t parent, device_t self, void *aux) 160 { 161 struct bztzsc_softc *bsc = device_private(self); 162 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 163 struct zbus_args *zap; 164 extern u_long scsi_nosync; 165 extern int shift_nosync; 166 extern int ncr53c9x_debug; 167 168 /* 169 * Set up the glue for MI code early; we use some of it here. 170 */ 171 sc->sc_dev = self; 172 sc->sc_glue = &bztzsc_glue; 173 174 /* 175 * Save the regs 176 */ 177 zap = aux; 178 bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff00]; 179 bsc->sc_dmabase = &bsc->sc_reg[0xf0]; 180 181 sc->sc_freq = 40; /* Clocked at 40 MHz */ 182 183 aprint_normal(": address %p", bsc->sc_reg); 184 185 sc->sc_id = 7; 186 187 /* 188 * It is necessary to try to load the 2nd config register here, 189 * to find out what rev the FAS chip is, else the ncr53c9x_reset 190 * will not set up the defaults correctly. 191 */ 192 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 193 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 194 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 195 sc->sc_rev = NCR_VARIANT_FAS216; 196 197 /* 198 * This is the value used to start sync negotiations 199 * Note that the NCR register "SYNCTP" is programmed 200 * in "clocks per byte", and has a minimum value of 4. 201 * The SCSI period used in negotiation is one-fourth 202 * of the time (in nanoseconds) needed to transfer one byte. 203 * Since the chip's clock is given in MHz, we have the following 204 * formula: 4 * period = (1000 / freq) * 4 205 */ 206 sc->sc_minsync = 1000 / sc->sc_freq; 207 208 /* 209 * get flags from -I argument and set cf_flags. 210 * NOTE: low 8 bits are to disable disconnect, and the next 211 * 8 bits are to disable sync. 212 */ 213 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 214 & 0xffff; 215 shift_nosync += 16; 216 217 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 218 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 219 shift_nosync += 16; 220 221 #if 1 222 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 223 sc->sc_minsync = 0; 224 #endif 225 226 /* Really no limit, but since we want to fit into the TCR... */ 227 sc->sc_maxxfer = 64 * 1024; 228 229 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 230 231 /* 232 * Configure interrupts. 233 */ 234 bsc->sc_isr.isr_intr = ncr53c9x_intr; 235 bsc->sc_isr.isr_arg = sc; 236 bsc->sc_isr.isr_ipl = 2; 237 add_isr(&bsc->sc_isr); 238 239 /* 240 * Now try to attach all the sub-devices 241 */ 242 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 243 sc->sc_adapter.adapt_minphys = minphys; 244 ncr53c9x_attach(sc); 245 } 246 247 /* 248 * Glue functions. 249 */ 250 251 uint8_t 252 bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 253 { 254 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 255 256 return bsc->sc_reg[reg * 4]; 257 } 258 259 void 260 bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 261 { 262 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 263 uint8_t v = val; 264 265 bsc->sc_reg[reg * 4] = v; 266 #ifdef DEBUG 267 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 268 reg == NCR_CMD/* && bsc->sc_active*/) { 269 bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v; 270 /* printf(" cmd %x", v);*/ 271 } 272 #endif 273 } 274 275 int 276 bztzsc_dma_isintr(struct ncr53c9x_softc *sc) 277 { 278 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 279 280 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 281 return 0; 282 283 if (sc->sc_state == NCR_CONNECTED) 284 bsc->sc_reg[0xe0] = 0; /* Turn LED on */ 285 else 286 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 287 288 #ifdef DEBUG 289 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) { 290 bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 291 bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 292 bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active; 293 bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127; 294 } 295 #endif 296 return 1; 297 } 298 299 void 300 bztzsc_dma_reset(struct ncr53c9x_softc *sc) 301 { 302 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 303 304 bsc->sc_active = 0; 305 } 306 307 int 308 bztzsc_dma_intr(struct ncr53c9x_softc *sc) 309 { 310 register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 311 register int cnt; 312 313 NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 314 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 315 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 316 if (bsc->sc_active == 0) { 317 printf("bztzsc_intr--inactive DMA\n"); 318 return -1; 319 } 320 321 /* update sc_dmaaddr and sc_pdmalen */ 322 cnt = bsc->sc_reg[NCR_TCL * 4]; 323 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 324 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 325 if (!bsc->sc_datain) { 326 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 327 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 328 } 329 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 330 NCR_DMA(("DMA xferred %d\n", cnt)); 331 if (bsc->sc_xfr_align) { 332 memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt); 333 bsc->sc_xfr_align = 0; 334 } 335 *bsc->sc_dmaaddr += cnt; 336 *bsc->sc_pdmalen -= cnt; 337 bsc->sc_active = 0; 338 return 0; 339 } 340 341 int 342 bztzsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 343 int datain, size_t *dmasize) 344 { 345 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 346 paddr_t pa; 347 uint8_t *ptr; 348 size_t xfer; 349 350 bsc->sc_dmaaddr = addr; 351 bsc->sc_pdmalen = len; 352 bsc->sc_datain = datain; 353 bsc->sc_dmasize = *dmasize; 354 /* 355 * DMA can be nasty for high-speed serial input, so limit the 356 * size of this DMA operation if the serial port is running at 357 * a high speed (higher than 19200 for now - should be adjusted 358 * based on CPU type and speed?). 359 * XXX - add serial speed check XXX 360 */ 361 if (ser_open_speed > 19200 && bztzsc_max_dma != 0 && 362 bsc->sc_dmasize > bztzsc_max_dma) 363 bsc->sc_dmasize = bztzsc_max_dma; 364 ptr = *addr; /* Kernel virtual address */ 365 pa = kvtop(ptr); /* Physical address of DMA */ 366 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 367 bsc->sc_xfr_align = 0; 368 /* 369 * If output and unaligned, stuff odd byte into FIFO 370 */ 371 if (datain == 0 && (int)ptr & 1) { 372 NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n")); 373 pa++; 374 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 375 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 376 } 377 /* 378 * If unaligned address, read unaligned bytes into alignment buffer 379 */ 380 else if ((int)ptr & 1) { 381 pa = kvtop((void *)&bsc->sc_alignbuf); 382 xfer = bsc->sc_dmasize = min(xfer, sizeof(bsc->sc_alignbuf)); 383 NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer)); 384 bsc->sc_xfr_align = 1; 385 } 386 ++bztzsc_cnt_dma; /* number of DMA operations */ 387 388 while (xfer < bsc->sc_dmasize) { 389 if ((pa + xfer) != kvtop(*addr + xfer)) 390 break; 391 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 392 xfer = bsc->sc_dmasize; 393 else 394 xfer += PAGE_SIZE; 395 ++bztzsc_cnt_dma3; 396 } 397 if (xfer != *len) 398 ++bztzsc_cnt_dma2; 399 400 bsc->sc_dmasize = xfer; 401 *dmasize = bsc->sc_dmasize; 402 bsc->sc_pa = pa; 403 #if defined(M68040) || defined(M68060) 404 if (mmutype == MMU_68040) { 405 if (bsc->sc_xfr_align) { 406 dma_cachectl(bsc->sc_alignbuf, 407 sizeof(bsc->sc_alignbuf)); 408 } 409 else 410 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 411 } 412 #endif 413 414 pa >>= 1; 415 if (!bsc->sc_datain) 416 pa |= 0x80000000; 417 bsc->sc_dmabase[12] = (uint8_t)(pa); 418 bsc->sc_dmabase[8] = (uint8_t)(pa >> 8); 419 bsc->sc_dmabase[4] = (uint8_t)(pa >> 16); 420 bsc->sc_dmabase[0] = (uint8_t)(pa >> 24); 421 bsc->sc_active = 1; 422 return 0; 423 } 424 425 void 426 bztzsc_dma_go(struct ncr53c9x_softc *sc) 427 { 428 } 429 430 void 431 bztzsc_dma_stop(struct ncr53c9x_softc *sc) 432 { 433 } 434 435 int 436 bztzsc_dma_isactive(struct ncr53c9x_softc *sc) 437 { 438 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 439 440 return bsc->sc_active; 441 } 442 443 #ifdef DEBUG 444 void 445 bztzsc_dump(void) 446 { 447 int i; 448 449 i = bztzsc_trace_ptr; 450 printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr); 451 do { 452 if (bztzsc_trace[i].hardbits == 0) { 453 i = (i + 1) & 127; 454 continue; 455 } 456 printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits, 457 bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy); 458 if (bztzsc_trace[i].status & NCRSTAT_INT) 459 printf("NCRINT/"); 460 if (bztzsc_trace[i].status & NCRSTAT_TC) 461 printf("NCRTC/"); 462 switch(bztzsc_trace[i].status & NCRSTAT_PHASE) { 463 case 0: 464 printf("dataout"); break; 465 case 1: 466 printf("datain"); break; 467 case 2: 468 printf("cmdout"); break; 469 case 3: 470 printf("status"); break; 471 case 6: 472 printf("msgout"); break; 473 case 7: 474 printf("msgin"); break; 475 default: 476 printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE); 477 } 478 printf(") "); 479 i = (i + 1) & 127; 480 } while (i != bztzsc_trace_ptr); 481 printf("\n"); 482 } 483 #endif 484