1 /* $NetBSD: bztzsc.c,v 1.6 1997/10/24 01:43:49 mhitch Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1996 Ignatios Souvatzis 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product contains software written by Ignatios Souvatzis and 20 * Michael L. Hitch for the NetBSD project. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 /* 40 * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <machine/cpu.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <amiga/amiga/isr.h> 68 #include <amiga/dev/bztzscvar.h> 69 #include <amiga/dev/zbusvar.h> 70 71 void bztzscattach __P((struct device *, struct device *, void *)); 72 int bztzscmatch __P((struct device *, struct cfdata *, void *)); 73 74 /* Linkup to the rest of the kernel */ 75 struct cfattach bztzsc_ca = { 76 sizeof(struct bztzsc_softc), bztzscmatch, bztzscattach 77 }; 78 79 struct cfdriver bztzsc_cd = { 80 NULL, "bztzsc", DV_DULL 81 }; 82 83 struct scsipi_adapter bztzsc_switch = { 84 ncr53c9x_scsi_cmd, 85 minphys, /* no max at this level; handled by DMA code */ 86 NULL, 87 NULL, 88 }; 89 90 struct scsipi_device bztzsc_dev = { 91 NULL, /* Use default error handler */ 92 NULL, /* have a queue, served by this */ 93 NULL, /* have no async handler */ 94 NULL, /* Use default 'done' routine */ 95 }; 96 97 /* 98 * Functions and the switch for the MI code. 99 */ 100 u_char bztzsc_read_reg __P((struct ncr53c9x_softc *, int)); 101 void bztzsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 102 int bztzsc_dma_isintr __P((struct ncr53c9x_softc *)); 103 void bztzsc_dma_reset __P((struct ncr53c9x_softc *)); 104 int bztzsc_dma_intr __P((struct ncr53c9x_softc *)); 105 int bztzsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 106 size_t *, int, size_t *)); 107 void bztzsc_dma_go __P((struct ncr53c9x_softc *)); 108 void bztzsc_dma_stop __P((struct ncr53c9x_softc *)); 109 int bztzsc_dma_isactive __P((struct ncr53c9x_softc *)); 110 111 struct ncr53c9x_glue bztzsc_glue = { 112 bztzsc_read_reg, 113 bztzsc_write_reg, 114 bztzsc_dma_isintr, 115 bztzsc_dma_reset, 116 bztzsc_dma_intr, 117 bztzsc_dma_setup, 118 bztzsc_dma_go, 119 bztzsc_dma_stop, 120 bztzsc_dma_isactive, 121 0, 122 }; 123 124 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 125 u_long bztzsc_max_dma = 1024; 126 extern int ser_open_speed; 127 128 u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */ 129 u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */ 130 u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 131 u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */ 132 133 #ifdef DEBUG 134 struct { 135 u_char hardbits; 136 u_char status; 137 u_char xx; 138 u_char yy; 139 } bztzsc_trace[128]; 140 int bztzsc_trace_ptr = 0; 141 int bztzsc_trace_enable = 1; 142 void bztzsc_dump __P((void)); 143 #endif 144 145 /* 146 * if we are a Phase5 Blizzard 2060 SCSI 147 */ 148 int 149 bztzscmatch(parent, cf, aux) 150 struct device *parent; 151 struct cfdata *cf; 152 void *aux; 153 { 154 struct zbus_args *zap; 155 volatile u_char *regs; 156 157 zap = aux; 158 if (zap->manid != 0x2140 || zap->prodid != 24) 159 return(0); 160 regs = &((volatile u_char *)zap->va)[0x1ff00]; 161 if (badaddr((caddr_t)regs)) 162 return(0); 163 regs[NCR_CFG1 * 4] = 0; 164 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 165 delay(5); 166 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 167 return(0); 168 return(1); 169 } 170 171 /* 172 * Attach this instance, and then all the sub-devices 173 */ 174 void 175 bztzscattach(parent, self, aux) 176 struct device *parent, *self; 177 void *aux; 178 { 179 struct bztzsc_softc *bsc = (void *)self; 180 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 181 struct zbus_args *zap; 182 extern u_long scsi_nosync; 183 extern int shift_nosync; 184 extern int ncr53c9x_debug; 185 186 /* 187 * Set up the glue for MI code early; we use some of it here. 188 */ 189 sc->sc_glue = &bztzsc_glue; 190 191 /* 192 * Save the regs 193 */ 194 zap = aux; 195 bsc->sc_reg = &((volatile u_char *)zap->va)[0x1ff00]; 196 bsc->sc_dmabase = &bsc->sc_reg[0xf0]; 197 198 sc->sc_freq = 40; /* Clocked at 40Mhz */ 199 200 printf(": address %p", bsc->sc_reg); 201 202 sc->sc_id = 7; 203 204 /* 205 * It is necessary to try to load the 2nd config register here, 206 * to find out what rev the FAS chip is, else the ncr53c9x_reset 207 * will not set up the defaults correctly. 208 */ 209 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 210 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 211 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 212 sc->sc_rev = NCR_VARIANT_FAS216; 213 214 /* 215 * This is the value used to start sync negotiations 216 * Note that the NCR register "SYNCTP" is programmed 217 * in "clocks per byte", and has a minimum value of 4. 218 * The SCSI period used in negotiation is one-fourth 219 * of the time (in nanoseconds) needed to transfer one byte. 220 * Since the chip's clock is given in MHz, we have the following 221 * formula: 4 * period = (1000 / freq) * 4 222 */ 223 sc->sc_minsync = 1000 / sc->sc_freq; 224 225 /* 226 * get flags from -I argument and set cf_flags. 227 * NOTE: low 8 bits are to disable disconnect, and the next 228 * 8 bits are to disable sync. 229 */ 230 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 231 & 0xffff; 232 shift_nosync += 16; 233 234 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 235 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 236 shift_nosync += 16; 237 238 #if 1 239 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 240 sc->sc_minsync = 0; 241 #endif 242 243 /* Really no limit, but since we want to fit into the TCR... */ 244 sc->sc_maxxfer = 64 * 1024; 245 246 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 247 248 /* 249 * Configure interrupts. 250 */ 251 bsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 252 bsc->sc_isr.isr_arg = sc; 253 bsc->sc_isr.isr_ipl = 2; 254 add_isr(&bsc->sc_isr); 255 256 /* 257 * Now try to attach all the sub-devices 258 */ 259 ncr53c9x_attach(sc, &bztzsc_switch, &bztzsc_dev); 260 } 261 262 /* 263 * Glue functions. 264 */ 265 266 u_char 267 bztzsc_read_reg(sc, reg) 268 struct ncr53c9x_softc *sc; 269 int reg; 270 { 271 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 272 273 return bsc->sc_reg[reg * 4]; 274 } 275 276 void 277 bztzsc_write_reg(sc, reg, val) 278 struct ncr53c9x_softc *sc; 279 int reg; 280 u_char val; 281 { 282 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 283 u_char v = val; 284 285 bsc->sc_reg[reg * 4] = v; 286 #ifdef DEBUG 287 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ && 288 reg == NCR_CMD/* && bsc->sc_active*/) { 289 bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v; 290 /* printf(" cmd %x", v);*/ 291 } 292 #endif 293 } 294 295 int 296 bztzsc_dma_isintr(sc) 297 struct ncr53c9x_softc *sc; 298 { 299 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 300 301 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 302 return 0; 303 304 if (sc->sc_state == NCR_CONNECTED) 305 bsc->sc_reg[0xe0] = 0; /* Turn LED on */ 306 else 307 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 308 309 #ifdef DEBUG 310 if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ bztzsc_trace_enable) { 311 bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 312 bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 313 bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active; 314 bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127; 315 } 316 #endif 317 return 1; 318 } 319 320 void 321 bztzsc_dma_reset(sc) 322 struct ncr53c9x_softc *sc; 323 { 324 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 325 326 bsc->sc_active = 0; 327 } 328 329 int 330 bztzsc_dma_intr(sc) 331 struct ncr53c9x_softc *sc; 332 { 333 register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 334 register int cnt; 335 336 NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 337 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 338 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 339 if (bsc->sc_active == 0) { 340 printf("bztzsc_intr--inactive DMA\n"); 341 return -1; 342 } 343 344 /* update sc_dmaaddr and sc_pdmalen */ 345 cnt = bsc->sc_reg[NCR_TCL * 4]; 346 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 347 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 348 if (!bsc->sc_datain) { 349 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 350 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 351 } 352 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 353 NCR_DMA(("DMA xferred %d\n", cnt)); 354 if (bsc->sc_xfr_align) { 355 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 356 bsc->sc_xfr_align = 0; 357 } 358 *bsc->sc_dmaaddr += cnt; 359 *bsc->sc_pdmalen -= cnt; 360 bsc->sc_active = 0; 361 return 0; 362 } 363 364 int 365 bztzsc_dma_setup(sc, addr, len, datain, dmasize) 366 struct ncr53c9x_softc *sc; 367 caddr_t *addr; 368 size_t *len; 369 int datain; 370 size_t *dmasize; 371 { 372 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 373 vm_offset_t pa; 374 u_char *ptr; 375 size_t xfer; 376 377 bsc->sc_dmaaddr = addr; 378 bsc->sc_pdmalen = len; 379 bsc->sc_datain = datain; 380 bsc->sc_dmasize = *dmasize; 381 /* 382 * DMA can be nasty for high-speed serial input, so limit the 383 * size of this DMA operation if the serial port is running at 384 * a high speed (higher than 19200 for now - should be adjusted 385 * based on cpu type and speed?). 386 * XXX - add serial speed check XXX 387 */ 388 if (ser_open_speed > 19200 && bztzsc_max_dma != 0 && 389 bsc->sc_dmasize > bztzsc_max_dma) 390 bsc->sc_dmasize = bztzsc_max_dma; 391 ptr = *addr; /* Kernel virtual address */ 392 pa = kvtop(ptr); /* Physical address of DMA */ 393 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 394 bsc->sc_xfr_align = 0; 395 /* 396 * If output and unaligned, stuff odd byte into FIFO 397 */ 398 if (datain == 0 && (int)ptr & 1) { 399 NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n")); 400 pa++; 401 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 402 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 403 } 404 /* 405 * If unaligned address, read unaligned bytes into alignment buffer 406 */ 407 else if ((int)ptr & 1) { 408 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 409 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 410 NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer)); 411 bsc->sc_xfr_align = 1; 412 } 413 ++bztzsc_cnt_dma; /* number of DMA operations */ 414 415 while (xfer < bsc->sc_dmasize) { 416 if ((pa + xfer) != kvtop(*addr + xfer)) 417 break; 418 if ((bsc->sc_dmasize - xfer) < NBPG) 419 xfer = bsc->sc_dmasize; 420 else 421 xfer += NBPG; 422 ++bztzsc_cnt_dma3; 423 } 424 if (xfer != *len) 425 ++bztzsc_cnt_dma2; 426 427 bsc->sc_dmasize = xfer; 428 *dmasize = bsc->sc_dmasize; 429 bsc->sc_pa = pa; 430 #if defined(M68040) || defined(M68060) 431 if (mmutype == MMU_68040) { 432 if (bsc->sc_xfr_align) { 433 dma_cachectl(bsc->sc_alignbuf, 434 sizeof(bsc->sc_alignbuf)); 435 } 436 else 437 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 438 } 439 #endif 440 441 pa >>= 1; 442 if (!bsc->sc_datain) 443 pa |= 0x80000000; 444 bsc->sc_dmabase[12] = (u_int8_t)(pa); 445 bsc->sc_dmabase[8] = (u_int8_t)(pa >> 8); 446 bsc->sc_dmabase[4] = (u_int8_t)(pa >> 16); 447 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 448 bsc->sc_active = 1; 449 return 0; 450 } 451 452 void 453 bztzsc_dma_go(sc) 454 struct ncr53c9x_softc *sc; 455 { 456 } 457 458 void 459 bztzsc_dma_stop(sc) 460 struct ncr53c9x_softc *sc; 461 { 462 } 463 464 int 465 bztzsc_dma_isactive(sc) 466 struct ncr53c9x_softc *sc; 467 { 468 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 469 470 return bsc->sc_active; 471 } 472 473 #ifdef DEBUG 474 void 475 bztzsc_dump() 476 { 477 int i; 478 479 i = bztzsc_trace_ptr; 480 printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr); 481 do { 482 if (bztzsc_trace[i].hardbits == 0) { 483 i = (i + 1) & 127; 484 continue; 485 } 486 printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits, 487 bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy); 488 if (bztzsc_trace[i].status & NCRSTAT_INT) 489 printf("NCRINT/"); 490 if (bztzsc_trace[i].status & NCRSTAT_TC) 491 printf("NCRTC/"); 492 switch(bztzsc_trace[i].status & NCRSTAT_PHASE) { 493 case 0: 494 printf("dataout"); break; 495 case 1: 496 printf("datain"); break; 497 case 2: 498 printf("cmdout"); break; 499 case 3: 500 printf("status"); break; 501 case 6: 502 printf("msgout"); break; 503 case 7: 504 printf("msgin"); break; 505 default: 506 printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE); 507 } 508 printf(") "); 509 i = (i + 1) & 127; 510 } while (i != bztzsc_trace_ptr); 511 printf("\n"); 512 } 513 #endif 514