1 /* $NetBSD: bztzsc.c,v 1.23 2005/12/11 12:16:28 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1996 Ignatios Souvatzis 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product contains software written by Ignatios Souvatzis and 20 * Michael L. Hitch for the NetBSD project. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 /* 40 * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: bztzsc.c,v 1.23 2005/12/11 12:16:28 christos Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 #include <sys/queue.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 #include <dev/scsipi/scsi_message.h> 65 66 #include <machine/cpu.h> 67 #include <machine/param.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <amiga/amiga/isr.h> 73 #include <amiga/dev/bztzscvar.h> 74 #include <amiga/dev/zbusvar.h> 75 76 void bztzscattach(struct device *, struct device *, void *); 77 int bztzscmatch(struct device *, struct cfdata *, void *); 78 79 /* Linkup to the rest of the kernel */ 80 CFATTACH_DECL(bztzsc, sizeof(struct bztzsc_softc), 81 bztzscmatch, bztzscattach, NULL, NULL); 82 83 /* 84 * Functions and the switch for the MI code. 85 */ 86 u_char bztzsc_read_reg(struct ncr53c9x_softc *, int); 87 void bztzsc_write_reg(struct ncr53c9x_softc *, int, u_char); 88 int bztzsc_dma_isintr(struct ncr53c9x_softc *); 89 void bztzsc_dma_reset(struct ncr53c9x_softc *); 90 int bztzsc_dma_intr(struct ncr53c9x_softc *); 91 int bztzsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 92 size_t *, int, size_t *); 93 void bztzsc_dma_go(struct ncr53c9x_softc *); 94 void bztzsc_dma_stop(struct ncr53c9x_softc *); 95 int bztzsc_dma_isactive(struct ncr53c9x_softc *); 96 97 struct ncr53c9x_glue bztzsc_glue = { 98 bztzsc_read_reg, 99 bztzsc_write_reg, 100 bztzsc_dma_isintr, 101 bztzsc_dma_reset, 102 bztzsc_dma_intr, 103 bztzsc_dma_setup, 104 bztzsc_dma_go, 105 bztzsc_dma_stop, 106 bztzsc_dma_isactive, 107 0, 108 }; 109 110 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 111 u_long bztzsc_max_dma = 1024; 112 extern int ser_open_speed; 113 114 u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */ 115 u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */ 116 u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 117 u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */ 118 119 #ifdef DEBUG 120 struct { 121 u_char hardbits; 122 u_char status; 123 u_char xx; 124 u_char yy; 125 } bztzsc_trace[128]; 126 int bztzsc_trace_ptr = 0; 127 int bztzsc_trace_enable = 1; 128 void bztzsc_dump(void); 129 #endif 130 131 /* 132 * if we are a Phase5 Blizzard 2060 SCSI 133 */ 134 int 135 bztzscmatch(struct device *parent, struct cfdata *cf, void *aux) 136 { 137 struct zbus_args *zap; 138 volatile u_char *regs; 139 140 zap = aux; 141 if (zap->manid != 0x2140 || zap->prodid != 24) 142 return(0); 143 regs = &((volatile u_char *)zap->va)[0x1ff00]; 144 if (badaddr((caddr_t)__UNVOLATILE(regs))) 145 return(0); 146 regs[NCR_CFG1 * 4] = 0; 147 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 148 delay(5); 149 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 150 return(0); 151 return(1); 152 } 153 154 /* 155 * Attach this instance, and then all the sub-devices 156 */ 157 void 158 bztzscattach(struct device *parent, struct device *self, void *aux) 159 { 160 struct bztzsc_softc *bsc = (void *)self; 161 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 162 struct zbus_args *zap; 163 extern u_long scsi_nosync; 164 extern int shift_nosync; 165 extern int ncr53c9x_debug; 166 167 /* 168 * Set up the glue for MI code early; we use some of it here. 169 */ 170 sc->sc_glue = &bztzsc_glue; 171 172 /* 173 * Save the regs 174 */ 175 zap = aux; 176 bsc->sc_reg = &((volatile u_char *)zap->va)[0x1ff00]; 177 bsc->sc_dmabase = &bsc->sc_reg[0xf0]; 178 179 sc->sc_freq = 40; /* Clocked at 40Mhz */ 180 181 printf(": address %p", bsc->sc_reg); 182 183 sc->sc_id = 7; 184 185 /* 186 * It is necessary to try to load the 2nd config register here, 187 * to find out what rev the FAS chip is, else the ncr53c9x_reset 188 * will not set up the defaults correctly. 189 */ 190 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 191 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 192 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 193 sc->sc_rev = NCR_VARIANT_FAS216; 194 195 /* 196 * This is the value used to start sync negotiations 197 * Note that the NCR register "SYNCTP" is programmed 198 * in "clocks per byte", and has a minimum value of 4. 199 * The SCSI period used in negotiation is one-fourth 200 * of the time (in nanoseconds) needed to transfer one byte. 201 * Since the chip's clock is given in MHz, we have the following 202 * formula: 4 * period = (1000 / freq) * 4 203 */ 204 sc->sc_minsync = 1000 / sc->sc_freq; 205 206 /* 207 * get flags from -I argument and set cf_flags. 208 * NOTE: low 8 bits are to disable disconnect, and the next 209 * 8 bits are to disable sync. 210 */ 211 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 212 & 0xffff; 213 shift_nosync += 16; 214 215 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 216 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 217 shift_nosync += 16; 218 219 #if 1 220 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 221 sc->sc_minsync = 0; 222 #endif 223 224 /* Really no limit, but since we want to fit into the TCR... */ 225 sc->sc_maxxfer = 64 * 1024; 226 227 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 228 229 /* 230 * Configure interrupts. 231 */ 232 bsc->sc_isr.isr_intr = ncr53c9x_intr; 233 bsc->sc_isr.isr_arg = sc; 234 bsc->sc_isr.isr_ipl = 2; 235 add_isr(&bsc->sc_isr); 236 237 /* 238 * Now try to attach all the sub-devices 239 */ 240 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 241 sc->sc_adapter.adapt_minphys = minphys; 242 ncr53c9x_attach(sc); 243 } 244 245 /* 246 * Glue functions. 247 */ 248 249 u_char 250 bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 251 { 252 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 253 254 return bsc->sc_reg[reg * 4]; 255 } 256 257 void 258 bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 259 { 260 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 261 u_char v = val; 262 263 bsc->sc_reg[reg * 4] = v; 264 #ifdef DEBUG 265 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 266 reg == NCR_CMD/* && bsc->sc_active*/) { 267 bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v; 268 /* printf(" cmd %x", v);*/ 269 } 270 #endif 271 } 272 273 int 274 bztzsc_dma_isintr(struct ncr53c9x_softc *sc) 275 { 276 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 277 278 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 279 return 0; 280 281 if (sc->sc_state == NCR_CONNECTED) 282 bsc->sc_reg[0xe0] = 0; /* Turn LED on */ 283 else 284 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 285 286 #ifdef DEBUG 287 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) { 288 bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 289 bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 290 bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active; 291 bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127; 292 } 293 #endif 294 return 1; 295 } 296 297 void 298 bztzsc_dma_reset(struct ncr53c9x_softc *sc) 299 { 300 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 301 302 bsc->sc_active = 0; 303 } 304 305 int 306 bztzsc_dma_intr(struct ncr53c9x_softc *sc) 307 { 308 register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 309 register int cnt; 310 311 NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 312 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 313 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 314 if (bsc->sc_active == 0) { 315 printf("bztzsc_intr--inactive DMA\n"); 316 return -1; 317 } 318 319 /* update sc_dmaaddr and sc_pdmalen */ 320 cnt = bsc->sc_reg[NCR_TCL * 4]; 321 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 322 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 323 if (!bsc->sc_datain) { 324 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 325 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 326 } 327 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 328 NCR_DMA(("DMA xferred %d\n", cnt)); 329 if (bsc->sc_xfr_align) { 330 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 331 bsc->sc_xfr_align = 0; 332 } 333 *bsc->sc_dmaaddr += cnt; 334 *bsc->sc_pdmalen -= cnt; 335 bsc->sc_active = 0; 336 return 0; 337 } 338 339 int 340 bztzsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 341 int datain, size_t *dmasize) 342 { 343 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 344 paddr_t pa; 345 u_char *ptr; 346 size_t xfer; 347 348 bsc->sc_dmaaddr = addr; 349 bsc->sc_pdmalen = len; 350 bsc->sc_datain = datain; 351 bsc->sc_dmasize = *dmasize; 352 /* 353 * DMA can be nasty for high-speed serial input, so limit the 354 * size of this DMA operation if the serial port is running at 355 * a high speed (higher than 19200 for now - should be adjusted 356 * based on CPU type and speed?). 357 * XXX - add serial speed check XXX 358 */ 359 if (ser_open_speed > 19200 && bztzsc_max_dma != 0 && 360 bsc->sc_dmasize > bztzsc_max_dma) 361 bsc->sc_dmasize = bztzsc_max_dma; 362 ptr = *addr; /* Kernel virtual address */ 363 pa = kvtop(ptr); /* Physical address of DMA */ 364 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 365 bsc->sc_xfr_align = 0; 366 /* 367 * If output and unaligned, stuff odd byte into FIFO 368 */ 369 if (datain == 0 && (int)ptr & 1) { 370 NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n")); 371 pa++; 372 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 373 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 374 } 375 /* 376 * If unaligned address, read unaligned bytes into alignment buffer 377 */ 378 else if ((int)ptr & 1) { 379 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 380 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 381 NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer)); 382 bsc->sc_xfr_align = 1; 383 } 384 ++bztzsc_cnt_dma; /* number of DMA operations */ 385 386 while (xfer < bsc->sc_dmasize) { 387 if ((pa + xfer) != kvtop(*addr + xfer)) 388 break; 389 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 390 xfer = bsc->sc_dmasize; 391 else 392 xfer += PAGE_SIZE; 393 ++bztzsc_cnt_dma3; 394 } 395 if (xfer != *len) 396 ++bztzsc_cnt_dma2; 397 398 bsc->sc_dmasize = xfer; 399 *dmasize = bsc->sc_dmasize; 400 bsc->sc_pa = pa; 401 #if defined(M68040) || defined(M68060) 402 if (mmutype == MMU_68040) { 403 if (bsc->sc_xfr_align) { 404 dma_cachectl(bsc->sc_alignbuf, 405 sizeof(bsc->sc_alignbuf)); 406 } 407 else 408 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 409 } 410 #endif 411 412 pa >>= 1; 413 if (!bsc->sc_datain) 414 pa |= 0x80000000; 415 bsc->sc_dmabase[12] = (u_int8_t)(pa); 416 bsc->sc_dmabase[8] = (u_int8_t)(pa >> 8); 417 bsc->sc_dmabase[4] = (u_int8_t)(pa >> 16); 418 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 419 bsc->sc_active = 1; 420 return 0; 421 } 422 423 void 424 bztzsc_dma_go(struct ncr53c9x_softc *sc) 425 { 426 } 427 428 void 429 bztzsc_dma_stop(struct ncr53c9x_softc *sc) 430 { 431 } 432 433 int 434 bztzsc_dma_isactive(struct ncr53c9x_softc *sc) 435 { 436 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 437 438 return bsc->sc_active; 439 } 440 441 #ifdef DEBUG 442 void 443 bztzsc_dump(void) 444 { 445 int i; 446 447 i = bztzsc_trace_ptr; 448 printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr); 449 do { 450 if (bztzsc_trace[i].hardbits == 0) { 451 i = (i + 1) & 127; 452 continue; 453 } 454 printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits, 455 bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy); 456 if (bztzsc_trace[i].status & NCRSTAT_INT) 457 printf("NCRINT/"); 458 if (bztzsc_trace[i].status & NCRSTAT_TC) 459 printf("NCRTC/"); 460 switch(bztzsc_trace[i].status & NCRSTAT_PHASE) { 461 case 0: 462 printf("dataout"); break; 463 case 1: 464 printf("datain"); break; 465 case 2: 466 printf("cmdout"); break; 467 case 3: 468 printf("status"); break; 469 case 6: 470 printf("msgout"); break; 471 case 7: 472 printf("msgin"); break; 473 default: 474 printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE); 475 } 476 printf(") "); 477 i = (i + 1) & 127; 478 } while (i != bztzsc_trace_ptr); 479 printf("\n"); 480 } 481 #endif 482