1 /* $NetBSD: bztzsc.c,v 1.30 2007/10/17 19:53:15 garbled Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1996 Ignatios Souvatzis 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product contains software written by Ignatios Souvatzis and 20 * Michael L. Hitch for the NetBSD project. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 /* 40 * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: bztzsc.c,v 1.30 2007/10/17 19:53:15 garbled Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 #include <sys/queue.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 #include <dev/scsipi/scsi_message.h> 65 66 #include <machine/cpu.h> 67 #include <machine/param.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <amiga/amiga/isr.h> 73 #include <amiga/dev/bztzscvar.h> 74 #include <amiga/dev/zbusvar.h> 75 76 #ifdef __powerpc__ 77 #define badaddr(a) badaddr_read(a, 2, NULL) 78 #endif 79 80 void bztzscattach(struct device *, struct device *, void *); 81 int bztzscmatch(struct device *, struct cfdata *, void *); 82 83 /* Linkup to the rest of the kernel */ 84 CFATTACH_DECL(bztzsc, sizeof(struct bztzsc_softc), 85 bztzscmatch, bztzscattach, NULL, NULL); 86 87 /* 88 * Functions and the switch for the MI code. 89 */ 90 u_char bztzsc_read_reg(struct ncr53c9x_softc *, int); 91 void bztzsc_write_reg(struct ncr53c9x_softc *, int, u_char); 92 int bztzsc_dma_isintr(struct ncr53c9x_softc *); 93 void bztzsc_dma_reset(struct ncr53c9x_softc *); 94 int bztzsc_dma_intr(struct ncr53c9x_softc *); 95 int bztzsc_dma_setup(struct ncr53c9x_softc *, void **, 96 size_t *, int, size_t *); 97 void bztzsc_dma_go(struct ncr53c9x_softc *); 98 void bztzsc_dma_stop(struct ncr53c9x_softc *); 99 int bztzsc_dma_isactive(struct ncr53c9x_softc *); 100 101 struct ncr53c9x_glue bztzsc_glue = { 102 bztzsc_read_reg, 103 bztzsc_write_reg, 104 bztzsc_dma_isintr, 105 bztzsc_dma_reset, 106 bztzsc_dma_intr, 107 bztzsc_dma_setup, 108 bztzsc_dma_go, 109 bztzsc_dma_stop, 110 bztzsc_dma_isactive, 111 0, 112 }; 113 114 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 115 u_long bztzsc_max_dma = 1024; 116 extern int ser_open_speed; 117 118 u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */ 119 u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */ 120 u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 121 u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */ 122 123 #ifdef DEBUG 124 struct { 125 u_char hardbits; 126 u_char status; 127 u_char xx; 128 u_char yy; 129 } bztzsc_trace[128]; 130 int bztzsc_trace_ptr = 0; 131 int bztzsc_trace_enable = 1; 132 void bztzsc_dump(void); 133 #endif 134 135 /* 136 * if we are a Phase5 Blizzard 2060 SCSI 137 */ 138 int 139 bztzscmatch(struct device *parent, struct cfdata *cf, void *aux) 140 { 141 struct zbus_args *zap; 142 volatile u_char *regs; 143 144 zap = aux; 145 if (zap->manid != 0x2140 || zap->prodid != 24) 146 return(0); 147 regs = &((volatile u_char *)zap->va)[0x1ff00]; 148 if (badaddr((void *)__UNVOLATILE(regs))) 149 return(0); 150 regs[NCR_CFG1 * 4] = 0; 151 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 152 delay(5); 153 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 154 return(0); 155 return(1); 156 } 157 158 /* 159 * Attach this instance, and then all the sub-devices 160 */ 161 void 162 bztzscattach(struct device *parent, struct device *self, void *aux) 163 { 164 struct bztzsc_softc *bsc = (void *)self; 165 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 166 struct zbus_args *zap; 167 extern u_long scsi_nosync; 168 extern int shift_nosync; 169 extern int ncr53c9x_debug; 170 171 /* 172 * Set up the glue for MI code early; we use some of it here. 173 */ 174 sc->sc_glue = &bztzsc_glue; 175 176 /* 177 * Save the regs 178 */ 179 zap = aux; 180 bsc->sc_reg = &((volatile u_char *)zap->va)[0x1ff00]; 181 bsc->sc_dmabase = &bsc->sc_reg[0xf0]; 182 183 sc->sc_freq = 40; /* Clocked at 40 MHz */ 184 185 printf(": address %p", bsc->sc_reg); 186 187 sc->sc_id = 7; 188 189 /* 190 * It is necessary to try to load the 2nd config register here, 191 * to find out what rev the FAS chip is, else the ncr53c9x_reset 192 * will not set up the defaults correctly. 193 */ 194 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 195 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 196 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 197 sc->sc_rev = NCR_VARIANT_FAS216; 198 199 /* 200 * This is the value used to start sync negotiations 201 * Note that the NCR register "SYNCTP" is programmed 202 * in "clocks per byte", and has a minimum value of 4. 203 * The SCSI period used in negotiation is one-fourth 204 * of the time (in nanoseconds) needed to transfer one byte. 205 * Since the chip's clock is given in MHz, we have the following 206 * formula: 4 * period = (1000 / freq) * 4 207 */ 208 sc->sc_minsync = 1000 / sc->sc_freq; 209 210 /* 211 * get flags from -I argument and set cf_flags. 212 * NOTE: low 8 bits are to disable disconnect, and the next 213 * 8 bits are to disable sync. 214 */ 215 device_cfdata(&sc->sc_dev)->cf_flags |= (scsi_nosync >> shift_nosync) 216 & 0xffff; 217 shift_nosync += 16; 218 219 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 220 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 221 shift_nosync += 16; 222 223 #if 1 224 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 225 sc->sc_minsync = 0; 226 #endif 227 228 /* Really no limit, but since we want to fit into the TCR... */ 229 sc->sc_maxxfer = 64 * 1024; 230 231 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 232 233 /* 234 * Configure interrupts. 235 */ 236 bsc->sc_isr.isr_intr = ncr53c9x_intr; 237 bsc->sc_isr.isr_arg = sc; 238 bsc->sc_isr.isr_ipl = 2; 239 add_isr(&bsc->sc_isr); 240 241 /* 242 * Now try to attach all the sub-devices 243 */ 244 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 245 sc->sc_adapter.adapt_minphys = minphys; 246 ncr53c9x_attach(sc); 247 } 248 249 /* 250 * Glue functions. 251 */ 252 253 u_char 254 bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 255 { 256 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 257 258 return bsc->sc_reg[reg * 4]; 259 } 260 261 void 262 bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 263 { 264 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 265 u_char v = val; 266 267 bsc->sc_reg[reg * 4] = v; 268 #ifdef DEBUG 269 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 270 reg == NCR_CMD/* && bsc->sc_active*/) { 271 bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v; 272 /* printf(" cmd %x", v);*/ 273 } 274 #endif 275 } 276 277 int 278 bztzsc_dma_isintr(struct ncr53c9x_softc *sc) 279 { 280 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 281 282 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 283 return 0; 284 285 if (sc->sc_state == NCR_CONNECTED) 286 bsc->sc_reg[0xe0] = 0; /* Turn LED on */ 287 else 288 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 289 290 #ifdef DEBUG 291 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) { 292 bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 293 bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 294 bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active; 295 bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127; 296 } 297 #endif 298 return 1; 299 } 300 301 void 302 bztzsc_dma_reset(struct ncr53c9x_softc *sc) 303 { 304 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 305 306 bsc->sc_active = 0; 307 } 308 309 int 310 bztzsc_dma_intr(struct ncr53c9x_softc *sc) 311 { 312 register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 313 register int cnt; 314 315 NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 316 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 317 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 318 if (bsc->sc_active == 0) { 319 printf("bztzsc_intr--inactive DMA\n"); 320 return -1; 321 } 322 323 /* update sc_dmaaddr and sc_pdmalen */ 324 cnt = bsc->sc_reg[NCR_TCL * 4]; 325 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 326 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 327 if (!bsc->sc_datain) { 328 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 329 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 330 } 331 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 332 NCR_DMA(("DMA xferred %d\n", cnt)); 333 if (bsc->sc_xfr_align) { 334 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 335 bsc->sc_xfr_align = 0; 336 } 337 *bsc->sc_dmaaddr += cnt; 338 *bsc->sc_pdmalen -= cnt; 339 bsc->sc_active = 0; 340 return 0; 341 } 342 343 int 344 bztzsc_dma_setup(struct ncr53c9x_softc *sc, void **addr, size_t *len, 345 int datain, size_t *dmasize) 346 { 347 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 348 paddr_t pa; 349 u_char *ptr; 350 size_t xfer; 351 352 bsc->sc_dmaaddr = (char **)addr; 353 bsc->sc_pdmalen = len; 354 bsc->sc_datain = datain; 355 bsc->sc_dmasize = *dmasize; 356 /* 357 * DMA can be nasty for high-speed serial input, so limit the 358 * size of this DMA operation if the serial port is running at 359 * a high speed (higher than 19200 for now - should be adjusted 360 * based on CPU type and speed?). 361 * XXX - add serial speed check XXX 362 */ 363 if (ser_open_speed > 19200 && bztzsc_max_dma != 0 && 364 bsc->sc_dmasize > bztzsc_max_dma) 365 bsc->sc_dmasize = bztzsc_max_dma; 366 ptr = *addr; /* Kernel virtual address */ 367 pa = kvtop(ptr); /* Physical address of DMA */ 368 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 369 bsc->sc_xfr_align = 0; 370 /* 371 * If output and unaligned, stuff odd byte into FIFO 372 */ 373 if (datain == 0 && (int)ptr & 1) { 374 NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n")); 375 pa++; 376 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 377 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 378 } 379 /* 380 * If unaligned address, read unaligned bytes into alignment buffer 381 */ 382 else if ((int)ptr & 1) { 383 pa = kvtop((void *)&bsc->sc_alignbuf); 384 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 385 NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer)); 386 bsc->sc_xfr_align = 1; 387 } 388 ++bztzsc_cnt_dma; /* number of DMA operations */ 389 390 while (xfer < bsc->sc_dmasize) { 391 if ((pa + xfer) != kvtop((char*)*addr + xfer)) 392 break; 393 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 394 xfer = bsc->sc_dmasize; 395 else 396 xfer += PAGE_SIZE; 397 ++bztzsc_cnt_dma3; 398 } 399 if (xfer != *len) 400 ++bztzsc_cnt_dma2; 401 402 bsc->sc_dmasize = xfer; 403 *dmasize = bsc->sc_dmasize; 404 bsc->sc_pa = pa; 405 #if defined(M68040) || defined(M68060) 406 if (mmutype == MMU_68040) { 407 if (bsc->sc_xfr_align) { 408 dma_cachectl(bsc->sc_alignbuf, 409 sizeof(bsc->sc_alignbuf)); 410 } 411 else 412 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 413 } 414 #endif 415 416 pa >>= 1; 417 if (!bsc->sc_datain) 418 pa |= 0x80000000; 419 bsc->sc_dmabase[12] = (u_int8_t)(pa); 420 bsc->sc_dmabase[8] = (u_int8_t)(pa >> 8); 421 bsc->sc_dmabase[4] = (u_int8_t)(pa >> 16); 422 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 423 bsc->sc_active = 1; 424 return 0; 425 } 426 427 void 428 bztzsc_dma_go(struct ncr53c9x_softc *sc) 429 { 430 } 431 432 void 433 bztzsc_dma_stop(struct ncr53c9x_softc *sc) 434 { 435 } 436 437 int 438 bztzsc_dma_isactive(struct ncr53c9x_softc *sc) 439 { 440 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 441 442 return bsc->sc_active; 443 } 444 445 #ifdef DEBUG 446 void 447 bztzsc_dump(void) 448 { 449 int i; 450 451 i = bztzsc_trace_ptr; 452 printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr); 453 do { 454 if (bztzsc_trace[i].hardbits == 0) { 455 i = (i + 1) & 127; 456 continue; 457 } 458 printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits, 459 bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy); 460 if (bztzsc_trace[i].status & NCRSTAT_INT) 461 printf("NCRINT/"); 462 if (bztzsc_trace[i].status & NCRSTAT_TC) 463 printf("NCRTC/"); 464 switch(bztzsc_trace[i].status & NCRSTAT_PHASE) { 465 case 0: 466 printf("dataout"); break; 467 case 1: 468 printf("datain"); break; 469 case 2: 470 printf("cmdout"); break; 471 case 3: 472 printf("status"); break; 473 case 6: 474 printf("msgout"); break; 475 case 7: 476 printf("msgin"); break; 477 default: 478 printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE); 479 } 480 printf(") "); 481 i = (i + 1) & 127; 482 } while (i != bztzsc_trace_ptr); 483 printf("\n"); 484 } 485 #endif 486