xref: /netbsd-src/sys/arch/amiga/dev/bztzsc.c (revision 7d62b00eb9ad855ffcd7da46b41e23feb5476fac) 
1 /*	$NetBSD: bztzsc.c,v 1.38 2019/01/08 19:41:09 jdolecek Exp $ */
2 
3 /*
4  * Copyright (c) 1997 Michael L. Hitch
5  * Copyright (c) 1996 Ignatios Souvatzis
6  * Copyright (c) 1982, 1990 The Regents of the University of California.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. Neither the name of the University nor the names of its contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  *
33  */
34 
35 /*
36  * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis.  Conversion to
37  * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu).
38  */
39 
40 #ifdef __m68k__
41 #include "opt_m68k_arch.h"
42 #endif
43 
44 #include <sys/cdefs.h>
45 __KERNEL_RCSID(0, "$NetBSD: bztzsc.c,v 1.38 2019/01/08 19:41:09 jdolecek Exp $");
46 
47 #include <sys/types.h>
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/errno.h>
52 #include <sys/ioctl.h>
53 #include <sys/device.h>
54 #include <sys/buf.h>
55 #include <sys/proc.h>
56 #include <sys/queue.h>
57 
58 #include <dev/scsipi/scsi_all.h>
59 #include <dev/scsipi/scsipi_all.h>
60 #include <dev/scsipi/scsiconf.h>
61 #include <dev/scsipi/scsi_message.h>
62 
63 #include <machine/cpu.h>
64 
65 #include <dev/ic/ncr53c9xreg.h>
66 #include <dev/ic/ncr53c9xvar.h>
67 
68 #include <amiga/amiga/isr.h>
69 #include <amiga/dev/bztzscvar.h>
70 #include <amiga/dev/zbusvar.h>
71 
72 #ifdef __powerpc__
73 #define badaddr(a)      badaddr_read(a, 2, NULL)
74 #endif
75 
76 int	bztzscmatch(device_t, cfdata_t, void *);
77 void	bztzscattach(device_t, device_t, void *);
78 
79 /* Linkup to the rest of the kernel */
80 CFATTACH_DECL_NEW(bztzsc, sizeof(struct bztzsc_softc),
81     bztzscmatch, bztzscattach, NULL, NULL);
82 
83 /*
84  * Functions and the switch for the MI code.
85  */
86 uint8_t	bztzsc_read_reg(struct ncr53c9x_softc *, int);
87 void	bztzsc_write_reg(struct ncr53c9x_softc *, int, uint8_t);
88 int	bztzsc_dma_isintr(struct ncr53c9x_softc *);
89 void	bztzsc_dma_reset(struct ncr53c9x_softc *);
90 int	bztzsc_dma_intr(struct ncr53c9x_softc *);
91 int	bztzsc_dma_setup(struct ncr53c9x_softc *, uint8_t **,
92 	    size_t *, int, size_t *);
93 void	bztzsc_dma_go(struct ncr53c9x_softc *);
94 void	bztzsc_dma_stop(struct ncr53c9x_softc *);
95 int	bztzsc_dma_isactive(struct ncr53c9x_softc *);
96 
97 struct ncr53c9x_glue bztzsc_glue = {
98 	bztzsc_read_reg,
99 	bztzsc_write_reg,
100 	bztzsc_dma_isintr,
101 	bztzsc_dma_reset,
102 	bztzsc_dma_intr,
103 	bztzsc_dma_setup,
104 	bztzsc_dma_go,
105 	bztzsc_dma_stop,
106 	bztzsc_dma_isactive,
107 	NULL,
108 };
109 
110 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
111 u_long bztzsc_max_dma = 1024;
112 extern int ser_open_speed;
113 
114 u_long bztzsc_cnt_pio = 0;	/* number of PIO transfers */
115 u_long bztzsc_cnt_dma = 0;	/* number of DMA transfers */
116 u_long bztzsc_cnt_dma2 = 0;	/* number of DMA transfers broken up */
117 u_long bztzsc_cnt_dma3 = 0;	/* number of pages combined */
118 
119 #ifdef DEBUG
120 struct {
121 	uint8_t hardbits;
122 	uint8_t status;
123 	uint8_t xx;
124 	uint8_t yy;
125 } bztzsc_trace[128];
126 int bztzsc_trace_ptr = 0;
127 int bztzsc_trace_enable = 1;
128 void bztzsc_dump(void);
129 #endif
130 
131 /*
132  * if we are a Phase5 Blizzard 2060 SCSI
133  */
134 int
135 bztzscmatch(device_t parent, cfdata_t cf, void *aux)
136 {
137 	struct zbus_args *zap;
138 	volatile uint8_t *regs;
139 
140 	zap = aux;
141 	if (zap->manid != 0x2140 || zap->prodid != 24)
142 		return 0;
143 	regs = &((volatile uint8_t *)zap->va)[0x1ff00];
144 	if (badaddr((void *)__UNVOLATILE(regs)))
145 		return 0;
146 	regs[NCR_CFG1 * 4] = 0;
147 	regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
148 	delay(5);
149 	if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
150 		return 0;
151 	return 1;
152 }
153 
154 /*
155  * Attach this instance, and then all the sub-devices
156  */
157 void
158 bztzscattach(device_t parent, device_t self, void *aux)
159 {
160 	struct bztzsc_softc *bsc = device_private(self);
161 	struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x;
162 	struct zbus_args  *zap;
163 	extern u_long scsi_nosync;
164 	extern int shift_nosync;
165 	extern int ncr53c9x_debug;
166 
167 	/*
168 	 * Set up the glue for MI code early; we use some of it here.
169 	 */
170 	sc->sc_dev = self;
171 	sc->sc_glue = &bztzsc_glue;
172 
173 	/*
174 	 * Save the regs
175 	 */
176 	zap = aux;
177 	bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff00];
178 	bsc->sc_dmabase = &bsc->sc_reg[0xf0];
179 
180 	sc->sc_freq = 40;		/* Clocked at 40 MHz */
181 
182 	aprint_normal(": address %p", bsc->sc_reg);
183 
184 	sc->sc_id = 7;
185 
186 	/*
187 	 * It is necessary to try to load the 2nd config register here,
188 	 * to find out what rev the FAS chip is, else the ncr53c9x_reset
189 	 * will not set up the defaults correctly.
190 	 */
191 	sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
192 	sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
193 	sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
194 	sc->sc_rev = NCR_VARIANT_FAS216;
195 
196 	/*
197 	 * This is the value used to start sync negotiations
198 	 * Note that the NCR register "SYNCTP" is programmed
199 	 * in "clocks per byte", and has a minimum value of 4.
200 	 * The SCSI period used in negotiation is one-fourth
201 	 * of the time (in nanoseconds) needed to transfer one byte.
202 	 * Since the chip's clock is given in MHz, we have the following
203 	 * formula: 4 * period = (1000 / freq) * 4
204 	 */
205 	sc->sc_minsync = 1000 / sc->sc_freq;
206 
207 	/*
208 	 * get flags from -I argument and set cf_flags.
209 	 * NOTE: low 8 bits are to disable disconnect, and the next
210 	 *       8 bits are to disable sync.
211 	 */
212 	device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync)
213 	    & 0xffff;
214 	shift_nosync += 16;
215 
216 	/* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
217 	ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
218 	shift_nosync += 16;
219 
220 #if 1
221 	if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
222 		sc->sc_minsync = 0;
223 #endif
224 
225 	/* Really no limit, but since we want to fit into the TCR... */
226 	sc->sc_maxxfer = 64 * 1024;
227 
228 	bsc->sc_reg[0xe0] = BZTZSC_PB_LED;	/* Turn LED off */
229 
230 	/*
231 	 * Configure interrupts.
232 	 */
233 	bsc->sc_isr.isr_intr = ncr53c9x_intr;
234 	bsc->sc_isr.isr_arg  = sc;
235 	bsc->sc_isr.isr_ipl  = 2;
236 	add_isr(&bsc->sc_isr);
237 
238 	/*
239 	 * Now try to attach all the sub-devices
240 	 */
241 	sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
242 	sc->sc_adapter.adapt_minphys = minphys;
243 	ncr53c9x_attach(sc);
244 }
245 
246 /*
247  * Glue functions.
248  */
249 
250 uint8_t
251 bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg)
252 {
253 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
254 
255 	return bsc->sc_reg[reg * 4];
256 }
257 
258 void
259 bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
260 {
261 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
262 	uint8_t v = val;
263 
264 	bsc->sc_reg[reg * 4] = v;
265 #ifdef DEBUG
266 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
267   reg == NCR_CMD/* && bsc->sc_active*/) {
268   bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v;
269 /*  printf(" cmd %x", v);*/
270 }
271 #endif
272 }
273 
274 int
275 bztzsc_dma_isintr(struct ncr53c9x_softc *sc)
276 {
277 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
278 
279 	if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
280 		return 0;
281 
282 	if (sc->sc_state == NCR_CONNECTED)
283 		bsc->sc_reg[0xe0] = 0;			/* Turn LED on */
284 	else
285 		bsc->sc_reg[0xe0] = BZTZSC_PB_LED;	/* Turn LED off */
286 
287 #ifdef DEBUG
288 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) {
289   bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4];
290   bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4];
291   bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active;
292   bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127;
293 }
294 #endif
295 	return 1;
296 }
297 
298 void
299 bztzsc_dma_reset(struct ncr53c9x_softc *sc)
300 {
301 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
302 
303 	bsc->sc_active = 0;
304 }
305 
306 int
307 bztzsc_dma_intr(struct ncr53c9x_softc *sc)
308 {
309 	register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
310 	register int	cnt;
311 
312 	NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ",
313 	    bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
314 	    bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
315 	if (bsc->sc_active == 0) {
316 		printf("bztzsc_intr--inactive DMA\n");
317 		return -1;
318 	}
319 
320 	/* update sc_dmaaddr and sc_pdmalen */
321 	cnt = bsc->sc_reg[NCR_TCL * 4];
322 	cnt += bsc->sc_reg[NCR_TCM * 4] << 8;
323 	cnt += bsc->sc_reg[NCR_TCH * 4] << 16;
324 	if (!bsc->sc_datain) {
325 		cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
326 		bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
327 	}
328 	cnt = bsc->sc_dmasize - cnt;	/* number of bytes transferred */
329 	NCR_DMA(("DMA xferred %d\n", cnt));
330 	if (bsc->sc_xfr_align) {
331 		memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt);
332 		bsc->sc_xfr_align = 0;
333 	}
334 	*bsc->sc_dmaaddr += cnt;
335 	*bsc->sc_pdmalen -= cnt;
336 	bsc->sc_active = 0;
337 	return 0;
338 }
339 
340 int
341 bztzsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
342                  int datain, size_t *dmasize)
343 {
344 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
345 	paddr_t pa;
346 	uint8_t *ptr;
347 	size_t xfer;
348 
349 	bsc->sc_dmaaddr = addr;
350 	bsc->sc_pdmalen = len;
351 	bsc->sc_datain = datain;
352 	bsc->sc_dmasize = *dmasize;
353 	/*
354 	 * DMA can be nasty for high-speed serial input, so limit the
355 	 * size of this DMA operation if the serial port is running at
356 	 * a high speed (higher than 19200 for now - should be adjusted
357 	 * based on CPU type and speed?).
358 	 * XXX - add serial speed check XXX
359 	 */
360 	if (ser_open_speed > 19200 && bztzsc_max_dma != 0 &&
361 	    bsc->sc_dmasize > bztzsc_max_dma)
362 		bsc->sc_dmasize = bztzsc_max_dma;
363 	ptr = *addr;			/* Kernel virtual address */
364 	pa = kvtop(ptr);		/* Physical address of DMA */
365 	xfer = uimin(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
366 	bsc->sc_xfr_align = 0;
367 	/*
368 	 * If output and unaligned, stuff odd byte into FIFO
369 	 */
370 	if (datain == 0 && (int)ptr & 1) {
371 		NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n"));
372 		pa++;
373 		xfer--;			/* XXXX CHECK THIS !!!! XXXX */
374 		bsc->sc_reg[NCR_FIFO * 4] = *ptr++;
375 	}
376 	/*
377 	 * If unaligned address, read unaligned bytes into alignment buffer
378 	 */
379 	else if ((int)ptr & 1) {
380 		pa = kvtop((void *)&bsc->sc_alignbuf);
381 		xfer = bsc->sc_dmasize = uimin(xfer, sizeof(bsc->sc_alignbuf));
382 		NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer));
383 		bsc->sc_xfr_align = 1;
384 	}
385 ++bztzsc_cnt_dma;		/* number of DMA operations */
386 
387 	while (xfer < bsc->sc_dmasize) {
388 		if ((pa + xfer) != kvtop(*addr + xfer))
389 			break;
390 		if ((bsc->sc_dmasize - xfer) < PAGE_SIZE)
391 			xfer = bsc->sc_dmasize;
392 		else
393 			xfer += PAGE_SIZE;
394 ++bztzsc_cnt_dma3;
395 	}
396 if (xfer != *len)
397   ++bztzsc_cnt_dma2;
398 
399 	bsc->sc_dmasize = xfer;
400 	*dmasize = bsc->sc_dmasize;
401 	bsc->sc_pa = pa;
402 #if defined(M68040) || defined(M68060)
403 	if (mmutype == MMU_68040) {
404 		if (bsc->sc_xfr_align) {
405 			dma_cachectl(bsc->sc_alignbuf,
406 			    sizeof(bsc->sc_alignbuf));
407 		}
408 		else
409 			dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize);
410 	}
411 #endif
412 
413 	pa >>= 1;
414 	if (!bsc->sc_datain)
415 		pa |= 0x80000000;
416 	bsc->sc_dmabase[12] = (uint8_t)(pa);
417 	bsc->sc_dmabase[8] = (uint8_t)(pa >> 8);
418 	bsc->sc_dmabase[4] = (uint8_t)(pa >> 16);
419 	bsc->sc_dmabase[0] = (uint8_t)(pa >> 24);
420 	bsc->sc_active = 1;
421 	return 0;
422 }
423 
424 void
425 bztzsc_dma_go(struct ncr53c9x_softc *sc)
426 {
427 }
428 
429 void
430 bztzsc_dma_stop(struct ncr53c9x_softc *sc)
431 {
432 }
433 
434 int
435 bztzsc_dma_isactive(struct ncr53c9x_softc *sc)
436 {
437 	struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc;
438 
439 	return bsc->sc_active;
440 }
441 
442 #ifdef DEBUG
443 void
444 bztzsc_dump(void)
445 {
446 	int i;
447 
448 	i = bztzsc_trace_ptr;
449 	printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr);
450 	do {
451 		if (bztzsc_trace[i].hardbits == 0) {
452 			i = (i + 1) & 127;
453 			continue;
454 		}
455 		printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits,
456 		    bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy);
457 		if (bztzsc_trace[i].status & NCRSTAT_INT)
458 			printf("NCRINT/");
459 		if (bztzsc_trace[i].status & NCRSTAT_TC)
460 			printf("NCRTC/");
461 		switch(bztzsc_trace[i].status & NCRSTAT_PHASE) {
462 		case 0:
463 			printf("dataout"); break;
464 		case 1:
465 			printf("datain"); break;
466 		case 2:
467 			printf("cmdout"); break;
468 		case 3:
469 			printf("status"); break;
470 		case 6:
471 			printf("msgout"); break;
472 		case 7:
473 			printf("msgin"); break;
474 		default:
475 			printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE);
476 		}
477 		printf(") ");
478 		i = (i + 1) & 127;
479 	} while (i != bztzsc_trace_ptr);
480 	printf("\n");
481 }
482 #endif
483