1 /* $NetBSD: bztzsc.c,v 1.15 2001/04/25 17:53:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1996 Ignatios Souvatzis 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product contains software written by Ignatios Souvatzis and 20 * Michael L. Hitch for the NetBSD project. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 /* 40 * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <machine/cpu.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <amiga/amiga/isr.h> 68 #include <amiga/dev/bztzscvar.h> 69 #include <amiga/dev/zbusvar.h> 70 71 void bztzscattach __P((struct device *, struct device *, void *)); 72 int bztzscmatch __P((struct device *, struct cfdata *, void *)); 73 74 /* Linkup to the rest of the kernel */ 75 struct cfattach bztzsc_ca = { 76 sizeof(struct bztzsc_softc), bztzscmatch, bztzscattach 77 }; 78 79 /* 80 * Functions and the switch for the MI code. 81 */ 82 u_char bztzsc_read_reg __P((struct ncr53c9x_softc *, int)); 83 void bztzsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 84 int bztzsc_dma_isintr __P((struct ncr53c9x_softc *)); 85 void bztzsc_dma_reset __P((struct ncr53c9x_softc *)); 86 int bztzsc_dma_intr __P((struct ncr53c9x_softc *)); 87 int bztzsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 88 size_t *, int, size_t *)); 89 void bztzsc_dma_go __P((struct ncr53c9x_softc *)); 90 void bztzsc_dma_stop __P((struct ncr53c9x_softc *)); 91 int bztzsc_dma_isactive __P((struct ncr53c9x_softc *)); 92 93 struct ncr53c9x_glue bztzsc_glue = { 94 bztzsc_read_reg, 95 bztzsc_write_reg, 96 bztzsc_dma_isintr, 97 bztzsc_dma_reset, 98 bztzsc_dma_intr, 99 bztzsc_dma_setup, 100 bztzsc_dma_go, 101 bztzsc_dma_stop, 102 bztzsc_dma_isactive, 103 0, 104 }; 105 106 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 107 u_long bztzsc_max_dma = 1024; 108 extern int ser_open_speed; 109 110 u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */ 111 u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */ 112 u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 113 u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */ 114 115 #ifdef DEBUG 116 struct { 117 u_char hardbits; 118 u_char status; 119 u_char xx; 120 u_char yy; 121 } bztzsc_trace[128]; 122 int bztzsc_trace_ptr = 0; 123 int bztzsc_trace_enable = 1; 124 void bztzsc_dump __P((void)); 125 #endif 126 127 /* 128 * if we are a Phase5 Blizzard 2060 SCSI 129 */ 130 int 131 bztzscmatch(parent, cf, aux) 132 struct device *parent; 133 struct cfdata *cf; 134 void *aux; 135 { 136 struct zbus_args *zap; 137 volatile u_char *regs; 138 139 zap = aux; 140 if (zap->manid != 0x2140 || zap->prodid != 24) 141 return(0); 142 regs = &((volatile u_char *)zap->va)[0x1ff00]; 143 if (badaddr((caddr_t)regs)) 144 return(0); 145 regs[NCR_CFG1 * 4] = 0; 146 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 147 delay(5); 148 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 149 return(0); 150 return(1); 151 } 152 153 /* 154 * Attach this instance, and then all the sub-devices 155 */ 156 void 157 bztzscattach(parent, self, aux) 158 struct device *parent, *self; 159 void *aux; 160 { 161 struct bztzsc_softc *bsc = (void *)self; 162 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 163 struct zbus_args *zap; 164 extern u_long scsi_nosync; 165 extern int shift_nosync; 166 extern int ncr53c9x_debug; 167 168 /* 169 * Set up the glue for MI code early; we use some of it here. 170 */ 171 sc->sc_glue = &bztzsc_glue; 172 173 /* 174 * Save the regs 175 */ 176 zap = aux; 177 bsc->sc_reg = &((volatile u_char *)zap->va)[0x1ff00]; 178 bsc->sc_dmabase = &bsc->sc_reg[0xf0]; 179 180 sc->sc_freq = 40; /* Clocked at 40Mhz */ 181 182 printf(": address %p", bsc->sc_reg); 183 184 sc->sc_id = 7; 185 186 /* 187 * It is necessary to try to load the 2nd config register here, 188 * to find out what rev the FAS chip is, else the ncr53c9x_reset 189 * will not set up the defaults correctly. 190 */ 191 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 192 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 193 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 194 sc->sc_rev = NCR_VARIANT_FAS216; 195 196 /* 197 * This is the value used to start sync negotiations 198 * Note that the NCR register "SYNCTP" is programmed 199 * in "clocks per byte", and has a minimum value of 4. 200 * The SCSI period used in negotiation is one-fourth 201 * of the time (in nanoseconds) needed to transfer one byte. 202 * Since the chip's clock is given in MHz, we have the following 203 * formula: 4 * period = (1000 / freq) * 4 204 */ 205 sc->sc_minsync = 1000 / sc->sc_freq; 206 207 /* 208 * get flags from -I argument and set cf_flags. 209 * NOTE: low 8 bits are to disable disconnect, and the next 210 * 8 bits are to disable sync. 211 */ 212 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 213 & 0xffff; 214 shift_nosync += 16; 215 216 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 217 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 218 shift_nosync += 16; 219 220 #if 1 221 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 222 sc->sc_minsync = 0; 223 #endif 224 225 /* Really no limit, but since we want to fit into the TCR... */ 226 sc->sc_maxxfer = 64 * 1024; 227 228 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 229 230 /* 231 * Configure interrupts. 232 */ 233 bsc->sc_isr.isr_intr = ncr53c9x_intr; 234 bsc->sc_isr.isr_arg = sc; 235 bsc->sc_isr.isr_ipl = 2; 236 add_isr(&bsc->sc_isr); 237 238 /* 239 * Now try to attach all the sub-devices 240 */ 241 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 242 sc->sc_adapter.adapt_minphys = minphys; 243 ncr53c9x_attach(sc); 244 } 245 246 /* 247 * Glue functions. 248 */ 249 250 u_char 251 bztzsc_read_reg(sc, reg) 252 struct ncr53c9x_softc *sc; 253 int reg; 254 { 255 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 256 257 return bsc->sc_reg[reg * 4]; 258 } 259 260 void 261 bztzsc_write_reg(sc, reg, val) 262 struct ncr53c9x_softc *sc; 263 int reg; 264 u_char val; 265 { 266 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 267 u_char v = val; 268 269 bsc->sc_reg[reg * 4] = v; 270 #ifdef DEBUG 271 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 272 reg == NCR_CMD/* && bsc->sc_active*/) { 273 bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v; 274 /* printf(" cmd %x", v);*/ 275 } 276 #endif 277 } 278 279 int 280 bztzsc_dma_isintr(sc) 281 struct ncr53c9x_softc *sc; 282 { 283 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 284 285 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 286 return 0; 287 288 if (sc->sc_state == NCR_CONNECTED) 289 bsc->sc_reg[0xe0] = 0; /* Turn LED on */ 290 else 291 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 292 293 #ifdef DEBUG 294 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) { 295 bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 296 bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 297 bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active; 298 bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127; 299 } 300 #endif 301 return 1; 302 } 303 304 void 305 bztzsc_dma_reset(sc) 306 struct ncr53c9x_softc *sc; 307 { 308 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 309 310 bsc->sc_active = 0; 311 } 312 313 int 314 bztzsc_dma_intr(sc) 315 struct ncr53c9x_softc *sc; 316 { 317 register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 318 register int cnt; 319 320 NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 321 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 322 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 323 if (bsc->sc_active == 0) { 324 printf("bztzsc_intr--inactive DMA\n"); 325 return -1; 326 } 327 328 /* update sc_dmaaddr and sc_pdmalen */ 329 cnt = bsc->sc_reg[NCR_TCL * 4]; 330 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 331 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 332 if (!bsc->sc_datain) { 333 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 334 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 335 } 336 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 337 NCR_DMA(("DMA xferred %d\n", cnt)); 338 if (bsc->sc_xfr_align) { 339 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 340 bsc->sc_xfr_align = 0; 341 } 342 *bsc->sc_dmaaddr += cnt; 343 *bsc->sc_pdmalen -= cnt; 344 bsc->sc_active = 0; 345 return 0; 346 } 347 348 int 349 bztzsc_dma_setup(sc, addr, len, datain, dmasize) 350 struct ncr53c9x_softc *sc; 351 caddr_t *addr; 352 size_t *len; 353 int datain; 354 size_t *dmasize; 355 { 356 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 357 paddr_t pa; 358 u_char *ptr; 359 size_t xfer; 360 361 bsc->sc_dmaaddr = addr; 362 bsc->sc_pdmalen = len; 363 bsc->sc_datain = datain; 364 bsc->sc_dmasize = *dmasize; 365 /* 366 * DMA can be nasty for high-speed serial input, so limit the 367 * size of this DMA operation if the serial port is running at 368 * a high speed (higher than 19200 for now - should be adjusted 369 * based on cpu type and speed?). 370 * XXX - add serial speed check XXX 371 */ 372 if (ser_open_speed > 19200 && bztzsc_max_dma != 0 && 373 bsc->sc_dmasize > bztzsc_max_dma) 374 bsc->sc_dmasize = bztzsc_max_dma; 375 ptr = *addr; /* Kernel virtual address */ 376 pa = kvtop(ptr); /* Physical address of DMA */ 377 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 378 bsc->sc_xfr_align = 0; 379 /* 380 * If output and unaligned, stuff odd byte into FIFO 381 */ 382 if (datain == 0 && (int)ptr & 1) { 383 NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n")); 384 pa++; 385 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 386 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 387 } 388 /* 389 * If unaligned address, read unaligned bytes into alignment buffer 390 */ 391 else if ((int)ptr & 1) { 392 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 393 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 394 NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer)); 395 bsc->sc_xfr_align = 1; 396 } 397 ++bztzsc_cnt_dma; /* number of DMA operations */ 398 399 while (xfer < bsc->sc_dmasize) { 400 if ((pa + xfer) != kvtop(*addr + xfer)) 401 break; 402 if ((bsc->sc_dmasize - xfer) < NBPG) 403 xfer = bsc->sc_dmasize; 404 else 405 xfer += NBPG; 406 ++bztzsc_cnt_dma3; 407 } 408 if (xfer != *len) 409 ++bztzsc_cnt_dma2; 410 411 bsc->sc_dmasize = xfer; 412 *dmasize = bsc->sc_dmasize; 413 bsc->sc_pa = pa; 414 #if defined(M68040) || defined(M68060) 415 if (mmutype == MMU_68040) { 416 if (bsc->sc_xfr_align) { 417 dma_cachectl(bsc->sc_alignbuf, 418 sizeof(bsc->sc_alignbuf)); 419 } 420 else 421 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 422 } 423 #endif 424 425 pa >>= 1; 426 if (!bsc->sc_datain) 427 pa |= 0x80000000; 428 bsc->sc_dmabase[12] = (u_int8_t)(pa); 429 bsc->sc_dmabase[8] = (u_int8_t)(pa >> 8); 430 bsc->sc_dmabase[4] = (u_int8_t)(pa >> 16); 431 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 432 bsc->sc_active = 1; 433 return 0; 434 } 435 436 void 437 bztzsc_dma_go(sc) 438 struct ncr53c9x_softc *sc; 439 { 440 } 441 442 void 443 bztzsc_dma_stop(sc) 444 struct ncr53c9x_softc *sc; 445 { 446 } 447 448 int 449 bztzsc_dma_isactive(sc) 450 struct ncr53c9x_softc *sc; 451 { 452 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 453 454 return bsc->sc_active; 455 } 456 457 #ifdef DEBUG 458 void 459 bztzsc_dump() 460 { 461 int i; 462 463 i = bztzsc_trace_ptr; 464 printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr); 465 do { 466 if (bztzsc_trace[i].hardbits == 0) { 467 i = (i + 1) & 127; 468 continue; 469 } 470 printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits, 471 bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy); 472 if (bztzsc_trace[i].status & NCRSTAT_INT) 473 printf("NCRINT/"); 474 if (bztzsc_trace[i].status & NCRSTAT_TC) 475 printf("NCRTC/"); 476 switch(bztzsc_trace[i].status & NCRSTAT_PHASE) { 477 case 0: 478 printf("dataout"); break; 479 case 1: 480 printf("datain"); break; 481 case 2: 482 printf("cmdout"); break; 483 case 3: 484 printf("status"); break; 485 case 6: 486 printf("msgout"); break; 487 case 7: 488 printf("msgin"); break; 489 default: 490 printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE); 491 } 492 printf(") "); 493 i = (i + 1) & 127; 494 } while (i != bztzsc_trace_ptr); 495 printf("\n"); 496 } 497 #endif 498