1 /* $NetBSD: bztzsc.c,v 1.31 2008/04/13 04:55:52 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1996 Ignatios Souvatzis 6 * Copyright (c) 1982, 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product contains software written by Ignatios Souvatzis and 20 * Michael L. Hitch for the NetBSD project. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 /* 40 * Initial amiga Blizzard 2060 driver by Ingatios Souvatzis. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: bztzsc.c,v 1.31 2008/04/13 04:55:52 tsutsui Exp $"); 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 #include <sys/queue.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 #include <dev/scsipi/scsi_message.h> 65 66 #include <machine/cpu.h> 67 #include <machine/param.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <amiga/amiga/isr.h> 73 #include <amiga/dev/bztzscvar.h> 74 #include <amiga/dev/zbusvar.h> 75 76 #ifdef __powerpc__ 77 #define badaddr(a) badaddr_read(a, 2, NULL) 78 #endif 79 80 int bztzscmatch(device_t, cfdata_t, void *); 81 void bztzscattach(device_t, device_t, void *); 82 83 /* Linkup to the rest of the kernel */ 84 CFATTACH_DECL_NEW(bztzsc, sizeof(struct bztzsc_softc), 85 bztzscmatch, bztzscattach, NULL, NULL); 86 87 /* 88 * Functions and the switch for the MI code. 89 */ 90 uint8_t bztzsc_read_reg(struct ncr53c9x_softc *, int); 91 void bztzsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 92 int bztzsc_dma_isintr(struct ncr53c9x_softc *); 93 void bztzsc_dma_reset(struct ncr53c9x_softc *); 94 int bztzsc_dma_intr(struct ncr53c9x_softc *); 95 int bztzsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 96 size_t *, int, size_t *); 97 void bztzsc_dma_go(struct ncr53c9x_softc *); 98 void bztzsc_dma_stop(struct ncr53c9x_softc *); 99 int bztzsc_dma_isactive(struct ncr53c9x_softc *); 100 101 struct ncr53c9x_glue bztzsc_glue = { 102 bztzsc_read_reg, 103 bztzsc_write_reg, 104 bztzsc_dma_isintr, 105 bztzsc_dma_reset, 106 bztzsc_dma_intr, 107 bztzsc_dma_setup, 108 bztzsc_dma_go, 109 bztzsc_dma_stop, 110 bztzsc_dma_isactive, 111 NULL, 112 }; 113 114 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 115 u_long bztzsc_max_dma = 1024; 116 extern int ser_open_speed; 117 118 u_long bztzsc_cnt_pio = 0; /* number of PIO transfers */ 119 u_long bztzsc_cnt_dma = 0; /* number of DMA transfers */ 120 u_long bztzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 121 u_long bztzsc_cnt_dma3 = 0; /* number of pages combined */ 122 123 #ifdef DEBUG 124 struct { 125 uint8_t hardbits; 126 uint8_t status; 127 uint8_t xx; 128 uint8_t yy; 129 } bztzsc_trace[128]; 130 int bztzsc_trace_ptr = 0; 131 int bztzsc_trace_enable = 1; 132 void bztzsc_dump(void); 133 #endif 134 135 /* 136 * if we are a Phase5 Blizzard 2060 SCSI 137 */ 138 int 139 bztzscmatch(device_t parent, cfdata_t cf, void *aux) 140 { 141 struct zbus_args *zap; 142 volatile uint8_t *regs; 143 144 zap = aux; 145 if (zap->manid != 0x2140 || zap->prodid != 24) 146 return 0; 147 regs = &((volatile uint8_t *)zap->va)[0x1ff00]; 148 if (badaddr((void *)__UNVOLATILE(regs))) 149 return 0; 150 regs[NCR_CFG1 * 4] = 0; 151 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 152 delay(5); 153 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 154 return 0; 155 return 1; 156 } 157 158 /* 159 * Attach this instance, and then all the sub-devices 160 */ 161 void 162 bztzscattach(device_t parent, device_t self, void *aux) 163 { 164 struct bztzsc_softc *bsc = device_private(self); 165 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 166 struct zbus_args *zap; 167 extern u_long scsi_nosync; 168 extern int shift_nosync; 169 extern int ncr53c9x_debug; 170 171 /* 172 * Set up the glue for MI code early; we use some of it here. 173 */ 174 sc->sc_dev = self; 175 sc->sc_glue = &bztzsc_glue; 176 177 /* 178 * Save the regs 179 */ 180 zap = aux; 181 bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x1ff00]; 182 bsc->sc_dmabase = &bsc->sc_reg[0xf0]; 183 184 sc->sc_freq = 40; /* Clocked at 40 MHz */ 185 186 aprint_normal(": address %p", bsc->sc_reg); 187 188 sc->sc_id = 7; 189 190 /* 191 * It is necessary to try to load the 2nd config register here, 192 * to find out what rev the FAS chip is, else the ncr53c9x_reset 193 * will not set up the defaults correctly. 194 */ 195 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 196 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 197 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 198 sc->sc_rev = NCR_VARIANT_FAS216; 199 200 /* 201 * This is the value used to start sync negotiations 202 * Note that the NCR register "SYNCTP" is programmed 203 * in "clocks per byte", and has a minimum value of 4. 204 * The SCSI period used in negotiation is one-fourth 205 * of the time (in nanoseconds) needed to transfer one byte. 206 * Since the chip's clock is given in MHz, we have the following 207 * formula: 4 * period = (1000 / freq) * 4 208 */ 209 sc->sc_minsync = 1000 / sc->sc_freq; 210 211 /* 212 * get flags from -I argument and set cf_flags. 213 * NOTE: low 8 bits are to disable disconnect, and the next 214 * 8 bits are to disable sync. 215 */ 216 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 217 & 0xffff; 218 shift_nosync += 16; 219 220 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 221 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 222 shift_nosync += 16; 223 224 #if 1 225 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 226 sc->sc_minsync = 0; 227 #endif 228 229 /* Really no limit, but since we want to fit into the TCR... */ 230 sc->sc_maxxfer = 64 * 1024; 231 232 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 233 234 /* 235 * Configure interrupts. 236 */ 237 bsc->sc_isr.isr_intr = ncr53c9x_intr; 238 bsc->sc_isr.isr_arg = sc; 239 bsc->sc_isr.isr_ipl = 2; 240 add_isr(&bsc->sc_isr); 241 242 /* 243 * Now try to attach all the sub-devices 244 */ 245 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 246 sc->sc_adapter.adapt_minphys = minphys; 247 ncr53c9x_attach(sc); 248 } 249 250 /* 251 * Glue functions. 252 */ 253 254 uint8_t 255 bztzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 256 { 257 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 258 259 return bsc->sc_reg[reg * 4]; 260 } 261 262 void 263 bztzsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 264 { 265 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 266 uint8_t v = val; 267 268 bsc->sc_reg[reg * 4] = v; 269 #ifdef DEBUG 270 if (bztzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 271 reg == NCR_CMD/* && bsc->sc_active*/) { 272 bztzsc_trace[(bztzsc_trace_ptr - 1) & 127].yy = v; 273 /* printf(" cmd %x", v);*/ 274 } 275 #endif 276 } 277 278 int 279 bztzsc_dma_isintr(struct ncr53c9x_softc *sc) 280 { 281 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 282 283 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 284 return 0; 285 286 if (sc->sc_state == NCR_CONNECTED) 287 bsc->sc_reg[0xe0] = 0; /* Turn LED on */ 288 else 289 bsc->sc_reg[0xe0] = BZTZSC_PB_LED; /* Turn LED off */ 290 291 #ifdef DEBUG 292 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bztzsc_trace_enable) { 293 bztzsc_trace[bztzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 294 bztzsc_trace[bztzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 295 bztzsc_trace[bztzsc_trace_ptr].yy = bsc->sc_active; 296 bztzsc_trace_ptr = (bztzsc_trace_ptr + 1) & 127; 297 } 298 #endif 299 return 1; 300 } 301 302 void 303 bztzsc_dma_reset(struct ncr53c9x_softc *sc) 304 { 305 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 306 307 bsc->sc_active = 0; 308 } 309 310 int 311 bztzsc_dma_intr(struct ncr53c9x_softc *sc) 312 { 313 register struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 314 register int cnt; 315 316 NCR_DMA(("bztzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 317 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 318 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 319 if (bsc->sc_active == 0) { 320 printf("bztzsc_intr--inactive DMA\n"); 321 return -1; 322 } 323 324 /* update sc_dmaaddr and sc_pdmalen */ 325 cnt = bsc->sc_reg[NCR_TCL * 4]; 326 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 327 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 328 if (!bsc->sc_datain) { 329 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 330 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 331 } 332 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 333 NCR_DMA(("DMA xferred %d\n", cnt)); 334 if (bsc->sc_xfr_align) { 335 memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt); 336 bsc->sc_xfr_align = 0; 337 } 338 *bsc->sc_dmaaddr += cnt; 339 *bsc->sc_pdmalen -= cnt; 340 bsc->sc_active = 0; 341 return 0; 342 } 343 344 int 345 bztzsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 346 int datain, size_t *dmasize) 347 { 348 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 349 paddr_t pa; 350 uint8_t *ptr; 351 size_t xfer; 352 353 bsc->sc_dmaaddr = addr; 354 bsc->sc_pdmalen = len; 355 bsc->sc_datain = datain; 356 bsc->sc_dmasize = *dmasize; 357 /* 358 * DMA can be nasty for high-speed serial input, so limit the 359 * size of this DMA operation if the serial port is running at 360 * a high speed (higher than 19200 for now - should be adjusted 361 * based on CPU type and speed?). 362 * XXX - add serial speed check XXX 363 */ 364 if (ser_open_speed > 19200 && bztzsc_max_dma != 0 && 365 bsc->sc_dmasize > bztzsc_max_dma) 366 bsc->sc_dmasize = bztzsc_max_dma; 367 ptr = *addr; /* Kernel virtual address */ 368 pa = kvtop(ptr); /* Physical address of DMA */ 369 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 370 bsc->sc_xfr_align = 0; 371 /* 372 * If output and unaligned, stuff odd byte into FIFO 373 */ 374 if (datain == 0 && (int)ptr & 1) { 375 NCR_DMA(("bztzsc_dma_setup: align byte written to fifo\n")); 376 pa++; 377 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 378 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 379 } 380 /* 381 * If unaligned address, read unaligned bytes into alignment buffer 382 */ 383 else if ((int)ptr & 1) { 384 pa = kvtop((void *)&bsc->sc_alignbuf); 385 xfer = bsc->sc_dmasize = min(xfer, sizeof(bsc->sc_alignbuf)); 386 NCR_DMA(("bztzsc_dma_setup: align read by %d bytes\n", xfer)); 387 bsc->sc_xfr_align = 1; 388 } 389 ++bztzsc_cnt_dma; /* number of DMA operations */ 390 391 while (xfer < bsc->sc_dmasize) { 392 if ((pa + xfer) != kvtop(*addr + xfer)) 393 break; 394 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 395 xfer = bsc->sc_dmasize; 396 else 397 xfer += PAGE_SIZE; 398 ++bztzsc_cnt_dma3; 399 } 400 if (xfer != *len) 401 ++bztzsc_cnt_dma2; 402 403 bsc->sc_dmasize = xfer; 404 *dmasize = bsc->sc_dmasize; 405 bsc->sc_pa = pa; 406 #if defined(M68040) || defined(M68060) 407 if (mmutype == MMU_68040) { 408 if (bsc->sc_xfr_align) { 409 dma_cachectl(bsc->sc_alignbuf, 410 sizeof(bsc->sc_alignbuf)); 411 } 412 else 413 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 414 } 415 #endif 416 417 pa >>= 1; 418 if (!bsc->sc_datain) 419 pa |= 0x80000000; 420 bsc->sc_dmabase[12] = (uint8_t)(pa); 421 bsc->sc_dmabase[8] = (uint8_t)(pa >> 8); 422 bsc->sc_dmabase[4] = (uint8_t)(pa >> 16); 423 bsc->sc_dmabase[0] = (uint8_t)(pa >> 24); 424 bsc->sc_active = 1; 425 return 0; 426 } 427 428 void 429 bztzsc_dma_go(struct ncr53c9x_softc *sc) 430 { 431 } 432 433 void 434 bztzsc_dma_stop(struct ncr53c9x_softc *sc) 435 { 436 } 437 438 int 439 bztzsc_dma_isactive(struct ncr53c9x_softc *sc) 440 { 441 struct bztzsc_softc *bsc = (struct bztzsc_softc *)sc; 442 443 return bsc->sc_active; 444 } 445 446 #ifdef DEBUG 447 void 448 bztzsc_dump(void) 449 { 450 int i; 451 452 i = bztzsc_trace_ptr; 453 printf("bztzsc_trace dump: ptr %x\n", bztzsc_trace_ptr); 454 do { 455 if (bztzsc_trace[i].hardbits == 0) { 456 i = (i + 1) & 127; 457 continue; 458 } 459 printf("%02x%02x%02x%02x(", bztzsc_trace[i].hardbits, 460 bztzsc_trace[i].status, bztzsc_trace[i].xx, bztzsc_trace[i].yy); 461 if (bztzsc_trace[i].status & NCRSTAT_INT) 462 printf("NCRINT/"); 463 if (bztzsc_trace[i].status & NCRSTAT_TC) 464 printf("NCRTC/"); 465 switch(bztzsc_trace[i].status & NCRSTAT_PHASE) { 466 case 0: 467 printf("dataout"); break; 468 case 1: 469 printf("datain"); break; 470 case 2: 471 printf("cmdout"); break; 472 case 3: 473 printf("status"); break; 474 case 6: 475 printf("msgout"); break; 476 case 7: 477 printf("msgin"); break; 478 default: 479 printf("phase%d?", bztzsc_trace[i].status & NCRSTAT_PHASE); 480 } 481 printf(") "); 482 i = (i + 1) & 127; 483 } while (i != bztzsc_trace_ptr); 484 printf("\n"); 485 } 486 #endif 487