1 /* $NetBSD: bzsc.c,v 1.30 2002/01/28 09:56:52 aymeric Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bzsc.c,v 1.30 2002/01/28 09:56:52 aymeric Exp $"); 41 42 /* 43 * Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to 44 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 #include <sys/queue.h> 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 #include <dev/scsipi/scsi_message.h> 63 64 #include <machine/cpu.h> 65 #include <machine/param.h> 66 67 #include <dev/ic/ncr53c9xreg.h> 68 #include <dev/ic/ncr53c9xvar.h> 69 70 #include <amiga/amiga/isr.h> 71 #include <amiga/dev/bzscvar.h> 72 #include <amiga/dev/zbusvar.h> 73 74 void bzscattach(struct device *, struct device *, void *); 75 int bzscmatch(struct device *, struct cfdata *, void *); 76 77 /* Linkup to the rest of the kernel */ 78 struct cfattach bzsc_ca = { 79 sizeof(struct bzsc_softc), bzscmatch, bzscattach 80 }; 81 82 /* 83 * Functions and the switch for the MI code. 84 */ 85 u_char bzsc_read_reg(struct ncr53c9x_softc *, int); 86 void bzsc_write_reg(struct ncr53c9x_softc *, int, u_char); 87 int bzsc_dma_isintr(struct ncr53c9x_softc *); 88 void bzsc_dma_reset(struct ncr53c9x_softc *); 89 int bzsc_dma_intr(struct ncr53c9x_softc *); 90 int bzsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 91 size_t *, int, size_t *); 92 void bzsc_dma_go(struct ncr53c9x_softc *); 93 void bzsc_dma_stop(struct ncr53c9x_softc *); 94 int bzsc_dma_isactive(struct ncr53c9x_softc *); 95 96 struct ncr53c9x_glue bzsc_glue = { 97 bzsc_read_reg, 98 bzsc_write_reg, 99 bzsc_dma_isintr, 100 bzsc_dma_reset, 101 bzsc_dma_intr, 102 bzsc_dma_setup, 103 bzsc_dma_go, 104 bzsc_dma_stop, 105 bzsc_dma_isactive, 106 0, 107 }; 108 109 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 110 u_long bzsc_max_dma = 1024; 111 extern int ser_open_speed; 112 113 u_long bzsc_cnt_pio = 0; /* number of PIO transfers */ 114 u_long bzsc_cnt_dma = 0; /* number of DMA transfers */ 115 u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 116 u_long bzsc_cnt_dma3 = 0; /* number of pages combined */ 117 118 #ifdef DEBUG 119 struct { 120 u_char hardbits; 121 u_char status; 122 u_char xx; 123 u_char yy; 124 } bzsc_trace[128]; 125 int bzsc_trace_ptr = 0; 126 int bzsc_trace_enable = 1; 127 void bzsc_dump(void); 128 #endif 129 130 /* 131 * if we are a Phase5 Blizzard 1230 II 132 */ 133 int 134 bzscmatch(struct device *parent, struct cfdata *cf, void *aux) 135 { 136 struct zbus_args *zap; 137 volatile u_char *regs; 138 139 zap = aux; 140 if (zap->manid != 0x2140 || zap->prodid != 11) 141 return(0); /* It's not Blizzard 1230 */ 142 if (!is_a1200()) 143 return(0); /* And not A1200 */ 144 regs = &((volatile u_char *)zap->va)[0x10000]; 145 if (badaddr((caddr_t)regs)) 146 return(0); 147 regs[NCR_CFG1 * 2] = 0; 148 regs[NCR_CFG1 * 2] = NCRCFG1_PARENB | 7; 149 delay(5); 150 if (regs[NCR_CFG1 * 2] != (NCRCFG1_PARENB | 7)) 151 return(0); 152 return(1); 153 } 154 155 /* 156 * Attach this instance, and then all the sub-devices 157 */ 158 void 159 bzscattach(struct device *parent, struct device *self, void *aux) 160 { 161 struct bzsc_softc *bsc = (void *)self; 162 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 163 struct zbus_args *zap; 164 extern u_long scsi_nosync; 165 extern int shift_nosync; 166 extern int ncr53c9x_debug; 167 168 /* 169 * Set up the glue for MI code early; we use some of it here. 170 */ 171 sc->sc_glue = &bzsc_glue; 172 173 /* 174 * Save the regs 175 */ 176 zap = aux; 177 bsc->sc_reg = &((volatile u_char *)zap->va)[0x10000]; 178 bsc->sc_dmabase = &bsc->sc_reg[0x21]; 179 180 sc->sc_freq = 40; /* Clocked at 40Mhz */ 181 182 printf(": address %p", bsc->sc_reg); 183 184 sc->sc_id = 7; 185 186 /* 187 * It is necessary to try to load the 2nd config register here, 188 * to find out what rev the FAS chip is, else the ncr53c9x_reset 189 * will not set up the defaults correctly. 190 */ 191 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 192 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 193 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 194 sc->sc_rev = NCR_VARIANT_FAS216; 195 196 /* 197 * This is the value used to start sync negotiations 198 * Note that the NCR register "SYNCTP" is programmed 199 * in "clocks per byte", and has a minimum value of 4. 200 * The SCSI period used in negotiation is one-fourth 201 * of the time (in nanoseconds) needed to transfer one byte. 202 * Since the chip's clock is given in MHz, we have the following 203 * formula: 4 * period = (1000 / freq) * 4 204 */ 205 sc->sc_minsync = 1000 / sc->sc_freq; 206 207 /* 208 * get flags from -I argument and set cf_flags. 209 * NOTE: low 8 bits are to disable disconnect, and the next 210 * 8 bits are to disable sync. 211 */ 212 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 213 & 0xffff; 214 shift_nosync += 16; 215 216 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 217 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 218 shift_nosync += 16; 219 220 #if 1 221 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 222 sc->sc_minsync = 0; 223 #endif 224 225 /* Really no limit, but since we want to fit into the TCR... */ 226 sc->sc_maxxfer = 64 * 1024; 227 228 /* 229 * Configure interrupts. 230 */ 231 bsc->sc_isr.isr_intr = ncr53c9x_intr; 232 bsc->sc_isr.isr_arg = sc; 233 bsc->sc_isr.isr_ipl = 2; 234 add_isr(&bsc->sc_isr); 235 236 /* 237 * Now try to attach all the sub-devices 238 */ 239 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 240 sc->sc_adapter.adapt_minphys = minphys; 241 ncr53c9x_attach(sc); 242 } 243 244 /* 245 * Glue functions. 246 */ 247 248 u_char 249 bzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 250 { 251 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 252 253 return bsc->sc_reg[reg * 2]; 254 } 255 256 void 257 bzsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 258 { 259 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 260 u_char v = val; 261 262 bsc->sc_reg[reg * 2] = v; 263 #ifdef DEBUG 264 if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 265 reg == NCR_CMD/* && bsc->sc_active*/) { 266 bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v; 267 /* printf(" cmd %x", v);*/ 268 } 269 #endif 270 } 271 272 int 273 bzsc_dma_isintr(struct ncr53c9x_softc *sc) 274 { 275 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 276 277 if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0) 278 return 0; 279 280 #ifdef DEBUG 281 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzsc_trace_enable) { 282 bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2]; 283 bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2]; 284 bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active; 285 bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127; 286 } 287 #endif 288 return 1; 289 } 290 291 void 292 bzsc_dma_reset(struct ncr53c9x_softc *sc) 293 { 294 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 295 296 bsc->sc_active = 0; 297 } 298 299 int 300 bzsc_dma_intr(struct ncr53c9x_softc *sc) 301 { 302 register struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 303 register int cnt; 304 305 NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 306 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 307 bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF)); 308 if (bsc->sc_active == 0) { 309 printf("bzsc_intr--inactive DMA\n"); 310 return -1; 311 } 312 313 /* update sc_dmaaddr and sc_pdmalen */ 314 cnt = bsc->sc_reg[NCR_TCL * 2]; 315 cnt += bsc->sc_reg[NCR_TCM * 2] << 8; 316 cnt += bsc->sc_reg[NCR_TCH * 2] << 16; 317 if (!bsc->sc_datain) { 318 cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF; 319 bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH; 320 } 321 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 322 NCR_DMA(("DMA xferred %d\n", cnt)); 323 if (bsc->sc_xfr_align) { 324 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 325 bsc->sc_xfr_align = 0; 326 } 327 *bsc->sc_dmaaddr += cnt; 328 *bsc->sc_pdmalen -= cnt; 329 bsc->sc_active = 0; 330 return 0; 331 } 332 333 int 334 bzsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 335 int datain, size_t *dmasize) 336 { 337 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 338 paddr_t pa; 339 u_char *ptr; 340 size_t xfer; 341 342 bsc->sc_dmaaddr = addr; 343 bsc->sc_pdmalen = len; 344 bsc->sc_datain = datain; 345 bsc->sc_dmasize = *dmasize; 346 /* 347 * DMA can be nasty for high-speed serial input, so limit the 348 * size of this DMA operation if the serial port is running at 349 * a high speed (higher than 19200 for now - should be adjusted 350 * based on cpu type and speed?). 351 * XXX - add serial speed check XXX 352 */ 353 if (ser_open_speed > 19200 && bzsc_max_dma != 0 && 354 bsc->sc_dmasize > bzsc_max_dma) 355 bsc->sc_dmasize = bzsc_max_dma; 356 ptr = *addr; /* Kernel virtual address */ 357 pa = kvtop(ptr); /* Physical address of DMA */ 358 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 359 bsc->sc_xfr_align = 0; 360 /* 361 * If output and unaligned, stuff odd byte into FIFO 362 */ 363 if (datain == 0 && (int)ptr & 1) { 364 NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n")); 365 pa++; 366 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 367 bsc->sc_reg[NCR_FIFO * 2] = *ptr++; 368 } 369 /* 370 * If unaligned address, read unaligned bytes into alignment buffer 371 */ 372 else if ((int)ptr & 1) { 373 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 374 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 375 NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer)); 376 bsc->sc_xfr_align = 1; 377 } 378 ++bzsc_cnt_dma; /* number of DMA operations */ 379 380 while (xfer < bsc->sc_dmasize) { 381 if ((pa + xfer) != kvtop(*addr + xfer)) 382 break; 383 if ((bsc->sc_dmasize - xfer) < NBPG) 384 xfer = bsc->sc_dmasize; 385 else 386 xfer += NBPG; 387 ++bzsc_cnt_dma3; 388 } 389 if (xfer != *len) 390 ++bzsc_cnt_dma2; 391 392 bsc->sc_dmasize = xfer; 393 *dmasize = bsc->sc_dmasize; 394 bsc->sc_pa = pa; 395 #if defined(M68040) || defined(M68060) 396 if (mmutype == MMU_68040) { 397 if (bsc->sc_xfr_align) { 398 dma_cachectl(bsc->sc_alignbuf, 399 sizeof(bsc->sc_alignbuf)); 400 } 401 else 402 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 403 } 404 #endif 405 406 pa >>= 1; 407 if (!bsc->sc_datain) 408 pa |= 0x80000000; 409 bsc->sc_dmabase[0x10] = (u_int8_t)(pa >> 24); 410 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 411 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 412 bsc->sc_dmabase[0] = (u_int8_t)(pa); 413 bsc->sc_active = 1; 414 return 0; 415 } 416 417 void 418 bzsc_dma_go(struct ncr53c9x_softc *sc) 419 { 420 } 421 422 void 423 bzsc_dma_stop(struct ncr53c9x_softc *sc) 424 { 425 } 426 427 int 428 bzsc_dma_isactive(struct ncr53c9x_softc *sc) 429 { 430 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 431 432 return bsc->sc_active; 433 } 434 435 #ifdef DEBUG 436 void 437 bzsc_dump(void) 438 { 439 int i; 440 441 i = bzsc_trace_ptr; 442 printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr); 443 do { 444 if (bzsc_trace[i].hardbits == 0) { 445 i = (i + 1) & 127; 446 continue; 447 } 448 printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits, 449 bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy); 450 if (bzsc_trace[i].status & NCRSTAT_INT) 451 printf("NCRINT/"); 452 if (bzsc_trace[i].status & NCRSTAT_TC) 453 printf("NCRTC/"); 454 switch(bzsc_trace[i].status & NCRSTAT_PHASE) { 455 case 0: 456 printf("dataout"); break; 457 case 1: 458 printf("datain"); break; 459 case 2: 460 printf("cmdout"); break; 461 case 3: 462 printf("status"); break; 463 case 6: 464 printf("msgout"); break; 465 case 7: 466 printf("msgin"); break; 467 default: 468 printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE); 469 } 470 printf(") "); 471 i = (i + 1) & 127; 472 } while (i != bzsc_trace_ptr); 473 printf("\n"); 474 } 475 #endif 476