1 /* $NetBSD: bzsc.c,v 1.28 2001/04/25 17:53:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to 41 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/errno.h> 49 #include <sys/ioctl.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <sys/proc.h> 53 #include <sys/user.h> 54 #include <sys/queue.h> 55 56 #include <dev/scsipi/scsi_all.h> 57 #include <dev/scsipi/scsipi_all.h> 58 #include <dev/scsipi/scsiconf.h> 59 #include <dev/scsipi/scsi_message.h> 60 61 #include <machine/cpu.h> 62 #include <machine/param.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 #include <amiga/amiga/isr.h> 68 #include <amiga/dev/bzscvar.h> 69 #include <amiga/dev/zbusvar.h> 70 71 void bzscattach __P((struct device *, struct device *, void *)); 72 int bzscmatch __P((struct device *, struct cfdata *, void *)); 73 74 /* Linkup to the rest of the kernel */ 75 struct cfattach bzsc_ca = { 76 sizeof(struct bzsc_softc), bzscmatch, bzscattach 77 }; 78 79 /* 80 * Functions and the switch for the MI code. 81 */ 82 u_char bzsc_read_reg __P((struct ncr53c9x_softc *, int)); 83 void bzsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 84 int bzsc_dma_isintr __P((struct ncr53c9x_softc *)); 85 void bzsc_dma_reset __P((struct ncr53c9x_softc *)); 86 int bzsc_dma_intr __P((struct ncr53c9x_softc *)); 87 int bzsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 88 size_t *, int, size_t *)); 89 void bzsc_dma_go __P((struct ncr53c9x_softc *)); 90 void bzsc_dma_stop __P((struct ncr53c9x_softc *)); 91 int bzsc_dma_isactive __P((struct ncr53c9x_softc *)); 92 93 struct ncr53c9x_glue bzsc_glue = { 94 bzsc_read_reg, 95 bzsc_write_reg, 96 bzsc_dma_isintr, 97 bzsc_dma_reset, 98 bzsc_dma_intr, 99 bzsc_dma_setup, 100 bzsc_dma_go, 101 bzsc_dma_stop, 102 bzsc_dma_isactive, 103 0, 104 }; 105 106 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 107 u_long bzsc_max_dma = 1024; 108 extern int ser_open_speed; 109 110 u_long bzsc_cnt_pio = 0; /* number of PIO transfers */ 111 u_long bzsc_cnt_dma = 0; /* number of DMA transfers */ 112 u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 113 u_long bzsc_cnt_dma3 = 0; /* number of pages combined */ 114 115 #ifdef DEBUG 116 struct { 117 u_char hardbits; 118 u_char status; 119 u_char xx; 120 u_char yy; 121 } bzsc_trace[128]; 122 int bzsc_trace_ptr = 0; 123 int bzsc_trace_enable = 1; 124 void bzsc_dump __P((void)); 125 #endif 126 127 /* 128 * if we are a Phase5 Blizzard 1230 II 129 */ 130 int 131 bzscmatch(parent, cf, aux) 132 struct device *parent; 133 struct cfdata *cf; 134 void *aux; 135 { 136 struct zbus_args *zap; 137 volatile u_char *regs; 138 139 zap = aux; 140 if (zap->manid != 0x2140 || zap->prodid != 11) 141 return(0); /* It's not Blizzard 1230 */ 142 if (!is_a1200()) 143 return(0); /* And not A1200 */ 144 regs = &((volatile u_char *)zap->va)[0x10000]; 145 if (badaddr((caddr_t)regs)) 146 return(0); 147 regs[NCR_CFG1 * 2] = 0; 148 regs[NCR_CFG1 * 2] = NCRCFG1_PARENB | 7; 149 delay(5); 150 if (regs[NCR_CFG1 * 2] != (NCRCFG1_PARENB | 7)) 151 return(0); 152 return(1); 153 } 154 155 /* 156 * Attach this instance, and then all the sub-devices 157 */ 158 void 159 bzscattach(parent, self, aux) 160 struct device *parent, *self; 161 void *aux; 162 { 163 struct bzsc_softc *bsc = (void *)self; 164 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 165 struct zbus_args *zap; 166 extern u_long scsi_nosync; 167 extern int shift_nosync; 168 extern int ncr53c9x_debug; 169 170 /* 171 * Set up the glue for MI code early; we use some of it here. 172 */ 173 sc->sc_glue = &bzsc_glue; 174 175 /* 176 * Save the regs 177 */ 178 zap = aux; 179 bsc->sc_reg = &((volatile u_char *)zap->va)[0x10000]; 180 bsc->sc_dmabase = &bsc->sc_reg[0x21]; 181 182 sc->sc_freq = 40; /* Clocked at 40Mhz */ 183 184 printf(": address %p", bsc->sc_reg); 185 186 sc->sc_id = 7; 187 188 /* 189 * It is necessary to try to load the 2nd config register here, 190 * to find out what rev the FAS chip is, else the ncr53c9x_reset 191 * will not set up the defaults correctly. 192 */ 193 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 194 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 195 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 196 sc->sc_rev = NCR_VARIANT_FAS216; 197 198 /* 199 * This is the value used to start sync negotiations 200 * Note that the NCR register "SYNCTP" is programmed 201 * in "clocks per byte", and has a minimum value of 4. 202 * The SCSI period used in negotiation is one-fourth 203 * of the time (in nanoseconds) needed to transfer one byte. 204 * Since the chip's clock is given in MHz, we have the following 205 * formula: 4 * period = (1000 / freq) * 4 206 */ 207 sc->sc_minsync = 1000 / sc->sc_freq; 208 209 /* 210 * get flags from -I argument and set cf_flags. 211 * NOTE: low 8 bits are to disable disconnect, and the next 212 * 8 bits are to disable sync. 213 */ 214 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 215 & 0xffff; 216 shift_nosync += 16; 217 218 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 219 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 220 shift_nosync += 16; 221 222 #if 1 223 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 224 sc->sc_minsync = 0; 225 #endif 226 227 /* Really no limit, but since we want to fit into the TCR... */ 228 sc->sc_maxxfer = 64 * 1024; 229 230 /* 231 * Configure interrupts. 232 */ 233 bsc->sc_isr.isr_intr = ncr53c9x_intr; 234 bsc->sc_isr.isr_arg = sc; 235 bsc->sc_isr.isr_ipl = 2; 236 add_isr(&bsc->sc_isr); 237 238 /* 239 * Now try to attach all the sub-devices 240 */ 241 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 242 sc->sc_adapter.adapt_minphys = minphys; 243 ncr53c9x_attach(sc); 244 } 245 246 /* 247 * Glue functions. 248 */ 249 250 u_char 251 bzsc_read_reg(sc, reg) 252 struct ncr53c9x_softc *sc; 253 int reg; 254 { 255 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 256 257 return bsc->sc_reg[reg * 2]; 258 } 259 260 void 261 bzsc_write_reg(sc, reg, val) 262 struct ncr53c9x_softc *sc; 263 int reg; 264 u_char val; 265 { 266 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 267 u_char v = val; 268 269 bsc->sc_reg[reg * 2] = v; 270 #ifdef DEBUG 271 if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 272 reg == NCR_CMD/* && bsc->sc_active*/) { 273 bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v; 274 /* printf(" cmd %x", v);*/ 275 } 276 #endif 277 } 278 279 int 280 bzsc_dma_isintr(sc) 281 struct ncr53c9x_softc *sc; 282 { 283 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 284 285 if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0) 286 return 0; 287 288 #ifdef DEBUG 289 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzsc_trace_enable) { 290 bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2]; 291 bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2]; 292 bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active; 293 bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127; 294 } 295 #endif 296 return 1; 297 } 298 299 void 300 bzsc_dma_reset(sc) 301 struct ncr53c9x_softc *sc; 302 { 303 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 304 305 bsc->sc_active = 0; 306 } 307 308 int 309 bzsc_dma_intr(sc) 310 struct ncr53c9x_softc *sc; 311 { 312 register struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 313 register int cnt; 314 315 NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 316 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 317 bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF)); 318 if (bsc->sc_active == 0) { 319 printf("bzsc_intr--inactive DMA\n"); 320 return -1; 321 } 322 323 /* update sc_dmaaddr and sc_pdmalen */ 324 cnt = bsc->sc_reg[NCR_TCL * 2]; 325 cnt += bsc->sc_reg[NCR_TCM * 2] << 8; 326 cnt += bsc->sc_reg[NCR_TCH * 2] << 16; 327 if (!bsc->sc_datain) { 328 cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF; 329 bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH; 330 } 331 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 332 NCR_DMA(("DMA xferred %d\n", cnt)); 333 if (bsc->sc_xfr_align) { 334 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 335 bsc->sc_xfr_align = 0; 336 } 337 *bsc->sc_dmaaddr += cnt; 338 *bsc->sc_pdmalen -= cnt; 339 bsc->sc_active = 0; 340 return 0; 341 } 342 343 int 344 bzsc_dma_setup(sc, addr, len, datain, dmasize) 345 struct ncr53c9x_softc *sc; 346 caddr_t *addr; 347 size_t *len; 348 int datain; 349 size_t *dmasize; 350 { 351 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 352 paddr_t pa; 353 u_char *ptr; 354 size_t xfer; 355 356 bsc->sc_dmaaddr = addr; 357 bsc->sc_pdmalen = len; 358 bsc->sc_datain = datain; 359 bsc->sc_dmasize = *dmasize; 360 /* 361 * DMA can be nasty for high-speed serial input, so limit the 362 * size of this DMA operation if the serial port is running at 363 * a high speed (higher than 19200 for now - should be adjusted 364 * based on cpu type and speed?). 365 * XXX - add serial speed check XXX 366 */ 367 if (ser_open_speed > 19200 && bzsc_max_dma != 0 && 368 bsc->sc_dmasize > bzsc_max_dma) 369 bsc->sc_dmasize = bzsc_max_dma; 370 ptr = *addr; /* Kernel virtual address */ 371 pa = kvtop(ptr); /* Physical address of DMA */ 372 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 373 bsc->sc_xfr_align = 0; 374 /* 375 * If output and unaligned, stuff odd byte into FIFO 376 */ 377 if (datain == 0 && (int)ptr & 1) { 378 NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n")); 379 pa++; 380 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 381 bsc->sc_reg[NCR_FIFO * 2] = *ptr++; 382 } 383 /* 384 * If unaligned address, read unaligned bytes into alignment buffer 385 */ 386 else if ((int)ptr & 1) { 387 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 388 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 389 NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer)); 390 bsc->sc_xfr_align = 1; 391 } 392 ++bzsc_cnt_dma; /* number of DMA operations */ 393 394 while (xfer < bsc->sc_dmasize) { 395 if ((pa + xfer) != kvtop(*addr + xfer)) 396 break; 397 if ((bsc->sc_dmasize - xfer) < NBPG) 398 xfer = bsc->sc_dmasize; 399 else 400 xfer += NBPG; 401 ++bzsc_cnt_dma3; 402 } 403 if (xfer != *len) 404 ++bzsc_cnt_dma2; 405 406 bsc->sc_dmasize = xfer; 407 *dmasize = bsc->sc_dmasize; 408 bsc->sc_pa = pa; 409 #if defined(M68040) || defined(M68060) 410 if (mmutype == MMU_68040) { 411 if (bsc->sc_xfr_align) { 412 dma_cachectl(bsc->sc_alignbuf, 413 sizeof(bsc->sc_alignbuf)); 414 } 415 else 416 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 417 } 418 #endif 419 420 pa >>= 1; 421 if (!bsc->sc_datain) 422 pa |= 0x80000000; 423 bsc->sc_dmabase[0x10] = (u_int8_t)(pa >> 24); 424 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 425 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 426 bsc->sc_dmabase[0] = (u_int8_t)(pa); 427 bsc->sc_active = 1; 428 return 0; 429 } 430 431 void 432 bzsc_dma_go(sc) 433 struct ncr53c9x_softc *sc; 434 { 435 } 436 437 void 438 bzsc_dma_stop(sc) 439 struct ncr53c9x_softc *sc; 440 { 441 } 442 443 int 444 bzsc_dma_isactive(sc) 445 struct ncr53c9x_softc *sc; 446 { 447 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 448 449 return bsc->sc_active; 450 } 451 452 #ifdef DEBUG 453 void 454 bzsc_dump() 455 { 456 int i; 457 458 i = bzsc_trace_ptr; 459 printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr); 460 do { 461 if (bzsc_trace[i].hardbits == 0) { 462 i = (i + 1) & 127; 463 continue; 464 } 465 printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits, 466 bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy); 467 if (bzsc_trace[i].status & NCRSTAT_INT) 468 printf("NCRINT/"); 469 if (bzsc_trace[i].status & NCRSTAT_TC) 470 printf("NCRTC/"); 471 switch(bzsc_trace[i].status & NCRSTAT_PHASE) { 472 case 0: 473 printf("dataout"); break; 474 case 1: 475 printf("datain"); break; 476 case 2: 477 printf("cmdout"); break; 478 case 3: 479 printf("status"); break; 480 case 6: 481 printf("msgout"); break; 482 case 7: 483 printf("msgin"); break; 484 default: 485 printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE); 486 } 487 printf(") "); 488 i = (i + 1) & 127; 489 } while (i != bzsc_trace_ptr); 490 printf("\n"); 491 } 492 #endif 493