1 /* $NetBSD: bzsc.c,v 1.45 2009/11/23 00:11:43 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bzsc.c,v 1.45 2009/11/23 00:11:43 rmind Exp $"); 41 42 /* 43 * Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to 44 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/queue.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <dev/scsipi/scsi_all.h> 61 #include <dev/scsipi/scsipi_all.h> 62 #include <dev/scsipi/scsiconf.h> 63 #include <dev/scsipi/scsi_message.h> 64 65 #include <machine/cpu.h> 66 #include <machine/param.h> 67 68 #include <dev/ic/ncr53c9xreg.h> 69 #include <dev/ic/ncr53c9xvar.h> 70 71 #include <amiga/amiga/isr.h> 72 #include <amiga/dev/bzscvar.h> 73 #include <amiga/dev/zbusvar.h> 74 75 #ifdef __powerpc__ 76 #define badaddr(a) badaddr_read(a, 2, NULL) 77 #endif 78 79 int bzscmatch(device_t, cfdata_t, void *); 80 void bzscattach(device_t, device_t, void *); 81 82 /* Linkup to the rest of the kernel */ 83 CFATTACH_DECL_NEW(bzsc, sizeof(struct bzsc_softc), 84 bzscmatch, bzscattach, NULL, NULL); 85 86 /* 87 * Functions and the switch for the MI code. 88 */ 89 uint8_t bzsc_read_reg(struct ncr53c9x_softc *, int); 90 void bzsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 91 int bzsc_dma_isintr(struct ncr53c9x_softc *); 92 void bzsc_dma_reset(struct ncr53c9x_softc *); 93 int bzsc_dma_intr(struct ncr53c9x_softc *); 94 int bzsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 95 size_t *, int, size_t *); 96 void bzsc_dma_go(struct ncr53c9x_softc *); 97 void bzsc_dma_stop(struct ncr53c9x_softc *); 98 int bzsc_dma_isactive(struct ncr53c9x_softc *); 99 100 struct ncr53c9x_glue bzsc_glue = { 101 bzsc_read_reg, 102 bzsc_write_reg, 103 bzsc_dma_isintr, 104 bzsc_dma_reset, 105 bzsc_dma_intr, 106 bzsc_dma_setup, 107 bzsc_dma_go, 108 bzsc_dma_stop, 109 bzsc_dma_isactive, 110 NULL, 111 }; 112 113 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 114 u_long bzsc_max_dma = 1024; 115 extern int ser_open_speed; 116 117 u_long bzsc_cnt_pio = 0; /* number of PIO transfers */ 118 u_long bzsc_cnt_dma = 0; /* number of DMA transfers */ 119 u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 120 u_long bzsc_cnt_dma3 = 0; /* number of pages combined */ 121 122 #ifdef DEBUG 123 struct { 124 uint8_t hardbits; 125 uint8_t status; 126 uint8_t xx; 127 uint8_t yy; 128 } bzsc_trace[128]; 129 int bzsc_trace_ptr = 0; 130 int bzsc_trace_enable = 1; 131 void bzsc_dump(void); 132 #endif 133 134 /* 135 * if we are a Phase5 Blizzard 1230 II 136 */ 137 int 138 bzscmatch(device_t parent, cfdata_t cf, void *aux) 139 { 140 struct zbus_args *zap; 141 volatile uint8_t *regs; 142 143 zap = aux; 144 if (zap->manid != 0x2140 || zap->prodid != 11) 145 return 0; /* It's not Blizzard 1230 */ 146 if (!is_a1200()) 147 return 0; /* And not A1200 */ 148 regs = &((volatile uint8_t *)zap->va)[0x10000]; 149 if (badaddr((void *)__UNVOLATILE(regs))) 150 return 0; 151 regs[NCR_CFG1 * 2] = 0; 152 regs[NCR_CFG1 * 2] = NCRCFG1_PARENB | 7; 153 delay(5); 154 if (regs[NCR_CFG1 * 2] != (NCRCFG1_PARENB | 7)) 155 return 0; 156 return 1; 157 } 158 159 /* 160 * Attach this instance, and then all the sub-devices 161 */ 162 void 163 bzscattach(device_t parent, device_t self, void *aux) 164 { 165 struct bzsc_softc *bsc = device_private(self); 166 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 167 struct zbus_args *zap; 168 extern u_long scsi_nosync; 169 extern int shift_nosync; 170 extern int ncr53c9x_debug; 171 172 /* 173 * Set up the glue for MI code early; we use some of it here. 174 */ 175 sc->sc_dev = self; 176 sc->sc_glue = &bzsc_glue; 177 178 /* 179 * Save the regs 180 */ 181 zap = aux; 182 bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x10000]; 183 bsc->sc_dmabase = &bsc->sc_reg[0x21]; 184 185 sc->sc_freq = 40; /* Clocked at 40 MHz */ 186 187 aprint_normal(": address %p", bsc->sc_reg); 188 189 sc->sc_id = 7; 190 191 /* 192 * It is necessary to try to load the 2nd config register here, 193 * to find out what rev the FAS chip is, else the ncr53c9x_reset 194 * will not set up the defaults correctly. 195 */ 196 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 197 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 198 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 199 sc->sc_rev = NCR_VARIANT_FAS216; 200 201 /* 202 * This is the value used to start sync negotiations 203 * Note that the NCR register "SYNCTP" is programmed 204 * in "clocks per byte", and has a minimum value of 4. 205 * The SCSI period used in negotiation is one-fourth 206 * of the time (in nanoseconds) needed to transfer one byte. 207 * Since the chip's clock is given in MHz, we have the following 208 * formula: 4 * period = (1000 / freq) * 4 209 */ 210 sc->sc_minsync = 1000 / sc->sc_freq; 211 212 /* 213 * get flags from -I argument and set cf_flags. 214 * NOTE: low 8 bits are to disable disconnect, and the next 215 * 8 bits are to disable sync. 216 */ 217 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 218 & 0xffff; 219 shift_nosync += 16; 220 221 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 222 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 223 shift_nosync += 16; 224 225 #if 1 226 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 227 sc->sc_minsync = 0; 228 #endif 229 230 /* Really no limit, but since we want to fit into the TCR... */ 231 sc->sc_maxxfer = 64 * 1024; 232 233 /* 234 * Configure interrupts. 235 */ 236 bsc->sc_isr.isr_intr = ncr53c9x_intr; 237 bsc->sc_isr.isr_arg = sc; 238 bsc->sc_isr.isr_ipl = 2; 239 add_isr(&bsc->sc_isr); 240 241 /* 242 * Now try to attach all the sub-devices 243 */ 244 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 245 sc->sc_adapter.adapt_minphys = minphys; 246 ncr53c9x_attach(sc); 247 } 248 249 /* 250 * Glue functions. 251 */ 252 253 uint8_t 254 bzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 255 { 256 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 257 258 return bsc->sc_reg[reg * 2]; 259 } 260 261 void 262 bzsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 263 { 264 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 265 uint8_t v = val; 266 267 bsc->sc_reg[reg * 2] = v; 268 #ifdef DEBUG 269 if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 270 reg == NCR_CMD/* && bsc->sc_active*/) { 271 bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v; 272 /* printf(" cmd %x", v);*/ 273 } 274 #endif 275 } 276 277 int 278 bzsc_dma_isintr(struct ncr53c9x_softc *sc) 279 { 280 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 281 282 if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0) 283 return 0; 284 285 #ifdef DEBUG 286 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzsc_trace_enable) { 287 bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2]; 288 bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2]; 289 bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active; 290 bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127; 291 } 292 #endif 293 return 1; 294 } 295 296 void 297 bzsc_dma_reset(struct ncr53c9x_softc *sc) 298 { 299 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 300 301 bsc->sc_active = 0; 302 } 303 304 int 305 bzsc_dma_intr(struct ncr53c9x_softc *sc) 306 { 307 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 308 int cnt; 309 310 NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 311 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 312 bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF)); 313 if (bsc->sc_active == 0) { 314 printf("bzsc_intr--inactive DMA\n"); 315 return -1; 316 } 317 318 /* update sc_dmaaddr and sc_pdmalen */ 319 cnt = bsc->sc_reg[NCR_TCL * 2]; 320 cnt += bsc->sc_reg[NCR_TCM * 2] << 8; 321 cnt += bsc->sc_reg[NCR_TCH * 2] << 16; 322 if (!bsc->sc_datain) { 323 cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF; 324 bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH; 325 } 326 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 327 NCR_DMA(("DMA xferred %d\n", cnt)); 328 if (bsc->sc_xfr_align) { 329 memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt); 330 bsc->sc_xfr_align = 0; 331 } 332 *bsc->sc_dmaaddr += cnt; 333 *bsc->sc_pdmalen -= cnt; 334 bsc->sc_active = 0; 335 return 0; 336 } 337 338 int 339 bzsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 340 int datain, size_t *dmasize) 341 { 342 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 343 paddr_t pa; 344 uint8_t *ptr; 345 size_t xfer; 346 347 bsc->sc_dmaaddr = addr; 348 bsc->sc_pdmalen = len; 349 bsc->sc_datain = datain; 350 bsc->sc_dmasize = *dmasize; 351 /* 352 * DMA can be nasty for high-speed serial input, so limit the 353 * size of this DMA operation if the serial port is running at 354 * a high speed (higher than 19200 for now - should be adjusted 355 * based on CPU type and speed?). 356 * XXX - add serial speed check XXX 357 */ 358 if (ser_open_speed > 19200 && bzsc_max_dma != 0 && 359 bsc->sc_dmasize > bzsc_max_dma) 360 bsc->sc_dmasize = bzsc_max_dma; 361 ptr = *addr; /* Kernel virtual address */ 362 pa = kvtop(ptr); /* Physical address of DMA */ 363 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 364 bsc->sc_xfr_align = 0; 365 /* 366 * If output and unaligned, stuff odd byte into FIFO 367 */ 368 if (datain == 0 && (int)ptr & 1) { 369 NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n")); 370 pa++; 371 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 372 bsc->sc_reg[NCR_FIFO * 2] = *ptr++; 373 } 374 /* 375 * If unaligned address, read unaligned bytes into alignment buffer 376 */ 377 else if ((int)ptr & 1) { 378 pa = kvtop((void *)&bsc->sc_alignbuf); 379 xfer = bsc->sc_dmasize = min(xfer, sizeof(bsc->sc_alignbuf)); 380 NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer)); 381 bsc->sc_xfr_align = 1; 382 } 383 ++bzsc_cnt_dma; /* number of DMA operations */ 384 385 while (xfer < bsc->sc_dmasize) { 386 if ((pa + xfer) != kvtop(*addr + xfer)) 387 break; 388 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 389 xfer = bsc->sc_dmasize; 390 else 391 xfer += PAGE_SIZE; 392 ++bzsc_cnt_dma3; 393 } 394 if (xfer != *len) 395 ++bzsc_cnt_dma2; 396 397 bsc->sc_dmasize = xfer; 398 *dmasize = bsc->sc_dmasize; 399 bsc->sc_pa = pa; 400 #if defined(M68040) || defined(M68060) 401 if (mmutype == MMU_68040) { 402 if (bsc->sc_xfr_align) { 403 dma_cachectl(bsc->sc_alignbuf, 404 sizeof(bsc->sc_alignbuf)); 405 } 406 else 407 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 408 } 409 #endif 410 411 pa >>= 1; 412 if (!bsc->sc_datain) 413 pa |= 0x80000000; 414 bsc->sc_dmabase[0x10] = (uint8_t)(pa >> 24); 415 bsc->sc_dmabase[0] = (uint8_t)(pa >> 16); 416 bsc->sc_dmabase[0] = (uint8_t)(pa >> 8); 417 bsc->sc_dmabase[0] = (uint8_t)(pa); 418 bsc->sc_active = 1; 419 return 0; 420 } 421 422 void 423 bzsc_dma_go(struct ncr53c9x_softc *sc) 424 { 425 } 426 427 void 428 bzsc_dma_stop(struct ncr53c9x_softc *sc) 429 { 430 } 431 432 int 433 bzsc_dma_isactive(struct ncr53c9x_softc *sc) 434 { 435 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 436 437 return bsc->sc_active; 438 } 439 440 #ifdef DEBUG 441 void 442 bzsc_dump(void) 443 { 444 int i; 445 446 i = bzsc_trace_ptr; 447 printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr); 448 do { 449 if (bzsc_trace[i].hardbits == 0) { 450 i = (i + 1) & 127; 451 continue; 452 } 453 printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits, 454 bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy); 455 if (bzsc_trace[i].status & NCRSTAT_INT) 456 printf("NCRINT/"); 457 if (bzsc_trace[i].status & NCRSTAT_TC) 458 printf("NCRTC/"); 459 switch(bzsc_trace[i].status & NCRSTAT_PHASE) { 460 case 0: 461 printf("dataout"); break; 462 case 1: 463 printf("datain"); break; 464 case 2: 465 printf("cmdout"); break; 466 case 3: 467 printf("status"); break; 468 case 6: 469 printf("msgout"); break; 470 case 7: 471 printf("msgin"); break; 472 default: 473 printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE); 474 } 475 printf(") "); 476 i = (i + 1) & 127; 477 } while (i != bzsc_trace_ptr); 478 printf("\n"); 479 } 480 #endif 481