1 /* $NetBSD: bzsc.c,v 1.34 2004/02/13 11:36:09 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1995 Daniel Widenfalk 6 * Copyright (c) 1994 Christian E. Hopps 7 * Copyright (c) 1982, 1990 The Regents of the University of California. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Daniel Widenfalk 21 * and Michael L. Hitch. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: bzsc.c,v 1.34 2004/02/13 11:36:09 wiz Exp $"); 41 42 /* 43 * Initial amiga Blizzard 1230-II driver by Daniel Widenfalk. Conversion to 44 * 53c9x MI driver by Michael L. Hitch (mhitch@montana.edu). 45 */ 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/errno.h> 52 #include <sys/ioctl.h> 53 #include <sys/device.h> 54 #include <sys/buf.h> 55 #include <sys/proc.h> 56 #include <sys/user.h> 57 #include <sys/queue.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <dev/scsipi/scsi_all.h> 62 #include <dev/scsipi/scsipi_all.h> 63 #include <dev/scsipi/scsiconf.h> 64 #include <dev/scsipi/scsi_message.h> 65 66 #include <machine/cpu.h> 67 #include <machine/param.h> 68 69 #include <dev/ic/ncr53c9xreg.h> 70 #include <dev/ic/ncr53c9xvar.h> 71 72 #include <amiga/amiga/isr.h> 73 #include <amiga/dev/bzscvar.h> 74 #include <amiga/dev/zbusvar.h> 75 76 void bzscattach(struct device *, struct device *, void *); 77 int bzscmatch(struct device *, struct cfdata *, void *); 78 79 /* Linkup to the rest of the kernel */ 80 CFATTACH_DECL(bzsc, sizeof(struct bzsc_softc), 81 bzscmatch, bzscattach, NULL, NULL); 82 83 /* 84 * Functions and the switch for the MI code. 85 */ 86 u_char bzsc_read_reg(struct ncr53c9x_softc *, int); 87 void bzsc_write_reg(struct ncr53c9x_softc *, int, u_char); 88 int bzsc_dma_isintr(struct ncr53c9x_softc *); 89 void bzsc_dma_reset(struct ncr53c9x_softc *); 90 int bzsc_dma_intr(struct ncr53c9x_softc *); 91 int bzsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 92 size_t *, int, size_t *); 93 void bzsc_dma_go(struct ncr53c9x_softc *); 94 void bzsc_dma_stop(struct ncr53c9x_softc *); 95 int bzsc_dma_isactive(struct ncr53c9x_softc *); 96 97 struct ncr53c9x_glue bzsc_glue = { 98 bzsc_read_reg, 99 bzsc_write_reg, 100 bzsc_dma_isintr, 101 bzsc_dma_reset, 102 bzsc_dma_intr, 103 bzsc_dma_setup, 104 bzsc_dma_go, 105 bzsc_dma_stop, 106 bzsc_dma_isactive, 107 0, 108 }; 109 110 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 111 u_long bzsc_max_dma = 1024; 112 extern int ser_open_speed; 113 114 u_long bzsc_cnt_pio = 0; /* number of PIO transfers */ 115 u_long bzsc_cnt_dma = 0; /* number of DMA transfers */ 116 u_long bzsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 117 u_long bzsc_cnt_dma3 = 0; /* number of pages combined */ 118 119 #ifdef DEBUG 120 struct { 121 u_char hardbits; 122 u_char status; 123 u_char xx; 124 u_char yy; 125 } bzsc_trace[128]; 126 int bzsc_trace_ptr = 0; 127 int bzsc_trace_enable = 1; 128 void bzsc_dump(void); 129 #endif 130 131 /* 132 * if we are a Phase5 Blizzard 1230 II 133 */ 134 int 135 bzscmatch(struct device *parent, struct cfdata *cf, void *aux) 136 { 137 struct zbus_args *zap; 138 volatile u_char *regs; 139 140 zap = aux; 141 if (zap->manid != 0x2140 || zap->prodid != 11) 142 return(0); /* It's not Blizzard 1230 */ 143 if (!is_a1200()) 144 return(0); /* And not A1200 */ 145 regs = &((volatile u_char *)zap->va)[0x10000]; 146 if (badaddr((caddr_t)regs)) 147 return(0); 148 regs[NCR_CFG1 * 2] = 0; 149 regs[NCR_CFG1 * 2] = NCRCFG1_PARENB | 7; 150 delay(5); 151 if (regs[NCR_CFG1 * 2] != (NCRCFG1_PARENB | 7)) 152 return(0); 153 return(1); 154 } 155 156 /* 157 * Attach this instance, and then all the sub-devices 158 */ 159 void 160 bzscattach(struct device *parent, struct device *self, void *aux) 161 { 162 struct bzsc_softc *bsc = (void *)self; 163 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 164 struct zbus_args *zap; 165 extern u_long scsi_nosync; 166 extern int shift_nosync; 167 extern int ncr53c9x_debug; 168 169 /* 170 * Set up the glue for MI code early; we use some of it here. 171 */ 172 sc->sc_glue = &bzsc_glue; 173 174 /* 175 * Save the regs 176 */ 177 zap = aux; 178 bsc->sc_reg = &((volatile u_char *)zap->va)[0x10000]; 179 bsc->sc_dmabase = &bsc->sc_reg[0x21]; 180 181 sc->sc_freq = 40; /* Clocked at 40Mhz */ 182 183 printf(": address %p", bsc->sc_reg); 184 185 sc->sc_id = 7; 186 187 /* 188 * It is necessary to try to load the 2nd config register here, 189 * to find out what rev the FAS chip is, else the ncr53c9x_reset 190 * will not set up the defaults correctly. 191 */ 192 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 193 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 194 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 195 sc->sc_rev = NCR_VARIANT_FAS216; 196 197 /* 198 * This is the value used to start sync negotiations 199 * Note that the NCR register "SYNCTP" is programmed 200 * in "clocks per byte", and has a minimum value of 4. 201 * The SCSI period used in negotiation is one-fourth 202 * of the time (in nanoseconds) needed to transfer one byte. 203 * Since the chip's clock is given in MHz, we have the following 204 * formula: 4 * period = (1000 / freq) * 4 205 */ 206 sc->sc_minsync = 1000 / sc->sc_freq; 207 208 /* 209 * get flags from -I argument and set cf_flags. 210 * NOTE: low 8 bits are to disable disconnect, and the next 211 * 8 bits are to disable sync. 212 */ 213 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 214 & 0xffff; 215 shift_nosync += 16; 216 217 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 218 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 219 shift_nosync += 16; 220 221 #if 1 222 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 223 sc->sc_minsync = 0; 224 #endif 225 226 /* Really no limit, but since we want to fit into the TCR... */ 227 sc->sc_maxxfer = 64 * 1024; 228 229 /* 230 * Configure interrupts. 231 */ 232 bsc->sc_isr.isr_intr = ncr53c9x_intr; 233 bsc->sc_isr.isr_arg = sc; 234 bsc->sc_isr.isr_ipl = 2; 235 add_isr(&bsc->sc_isr); 236 237 /* 238 * Now try to attach all the sub-devices 239 */ 240 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 241 sc->sc_adapter.adapt_minphys = minphys; 242 ncr53c9x_attach(sc); 243 } 244 245 /* 246 * Glue functions. 247 */ 248 249 u_char 250 bzsc_read_reg(struct ncr53c9x_softc *sc, int reg) 251 { 252 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 253 254 return bsc->sc_reg[reg * 2]; 255 } 256 257 void 258 bzsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 259 { 260 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 261 u_char v = val; 262 263 bsc->sc_reg[reg * 2] = v; 264 #ifdef DEBUG 265 if (bzsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ && 266 reg == NCR_CMD/* && bsc->sc_active*/) { 267 bzsc_trace[(bzsc_trace_ptr - 1) & 127].yy = v; 268 /* printf(" cmd %x", v);*/ 269 } 270 #endif 271 } 272 273 int 274 bzsc_dma_isintr(struct ncr53c9x_softc *sc) 275 { 276 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 277 278 if ((bsc->sc_reg[NCR_STAT * 2] & NCRSTAT_INT) == 0) 279 return 0; 280 281 #ifdef DEBUG 282 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzsc_trace_enable) { 283 bzsc_trace[bzsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 2]; 284 bzsc_trace[bzsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 2]; 285 bzsc_trace[bzsc_trace_ptr].yy = bsc->sc_active; 286 bzsc_trace_ptr = (bzsc_trace_ptr + 1) & 127; 287 } 288 #endif 289 return 1; 290 } 291 292 void 293 bzsc_dma_reset(struct ncr53c9x_softc *sc) 294 { 295 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 296 297 bsc->sc_active = 0; 298 } 299 300 int 301 bzsc_dma_intr(struct ncr53c9x_softc *sc) 302 { 303 register struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 304 register int cnt; 305 306 NCR_DMA(("bzsc_dma_intr: cnt %d int %x stat %x fifo %d ", 307 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 308 bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF)); 309 if (bsc->sc_active == 0) { 310 printf("bzsc_intr--inactive DMA\n"); 311 return -1; 312 } 313 314 /* update sc_dmaaddr and sc_pdmalen */ 315 cnt = bsc->sc_reg[NCR_TCL * 2]; 316 cnt += bsc->sc_reg[NCR_TCM * 2] << 8; 317 cnt += bsc->sc_reg[NCR_TCH * 2] << 16; 318 if (!bsc->sc_datain) { 319 cnt += bsc->sc_reg[NCR_FFLAG * 2] & NCRFIFO_FF; 320 bsc->sc_reg[NCR_CMD * 2] = NCRCMD_FLUSH; 321 } 322 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 323 NCR_DMA(("DMA xferred %d\n", cnt)); 324 if (bsc->sc_xfr_align) { 325 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 326 bsc->sc_xfr_align = 0; 327 } 328 *bsc->sc_dmaaddr += cnt; 329 *bsc->sc_pdmalen -= cnt; 330 bsc->sc_active = 0; 331 return 0; 332 } 333 334 int 335 bzsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 336 int datain, size_t *dmasize) 337 { 338 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 339 paddr_t pa; 340 u_char *ptr; 341 size_t xfer; 342 343 bsc->sc_dmaaddr = addr; 344 bsc->sc_pdmalen = len; 345 bsc->sc_datain = datain; 346 bsc->sc_dmasize = *dmasize; 347 /* 348 * DMA can be nasty for high-speed serial input, so limit the 349 * size of this DMA operation if the serial port is running at 350 * a high speed (higher than 19200 for now - should be adjusted 351 * based on CPU type and speed?). 352 * XXX - add serial speed check XXX 353 */ 354 if (ser_open_speed > 19200 && bzsc_max_dma != 0 && 355 bsc->sc_dmasize > bzsc_max_dma) 356 bsc->sc_dmasize = bzsc_max_dma; 357 ptr = *addr; /* Kernel virtual address */ 358 pa = kvtop(ptr); /* Physical address of DMA */ 359 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 360 bsc->sc_xfr_align = 0; 361 /* 362 * If output and unaligned, stuff odd byte into FIFO 363 */ 364 if (datain == 0 && (int)ptr & 1) { 365 NCR_DMA(("bzsc_dma_setup: align byte written to fifo\n")); 366 pa++; 367 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 368 bsc->sc_reg[NCR_FIFO * 2] = *ptr++; 369 } 370 /* 371 * If unaligned address, read unaligned bytes into alignment buffer 372 */ 373 else if ((int)ptr & 1) { 374 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 375 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 376 NCR_DMA(("bzsc_dma_setup: align read by %d bytes\n", xfer)); 377 bsc->sc_xfr_align = 1; 378 } 379 ++bzsc_cnt_dma; /* number of DMA operations */ 380 381 while (xfer < bsc->sc_dmasize) { 382 if ((pa + xfer) != kvtop(*addr + xfer)) 383 break; 384 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 385 xfer = bsc->sc_dmasize; 386 else 387 xfer += PAGE_SIZE; 388 ++bzsc_cnt_dma3; 389 } 390 if (xfer != *len) 391 ++bzsc_cnt_dma2; 392 393 bsc->sc_dmasize = xfer; 394 *dmasize = bsc->sc_dmasize; 395 bsc->sc_pa = pa; 396 #if defined(M68040) || defined(M68060) 397 if (mmutype == MMU_68040) { 398 if (bsc->sc_xfr_align) { 399 dma_cachectl(bsc->sc_alignbuf, 400 sizeof(bsc->sc_alignbuf)); 401 } 402 else 403 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 404 } 405 #endif 406 407 pa >>= 1; 408 if (!bsc->sc_datain) 409 pa |= 0x80000000; 410 bsc->sc_dmabase[0x10] = (u_int8_t)(pa >> 24); 411 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 412 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 413 bsc->sc_dmabase[0] = (u_int8_t)(pa); 414 bsc->sc_active = 1; 415 return 0; 416 } 417 418 void 419 bzsc_dma_go(struct ncr53c9x_softc *sc) 420 { 421 } 422 423 void 424 bzsc_dma_stop(struct ncr53c9x_softc *sc) 425 { 426 } 427 428 int 429 bzsc_dma_isactive(struct ncr53c9x_softc *sc) 430 { 431 struct bzsc_softc *bsc = (struct bzsc_softc *)sc; 432 433 return bsc->sc_active; 434 } 435 436 #ifdef DEBUG 437 void 438 bzsc_dump(void) 439 { 440 int i; 441 442 i = bzsc_trace_ptr; 443 printf("bzsc_trace dump: ptr %x\n", bzsc_trace_ptr); 444 do { 445 if (bzsc_trace[i].hardbits == 0) { 446 i = (i + 1) & 127; 447 continue; 448 } 449 printf("%02x%02x%02x%02x(", bzsc_trace[i].hardbits, 450 bzsc_trace[i].status, bzsc_trace[i].xx, bzsc_trace[i].yy); 451 if (bzsc_trace[i].status & NCRSTAT_INT) 452 printf("NCRINT/"); 453 if (bzsc_trace[i].status & NCRSTAT_TC) 454 printf("NCRTC/"); 455 switch(bzsc_trace[i].status & NCRSTAT_PHASE) { 456 case 0: 457 printf("dataout"); break; 458 case 1: 459 printf("datain"); break; 460 case 2: 461 printf("cmdout"); break; 462 case 3: 463 printf("status"); break; 464 case 6: 465 printf("msgout"); break; 466 case 7: 467 printf("msgin"); break; 468 default: 469 printf("phase%d?", bzsc_trace[i].status & NCRSTAT_PHASE); 470 } 471 printf(") "); 472 i = (i + 1) & 127; 473 } while (i != bzsc_trace_ptr); 474 printf("\n"); 475 } 476 #endif 477