1 /* $NetBSD: bzivsc.c,v 1.33 2019/01/08 19:41:09 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the University nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #ifdef __m68k__ 35 #include "opt_m68k_arch.h" 36 #endif 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: bzivsc.c,v 1.33 2019/01/08 19:41:09 jdolecek Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/queue.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/cpu.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 #include <amiga/amiga/isr.h> 63 #include <amiga/dev/bzivscvar.h> 64 #include <amiga/dev/zbusvar.h> 65 66 #ifdef __powerpc__ 67 #define badaddr(a) badaddr_read(a, 2, NULL) 68 #endif 69 70 int bzivscmatch(device_t, cfdata_t, void *); 71 void bzivscattach(device_t, device_t, void *); 72 73 /* Linkup to the rest of the kernel */ 74 CFATTACH_DECL_NEW(bzivsc, sizeof(struct bzivsc_softc), 75 bzivscmatch, bzivscattach, NULL, NULL); 76 77 /* 78 * Functions and the switch for the MI code. 79 */ 80 uint8_t bzivsc_read_reg(struct ncr53c9x_softc *, int); 81 void bzivsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 82 int bzivsc_dma_isintr(struct ncr53c9x_softc *); 83 void bzivsc_dma_reset(struct ncr53c9x_softc *); 84 int bzivsc_dma_intr(struct ncr53c9x_softc *); 85 int bzivsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 86 size_t *, int, size_t *); 87 void bzivsc_dma_go(struct ncr53c9x_softc *); 88 void bzivsc_dma_stop(struct ncr53c9x_softc *); 89 int bzivsc_dma_isactive(struct ncr53c9x_softc *); 90 91 struct ncr53c9x_glue bzivsc_glue = { 92 bzivsc_read_reg, 93 bzivsc_write_reg, 94 bzivsc_dma_isintr, 95 bzivsc_dma_reset, 96 bzivsc_dma_intr, 97 bzivsc_dma_setup, 98 bzivsc_dma_go, 99 bzivsc_dma_stop, 100 bzivsc_dma_isactive, 101 NULL, 102 }; 103 104 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 105 u_long bzivsc_max_dma = 1024; 106 extern int ser_open_speed; 107 108 u_long bzivsc_cnt_pio = 0; /* number of PIO transfers */ 109 u_long bzivsc_cnt_dma = 0; /* number of DMA transfers */ 110 u_long bzivsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 111 u_long bzivsc_cnt_dma3 = 0; /* number of pages combined */ 112 113 #ifdef DEBUG 114 struct { 115 uint8_t hardbits; 116 uint8_t status; 117 uint8_t xx; 118 uint8_t yy; 119 } bzivsc_trace[128]; 120 int bzivsc_trace_ptr = 0; 121 int bzivsc_trace_enable = 1; 122 void bzivsc_dump(void); 123 #endif 124 125 /* 126 * if we are a Phase5 Blizzard 12x0-IV 127 */ 128 int 129 bzivscmatch(device_t parent, cfdata_t cf, void *aux) 130 { 131 struct zbus_args *zap; 132 volatile uint8_t *regs; 133 134 zap = aux; 135 if (zap->manid != 0x2140) 136 return 0; /* It's not Phase 5 */ 137 if (zap->prodid != 11 && zap->prodid != 17) 138 return 0; /* Not Blizzard 12x0 */ 139 if (!is_a1200()) 140 return 0; /* And not A1200 */ 141 regs = &((volatile u_char *)zap->va)[0x8000]; 142 if (badaddr((void *)__UNVOLATILE(regs))) 143 return 0; 144 regs[NCR_CFG1 * 4] = 0; 145 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 146 delay(5); 147 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 148 return 0; 149 return 1; 150 } 151 152 /* 153 * Attach this instance, and then all the sub-devices 154 */ 155 void 156 bzivscattach(device_t parent, device_t self, void *aux) 157 { 158 struct bzivsc_softc *bsc = device_private(self); 159 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 160 struct zbus_args *zap; 161 extern u_long scsi_nosync; 162 extern int shift_nosync; 163 extern int ncr53c9x_debug; 164 165 /* 166 * Set up the glue for MI code early; we use some of it here. 167 */ 168 sc->sc_dev = self; 169 sc->sc_glue = &bzivsc_glue; 170 171 /* 172 * Save the regs 173 */ 174 zap = aux; 175 bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x8000]; 176 bsc->sc_dmabase = &bsc->sc_reg[0x8000]; 177 178 sc->sc_freq = 40; /* Clocked at 40 MHz */ 179 180 aprint_normal(": address %p", bsc->sc_reg); 181 182 sc->sc_id = 7; 183 184 /* 185 * It is necessary to try to load the 2nd config register here, 186 * to find out what rev the FAS chip is, else the ncr53c9x_reset 187 * will not set up the defaults correctly. 188 */ 189 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 190 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 191 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 192 sc->sc_rev = NCR_VARIANT_FAS216; 193 194 /* 195 * This is the value used to start sync negotiations 196 * Note that the NCR register "SYNCTP" is programmed 197 * in "clocks per byte", and has a minimum value of 4. 198 * The SCSI period used in negotiation is one-fourth 199 * of the time (in nanoseconds) needed to transfer one byte. 200 * Since the chip's clock is given in MHz, we have the following 201 * formula: 4 * period = (1000 / freq) * 4 202 */ 203 sc->sc_minsync = 1000 / sc->sc_freq; 204 205 /* 206 * get flags from -I argument and set cf_flags. 207 * NOTE: low 8 bits are to disable disconnect, and the next 208 * 8 bits are to disable sync. 209 */ 210 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 211 & 0xffff; 212 shift_nosync += 16; 213 214 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 215 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 216 shift_nosync += 16; 217 218 #if 1 219 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 220 sc->sc_minsync = 0; 221 #endif 222 223 /* Really no limit, but since we want to fit into the TCR... */ 224 sc->sc_maxxfer = 64 * 1024; 225 226 /* 227 * Configure interrupts. 228 */ 229 bsc->sc_isr.isr_intr = ncr53c9x_intr; 230 bsc->sc_isr.isr_arg = sc; 231 bsc->sc_isr.isr_ipl = 2; 232 add_isr(&bsc->sc_isr); 233 234 /* 235 * Now try to attach all the sub-devices 236 */ 237 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 238 sc->sc_adapter.adapt_minphys = minphys; 239 ncr53c9x_attach(sc); 240 } 241 242 /* 243 * Glue functions. 244 */ 245 246 uint8_t 247 bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg) 248 { 249 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 250 251 return bsc->sc_reg[reg * 4]; 252 } 253 254 void 255 bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 256 { 257 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 258 uint8_t v = val; 259 260 bsc->sc_reg[reg * 4] = v; 261 #ifdef DEBUG 262 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ && 263 reg == NCR_CMD/* && bsc->sc_active*/) { 264 bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v; 265 /* printf(" cmd %x", v);*/ 266 } 267 #endif 268 } 269 270 int 271 bzivsc_dma_isintr(struct ncr53c9x_softc *sc) 272 { 273 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 274 275 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 276 return 0; 277 278 #ifdef DEBUG 279 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) { 280 bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 281 bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 282 bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active; 283 bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127; 284 } 285 #endif 286 return 1; 287 } 288 289 void 290 bzivsc_dma_reset(struct ncr53c9x_softc *sc) 291 { 292 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 293 294 bsc->sc_active = 0; 295 } 296 297 int 298 bzivsc_dma_intr(struct ncr53c9x_softc *sc) 299 { 300 register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 301 register int cnt; 302 303 NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ", 304 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 305 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 306 if (bsc->sc_active == 0) { 307 printf("bzivsc_intr--inactive DMA\n"); 308 return -1; 309 } 310 311 /* update sc_dmaaddr and sc_pdmalen */ 312 cnt = bsc->sc_reg[NCR_TCL * 4]; 313 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 314 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 315 if (!bsc->sc_datain) { 316 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 317 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 318 } 319 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 320 NCR_DMA(("DMA xferred %d\n", cnt)); 321 if (bsc->sc_xfr_align) { 322 memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt); 323 bsc->sc_xfr_align = 0; 324 } 325 *bsc->sc_dmaaddr += cnt; 326 *bsc->sc_pdmalen -= cnt; 327 bsc->sc_active = 0; 328 return 0; 329 } 330 331 int 332 bzivsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 333 int datain, size_t *dmasize) 334 { 335 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 336 paddr_t pa; 337 uint8_t *ptr; 338 size_t xfer; 339 340 bsc->sc_dmaaddr = addr; 341 bsc->sc_pdmalen = len; 342 bsc->sc_datain = datain; 343 bsc->sc_dmasize = *dmasize; 344 /* 345 * DMA can be nasty for high-speed serial input, so limit the 346 * size of this DMA operation if the serial port is running at 347 * a high speed (higher than 19200 for now - should be adjusted 348 * based on CPU type and speed?). 349 * XXX - add serial speed check XXX 350 */ 351 if (ser_open_speed > 19200 && bzivsc_max_dma != 0 && 352 bsc->sc_dmasize > bzivsc_max_dma) 353 bsc->sc_dmasize = bzivsc_max_dma; 354 ptr = *addr; /* Kernel virtual address */ 355 pa = kvtop(ptr); /* Physical address of DMA */ 356 xfer = uimin(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 357 bsc->sc_xfr_align = 0; 358 /* 359 * If output and unaligned, stuff odd byte into FIFO 360 */ 361 if (datain == 0 && (int)ptr & 1) { 362 NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n")); 363 pa++; 364 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 365 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 366 } 367 /* 368 * If unaligned address, read unaligned bytes into alignment buffer 369 */ 370 else if ((int)ptr & 1) { 371 pa = kvtop((void *)&bsc->sc_alignbuf); 372 xfer = bsc->sc_dmasize = uimin(xfer, sizeof(bsc->sc_alignbuf)); 373 NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer)); 374 bsc->sc_xfr_align = 1; 375 } 376 ++bzivsc_cnt_dma; /* number of DMA operations */ 377 378 while (xfer < bsc->sc_dmasize) { 379 if ((pa + xfer) != kvtop(*addr + xfer)) 380 break; 381 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 382 xfer = bsc->sc_dmasize; 383 else 384 xfer += PAGE_SIZE; 385 ++bzivsc_cnt_dma3; 386 } 387 if (xfer != *len) 388 ++bzivsc_cnt_dma2; 389 390 bsc->sc_dmasize = xfer; 391 *dmasize = bsc->sc_dmasize; 392 bsc->sc_pa = pa; 393 #if defined(M68040) || defined(M68060) 394 if (mmutype == MMU_68040) { 395 if (bsc->sc_xfr_align) { 396 dma_cachectl(bsc->sc_alignbuf, 397 sizeof(bsc->sc_alignbuf)); 398 } 399 else 400 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 401 } 402 #endif 403 404 pa >>= 1; 405 if (!bsc->sc_datain) 406 pa |= 0x80000000; 407 bsc->sc_dmabase[0x8000] = (uint8_t)(pa >> 24); 408 bsc->sc_dmabase[0] = (uint8_t)(pa >> 24); 409 bsc->sc_dmabase[0] = (uint8_t)(pa >> 16); 410 bsc->sc_dmabase[0] = (uint8_t)(pa >> 8); 411 bsc->sc_dmabase[0] = (uint8_t)(pa); 412 bsc->sc_active = 1; 413 return 0; 414 } 415 416 void 417 bzivsc_dma_go(struct ncr53c9x_softc *sc) 418 { 419 } 420 421 void 422 bzivsc_dma_stop(struct ncr53c9x_softc *sc) 423 { 424 } 425 426 int 427 bzivsc_dma_isactive(struct ncr53c9x_softc *sc) 428 { 429 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 430 431 return bsc->sc_active; 432 } 433 434 #ifdef DEBUG 435 void 436 bzivsc_dump(void) 437 { 438 int i; 439 440 i = bzivsc_trace_ptr; 441 printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr); 442 do { 443 if (bzivsc_trace[i].hardbits == 0) { 444 i = (i + 1) & 127; 445 continue; 446 } 447 printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits, 448 bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy); 449 if (bzivsc_trace[i].status & NCRSTAT_INT) 450 printf("NCRINT/"); 451 if (bzivsc_trace[i].status & NCRSTAT_TC) 452 printf("NCRTC/"); 453 switch(bzivsc_trace[i].status & NCRSTAT_PHASE) { 454 case 0: 455 printf("dataout"); break; 456 case 1: 457 printf("datain"); break; 458 case 2: 459 printf("cmdout"); break; 460 case 3: 461 printf("status"); break; 462 case 6: 463 printf("msgout"); break; 464 case 7: 465 printf("msgin"); break; 466 default: 467 printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE); 468 } 469 printf(") "); 470 i = (i + 1) & 127; 471 } while (i != bzivsc_trace_ptr); 472 printf("\n"); 473 } 474 #endif 475