1 /* $NetBSD: bzivsc.c,v 1.20 2006/03/29 04:16:45 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: bzivsc.c,v 1.20 2006/03/29 04:16:45 thorpej Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/cpu.h> 61 #include <machine/param.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <amiga/amiga/isr.h> 67 #include <amiga/dev/bzivscvar.h> 68 #include <amiga/dev/zbusvar.h> 69 70 void bzivscattach(struct device *, struct device *, void *); 71 int bzivscmatch(struct device *, struct cfdata *, void *); 72 73 /* Linkup to the rest of the kernel */ 74 CFATTACH_DECL(bzivsc, sizeof(struct bzivsc_softc), 75 bzivscmatch, bzivscattach, NULL, NULL); 76 77 /* 78 * Functions and the switch for the MI code. 79 */ 80 u_char bzivsc_read_reg(struct ncr53c9x_softc *, int); 81 void bzivsc_write_reg(struct ncr53c9x_softc *, int, u_char); 82 int bzivsc_dma_isintr(struct ncr53c9x_softc *); 83 void bzivsc_dma_reset(struct ncr53c9x_softc *); 84 int bzivsc_dma_intr(struct ncr53c9x_softc *); 85 int bzivsc_dma_setup(struct ncr53c9x_softc *, caddr_t *, 86 size_t *, int, size_t *); 87 void bzivsc_dma_go(struct ncr53c9x_softc *); 88 void bzivsc_dma_stop(struct ncr53c9x_softc *); 89 int bzivsc_dma_isactive(struct ncr53c9x_softc *); 90 91 struct ncr53c9x_glue bzivsc_glue = { 92 bzivsc_read_reg, 93 bzivsc_write_reg, 94 bzivsc_dma_isintr, 95 bzivsc_dma_reset, 96 bzivsc_dma_intr, 97 bzivsc_dma_setup, 98 bzivsc_dma_go, 99 bzivsc_dma_stop, 100 bzivsc_dma_isactive, 101 0, 102 }; 103 104 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 105 u_long bzivsc_max_dma = 1024; 106 extern int ser_open_speed; 107 108 u_long bzivsc_cnt_pio = 0; /* number of PIO transfers */ 109 u_long bzivsc_cnt_dma = 0; /* number of DMA transfers */ 110 u_long bzivsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 111 u_long bzivsc_cnt_dma3 = 0; /* number of pages combined */ 112 113 #ifdef DEBUG 114 struct { 115 u_char hardbits; 116 u_char status; 117 u_char xx; 118 u_char yy; 119 } bzivsc_trace[128]; 120 int bzivsc_trace_ptr = 0; 121 int bzivsc_trace_enable = 1; 122 void bzivsc_dump(void); 123 #endif 124 125 /* 126 * if we are a Phase5 Blizzard 12x0-IV 127 */ 128 int 129 bzivscmatch(struct device *parent, struct cfdata *cf, void *aux) 130 { 131 struct zbus_args *zap; 132 volatile u_char *regs; 133 134 zap = aux; 135 if (zap->manid != 0x2140) 136 return(0); /* It's not Phase 5 */ 137 if (zap->prodid != 11 && zap->prodid != 17) 138 return(0); /* Not Blizzard 12x0 */ 139 if (!is_a1200()) 140 return(0); /* And not A1200 */ 141 regs = &((volatile u_char *)zap->va)[0x8000]; 142 if (badaddr((caddr_t)__UNVOLATILE(regs))) 143 return(0); 144 regs[NCR_CFG1 * 4] = 0; 145 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 146 delay(5); 147 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 148 return(0); 149 return(1); 150 } 151 152 /* 153 * Attach this instance, and then all the sub-devices 154 */ 155 void 156 bzivscattach(struct device *parent, struct device *self, void *aux) 157 { 158 struct bzivsc_softc *bsc = (void *)self; 159 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 160 struct zbus_args *zap; 161 extern u_long scsi_nosync; 162 extern int shift_nosync; 163 extern int ncr53c9x_debug; 164 165 /* 166 * Set up the glue for MI code early; we use some of it here. 167 */ 168 sc->sc_glue = &bzivsc_glue; 169 170 /* 171 * Save the regs 172 */ 173 zap = aux; 174 bsc->sc_reg = &((volatile u_char *)zap->va)[0x8000]; 175 bsc->sc_dmabase = &bsc->sc_reg[0x8000]; 176 177 sc->sc_freq = 40; /* Clocked at 40 MHz */ 178 179 printf(": address %p", bsc->sc_reg); 180 181 sc->sc_id = 7; 182 183 /* 184 * It is necessary to try to load the 2nd config register here, 185 * to find out what rev the FAS chip is, else the ncr53c9x_reset 186 * will not set up the defaults correctly. 187 */ 188 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 189 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 190 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 191 sc->sc_rev = NCR_VARIANT_FAS216; 192 193 /* 194 * This is the value used to start sync negotiations 195 * Note that the NCR register "SYNCTP" is programmed 196 * in "clocks per byte", and has a minimum value of 4. 197 * The SCSI period used in negotiation is one-fourth 198 * of the time (in nanoseconds) needed to transfer one byte. 199 * Since the chip's clock is given in MHz, we have the following 200 * formula: 4 * period = (1000 / freq) * 4 201 */ 202 sc->sc_minsync = 1000 / sc->sc_freq; 203 204 /* 205 * get flags from -I argument and set cf_flags. 206 * NOTE: low 8 bits are to disable disconnect, and the next 207 * 8 bits are to disable sync. 208 */ 209 device_cfdata(&sc->sc_dev)->cf_flags |= (scsi_nosync >> shift_nosync) 210 & 0xffff; 211 shift_nosync += 16; 212 213 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 214 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 215 shift_nosync += 16; 216 217 #if 1 218 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 219 sc->sc_minsync = 0; 220 #endif 221 222 /* Really no limit, but since we want to fit into the TCR... */ 223 sc->sc_maxxfer = 64 * 1024; 224 225 /* 226 * Configure interrupts. 227 */ 228 bsc->sc_isr.isr_intr = ncr53c9x_intr; 229 bsc->sc_isr.isr_arg = sc; 230 bsc->sc_isr.isr_ipl = 2; 231 add_isr(&bsc->sc_isr); 232 233 /* 234 * Now try to attach all the sub-devices 235 */ 236 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 237 sc->sc_adapter.adapt_minphys = minphys; 238 ncr53c9x_attach(sc); 239 } 240 241 /* 242 * Glue functions. 243 */ 244 245 u_char 246 bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg) 247 { 248 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 249 250 return bsc->sc_reg[reg * 4]; 251 } 252 253 void 254 bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 255 { 256 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 257 u_char v = val; 258 259 bsc->sc_reg[reg * 4] = v; 260 #ifdef DEBUG 261 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ && 262 reg == NCR_CMD/* && bsc->sc_active*/) { 263 bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v; 264 /* printf(" cmd %x", v);*/ 265 } 266 #endif 267 } 268 269 int 270 bzivsc_dma_isintr(struct ncr53c9x_softc *sc) 271 { 272 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 273 274 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 275 return 0; 276 277 #ifdef DEBUG 278 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) { 279 bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 280 bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 281 bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active; 282 bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127; 283 } 284 #endif 285 return 1; 286 } 287 288 void 289 bzivsc_dma_reset(struct ncr53c9x_softc *sc) 290 { 291 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 292 293 bsc->sc_active = 0; 294 } 295 296 int 297 bzivsc_dma_intr(struct ncr53c9x_softc *sc) 298 { 299 register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 300 register int cnt; 301 302 NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ", 303 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 304 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 305 if (bsc->sc_active == 0) { 306 printf("bzivsc_intr--inactive DMA\n"); 307 return -1; 308 } 309 310 /* update sc_dmaaddr and sc_pdmalen */ 311 cnt = bsc->sc_reg[NCR_TCL * 4]; 312 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 313 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 314 if (!bsc->sc_datain) { 315 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 316 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 317 } 318 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 319 NCR_DMA(("DMA xferred %d\n", cnt)); 320 if (bsc->sc_xfr_align) { 321 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 322 bsc->sc_xfr_align = 0; 323 } 324 *bsc->sc_dmaaddr += cnt; 325 *bsc->sc_pdmalen -= cnt; 326 bsc->sc_active = 0; 327 return 0; 328 } 329 330 int 331 bzivsc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 332 int datain, size_t *dmasize) 333 { 334 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 335 paddr_t pa; 336 u_char *ptr; 337 size_t xfer; 338 339 bsc->sc_dmaaddr = addr; 340 bsc->sc_pdmalen = len; 341 bsc->sc_datain = datain; 342 bsc->sc_dmasize = *dmasize; 343 /* 344 * DMA can be nasty for high-speed serial input, so limit the 345 * size of this DMA operation if the serial port is running at 346 * a high speed (higher than 19200 for now - should be adjusted 347 * based on CPU type and speed?). 348 * XXX - add serial speed check XXX 349 */ 350 if (ser_open_speed > 19200 && bzivsc_max_dma != 0 && 351 bsc->sc_dmasize > bzivsc_max_dma) 352 bsc->sc_dmasize = bzivsc_max_dma; 353 ptr = *addr; /* Kernel virtual address */ 354 pa = kvtop(ptr); /* Physical address of DMA */ 355 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 356 bsc->sc_xfr_align = 0; 357 /* 358 * If output and unaligned, stuff odd byte into FIFO 359 */ 360 if (datain == 0 && (int)ptr & 1) { 361 NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n")); 362 pa++; 363 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 364 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 365 } 366 /* 367 * If unaligned address, read unaligned bytes into alignment buffer 368 */ 369 else if ((int)ptr & 1) { 370 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 371 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 372 NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer)); 373 bsc->sc_xfr_align = 1; 374 } 375 ++bzivsc_cnt_dma; /* number of DMA operations */ 376 377 while (xfer < bsc->sc_dmasize) { 378 if ((pa + xfer) != kvtop(*addr + xfer)) 379 break; 380 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 381 xfer = bsc->sc_dmasize; 382 else 383 xfer += PAGE_SIZE; 384 ++bzivsc_cnt_dma3; 385 } 386 if (xfer != *len) 387 ++bzivsc_cnt_dma2; 388 389 bsc->sc_dmasize = xfer; 390 *dmasize = bsc->sc_dmasize; 391 bsc->sc_pa = pa; 392 #if defined(M68040) || defined(M68060) 393 if (mmutype == MMU_68040) { 394 if (bsc->sc_xfr_align) { 395 dma_cachectl(bsc->sc_alignbuf, 396 sizeof(bsc->sc_alignbuf)); 397 } 398 else 399 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 400 } 401 #endif 402 403 pa >>= 1; 404 if (!bsc->sc_datain) 405 pa |= 0x80000000; 406 bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24); 407 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 408 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 409 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 410 bsc->sc_dmabase[0] = (u_int8_t)(pa); 411 bsc->sc_active = 1; 412 return 0; 413 } 414 415 void 416 bzivsc_dma_go(struct ncr53c9x_softc *sc) 417 { 418 } 419 420 void 421 bzivsc_dma_stop(struct ncr53c9x_softc *sc) 422 { 423 } 424 425 int 426 bzivsc_dma_isactive(struct ncr53c9x_softc *sc) 427 { 428 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 429 430 return bsc->sc_active; 431 } 432 433 #ifdef DEBUG 434 void 435 bzivsc_dump(void) 436 { 437 int i; 438 439 i = bzivsc_trace_ptr; 440 printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr); 441 do { 442 if (bzivsc_trace[i].hardbits == 0) { 443 i = (i + 1) & 127; 444 continue; 445 } 446 printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits, 447 bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy); 448 if (bzivsc_trace[i].status & NCRSTAT_INT) 449 printf("NCRINT/"); 450 if (bzivsc_trace[i].status & NCRSTAT_TC) 451 printf("NCRTC/"); 452 switch(bzivsc_trace[i].status & NCRSTAT_PHASE) { 453 case 0: 454 printf("dataout"); break; 455 case 1: 456 printf("datain"); break; 457 case 2: 458 printf("cmdout"); break; 459 case 3: 460 printf("status"); break; 461 case 6: 462 printf("msgout"); break; 463 case 7: 464 printf("msgin"); break; 465 default: 466 printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE); 467 } 468 printf(") "); 469 i = (i + 1) & 127; 470 } while (i != bzivsc_trace_ptr); 471 printf("\n"); 472 } 473 #endif 474