1 /* $NetBSD: bzivsc.c,v 1.1 1997/10/10 04:53:32 mhitch Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/ioctl.h> 44 #include <sys/device.h> 45 #include <sys/buf.h> 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/queue.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsipi_all.h> 52 #include <dev/scsipi/scsiconf.h> 53 #include <dev/scsipi/scsi_message.h> 54 55 #include <machine/cpu.h> 56 #include <machine/param.h> 57 58 #include <dev/ic/ncr53c9xreg.h> 59 #include <dev/ic/ncr53c9xvar.h> 60 61 #include <amiga/amiga/isr.h> 62 #include <amiga/dev/bzivscvar.h> 63 #include <amiga/dev/zbusvar.h> 64 65 void bzivscattach __P((struct device *, struct device *, void *)); 66 int bzivscmatch __P((struct device *, struct cfdata *, void *)); 67 68 /* Linkup to the rest of the kernel */ 69 struct cfattach bzivsc_ca = { 70 sizeof(struct bzivsc_softc), bzivscmatch, bzivscattach 71 }; 72 73 struct cfdriver bzivsc_cd = { 74 NULL, "bzivsc", DV_DULL 75 }; 76 77 struct scsipi_adapter bzivsc_switch = { 78 ncr53c9x_scsi_cmd, 79 minphys, /* no max at this level; handled by DMA code */ 80 NULL, 81 NULL, 82 }; 83 84 struct scsipi_device bzivsc_dev = { 85 NULL, /* Use default error handler */ 86 NULL, /* have a queue, served by this */ 87 NULL, /* have no async handler */ 88 NULL, /* Use default 'done' routine */ 89 }; 90 91 /* 92 * Functions and the switch for the MI code. 93 */ 94 u_char bzivsc_read_reg __P((struct ncr53c9x_softc *, int)); 95 void bzivsc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 96 int bzivsc_dma_isintr __P((struct ncr53c9x_softc *)); 97 void bzivsc_dma_reset __P((struct ncr53c9x_softc *)); 98 int bzivsc_dma_intr __P((struct ncr53c9x_softc *)); 99 int bzivsc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 100 size_t *, int, size_t *)); 101 void bzivsc_dma_go __P((struct ncr53c9x_softc *)); 102 void bzivsc_dma_stop __P((struct ncr53c9x_softc *)); 103 int bzivsc_dma_isactive __P((struct ncr53c9x_softc *)); 104 105 struct ncr53c9x_glue bzivsc_glue = { 106 bzivsc_read_reg, 107 bzivsc_write_reg, 108 bzivsc_dma_isintr, 109 bzivsc_dma_reset, 110 bzivsc_dma_intr, 111 bzivsc_dma_setup, 112 bzivsc_dma_go, 113 bzivsc_dma_stop, 114 bzivsc_dma_isactive, 115 0, 116 }; 117 118 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 119 u_long bzivsc_max_dma = 1024; 120 extern int ser_open_speed; 121 122 u_long bzivsc_cnt_pio = 0; /* number of PIO transfers */ 123 u_long bzivsc_cnt_dma = 0; /* number of DMA transfers */ 124 u_long bzivsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 125 u_long bzivsc_cnt_dma3 = 0; /* number of pages combined */ 126 127 #ifdef DEBUG 128 struct { 129 u_char hardbits; 130 u_char status; 131 u_char xx; 132 u_char yy; 133 } bzivsc_trace[128]; 134 int bzivsc_trace_ptr = 0; 135 int bzivsc_trace_enable = 1; 136 void bzivsc_dump __P((void)); 137 #endif 138 139 /* 140 * if we are a Phase5 Blizzard 12x0-IV 141 */ 142 int 143 bzivscmatch(parent, cf, aux) 144 struct device *parent; 145 struct cfdata *cf; 146 void *aux; 147 { 148 struct zbus_args *zap; 149 volatile u_char *regs; 150 151 zap = aux; 152 if (zap->manid != 0x2140) 153 return(0); /* It's not Phase 5 */ 154 if (zap->prodid != 11 && zap->prodid != 17) 155 return(0); /* Not Blizzard 12x0 */ 156 if (!is_a1200()) 157 return(0); /* And not A1200 */ 158 regs = &((volatile u_char *)zap->va)[0x8000]; 159 if (badaddr((caddr_t)regs)) 160 return(0); 161 regs[NCR_CFG1 * 4] = 0; 162 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 163 delay(5); 164 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 165 return(0); 166 return(1); 167 } 168 169 /* 170 * Attach this instance, and then all the sub-devices 171 */ 172 void 173 bzivscattach(parent, self, aux) 174 struct device *parent, *self; 175 void *aux; 176 { 177 struct bzivsc_softc *bsc = (void *)self; 178 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 179 struct zbus_args *zap; 180 extern u_long scsi_nosync; 181 extern int shift_nosync; 182 extern int ncr53c9x_debug; 183 184 /* 185 * Set up the glue for MI code early; we use some of it here. 186 */ 187 sc->sc_glue = &bzivsc_glue; 188 189 /* 190 * Save the regs 191 */ 192 zap = aux; 193 bsc->sc_reg = &((volatile u_char *)zap->va)[0x8000]; 194 bsc->sc_dmabase = &bsc->sc_reg[0x8000]; 195 196 sc->sc_freq = 40; /* Clocked at 40Mhz */ 197 198 printf(": address %p", bsc->sc_reg); 199 200 sc->sc_id = 7; 201 202 /* 203 * It is necessary to try to load the 2nd config register here, 204 * to find out what rev the FAS chip is, else the ncr53c9x_reset 205 * will not set up the defaults correctly. 206 */ 207 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 208 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 209 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 210 sc->sc_rev = NCR_VARIANT_FAS216; 211 212 /* 213 * This is the value used to start sync negotiations 214 * Note that the NCR register "SYNCTP" is programmed 215 * in "clocks per byte", and has a minimum value of 4. 216 * The SCSI period used in negotiation is one-fourth 217 * of the time (in nanoseconds) needed to transfer one byte. 218 * Since the chip's clock is given in MHz, we have the following 219 * formula: 4 * period = (1000 / freq) * 4 220 */ 221 sc->sc_minsync = 1000 / sc->sc_freq; 222 223 /* 224 * get flags from -I argument and set cf_flags. 225 * NOTE: low 8 bits are to disable disconnect, and the next 226 * 8 bits are to disable sync. 227 */ 228 sc->sc_dev.dv_cfdata->cf_flags |= (scsi_nosync >> shift_nosync) 229 & 0xffff; 230 shift_nosync += 16; 231 232 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 233 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 234 shift_nosync += 16; 235 236 #if 1 237 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 238 sc->sc_minsync = 0; 239 #endif 240 241 /* Really no limit, but since we want to fit into the TCR... */ 242 sc->sc_maxxfer = 64 * 1024; 243 244 /* 245 * Configure interrupts. 246 */ 247 bsc->sc_isr.isr_intr = (int (*)(void *))ncr53c9x_intr; 248 bsc->sc_isr.isr_arg = sc; 249 bsc->sc_isr.isr_ipl = 2; 250 add_isr(&bsc->sc_isr); 251 252 /* 253 * Now try to attach all the sub-devices 254 */ 255 ncr53c9x_attach(sc, &bzivsc_switch, &bzivsc_dev); 256 } 257 258 /* 259 * Glue functions. 260 */ 261 262 u_char 263 bzivsc_read_reg(sc, reg) 264 struct ncr53c9x_softc *sc; 265 int reg; 266 { 267 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 268 269 return bsc->sc_reg[reg * 4]; 270 } 271 272 void 273 bzivsc_write_reg(sc, reg, val) 274 struct ncr53c9x_softc *sc; 275 int reg; 276 u_char val; 277 { 278 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 279 u_char v = val; 280 281 bsc->sc_reg[reg * 4] = v; 282 #ifdef DEBUG 283 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL*/ && 284 reg == NCR_CMD/* && bsc->sc_active*/) { 285 bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v; 286 /* printf(" cmd %x", v);*/ 287 } 288 #endif 289 } 290 291 int 292 bzivsc_dma_isintr(sc) 293 struct ncr53c9x_softc *sc; 294 { 295 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 296 297 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 298 return 0; 299 300 #ifdef DEBUG 301 if (/*sc->sc_nexus && sc->sc_nexus->xs->flags & SCSI_POLL &&*/ bzivsc_trace_enable) { 302 bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 303 bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 304 bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active; 305 bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127; 306 } 307 #endif 308 return 1; 309 } 310 311 void 312 bzivsc_dma_reset(sc) 313 struct ncr53c9x_softc *sc; 314 { 315 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 316 317 bsc->sc_active = 0; 318 } 319 320 int 321 bzivsc_dma_intr(sc) 322 struct ncr53c9x_softc *sc; 323 { 324 register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 325 register int cnt; 326 327 NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ", 328 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 329 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 330 if (bsc->sc_active == 0) { 331 printf("bzivsc_intr--inactive DMA\n"); 332 return -1; 333 } 334 335 /* update sc_dmaaddr and sc_pdmalen */ 336 cnt = bsc->sc_reg[NCR_TCL * 4]; 337 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 338 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 339 if (!bsc->sc_datain) { 340 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 341 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 342 } 343 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 344 NCR_DMA(("DMA xferred %d\n", cnt)); 345 if (bsc->sc_xfr_align) { 346 bcopy(bsc->sc_alignbuf, *bsc->sc_dmaaddr, cnt); 347 bsc->sc_xfr_align = 0; 348 } 349 *bsc->sc_dmaaddr += cnt; 350 *bsc->sc_pdmalen -= cnt; 351 bsc->sc_active = 0; 352 return 0; 353 } 354 355 int 356 bzivsc_dma_setup(sc, addr, len, datain, dmasize) 357 struct ncr53c9x_softc *sc; 358 caddr_t *addr; 359 size_t *len; 360 int datain; 361 size_t *dmasize; 362 { 363 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 364 vm_offset_t pa; 365 u_char *ptr; 366 size_t xfer; 367 368 bsc->sc_dmaaddr = addr; 369 bsc->sc_pdmalen = len; 370 bsc->sc_datain = datain; 371 bsc->sc_dmasize = *dmasize; 372 /* 373 * DMA can be nasty for high-speed serial input, so limit the 374 * size of this DMA operation if the serial port is running at 375 * a high speed (higher than 19200 for now - should be adjusted 376 * based on cpu type and speed?). 377 * XXX - add serial speed check XXX 378 */ 379 if (ser_open_speed > 19200 && bzivsc_max_dma != 0 && 380 bsc->sc_dmasize > bzivsc_max_dma) 381 bsc->sc_dmasize = bzivsc_max_dma; 382 ptr = *addr; /* Kernel virtual address */ 383 pa = kvtop(ptr); /* Physical address of DMA */ 384 xfer = min(bsc->sc_dmasize, NBPG - (pa & (NBPG - 1))); 385 bsc->sc_xfr_align = 0; 386 /* 387 * If output and unaligned, stuff odd byte into FIFO 388 */ 389 if (datain == 0 && (int)ptr & 1) { 390 NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n")); 391 pa++; 392 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 393 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 394 } 395 /* 396 * If unaligned address, read unaligned bytes into alignment buffer 397 */ 398 else if ((int)ptr & 1) { 399 pa = kvtop((caddr_t)&bsc->sc_alignbuf); 400 xfer = bsc->sc_dmasize = min(xfer, sizeof (bsc->sc_alignbuf)); 401 NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer)); 402 bsc->sc_xfr_align = 1; 403 } 404 ++bzivsc_cnt_dma; /* number of DMA operations */ 405 406 while (xfer < bsc->sc_dmasize) { 407 if ((pa + xfer) != kvtop(*addr + xfer)) 408 break; 409 if ((bsc->sc_dmasize - xfer) < NBPG) 410 xfer = bsc->sc_dmasize; 411 else 412 xfer += NBPG; 413 ++bzivsc_cnt_dma3; 414 } 415 if (xfer != *len) 416 ++bzivsc_cnt_dma2; 417 418 bsc->sc_dmasize = xfer; 419 *dmasize = bsc->sc_dmasize; 420 bsc->sc_pa = pa; 421 #if defined(M68040) || defined(M68060) 422 if (mmutype == MMU_68040) { 423 if (bsc->sc_xfr_align) { 424 dma_cachectl(bsc->sc_alignbuf, 425 sizeof(bsc->sc_alignbuf)); 426 } 427 else 428 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 429 } 430 #endif 431 432 pa >>= 1; 433 if (!bsc->sc_datain) 434 pa |= 0x80000000; 435 bsc->sc_dmabase[0x8000] = (u_int8_t)(pa >> 24); 436 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 24); 437 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 16); 438 bsc->sc_dmabase[0] = (u_int8_t)(pa >> 8); 439 bsc->sc_dmabase[0] = (u_int8_t)(pa); 440 bsc->sc_active = 1; 441 return 0; 442 } 443 444 void 445 bzivsc_dma_go(sc) 446 struct ncr53c9x_softc *sc; 447 { 448 } 449 450 void 451 bzivsc_dma_stop(sc) 452 struct ncr53c9x_softc *sc; 453 { 454 } 455 456 int 457 bzivsc_dma_isactive(sc) 458 struct ncr53c9x_softc *sc; 459 { 460 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 461 462 return bsc->sc_active; 463 } 464 465 #ifdef DEBUG 466 void 467 bzivsc_dump() 468 { 469 int i; 470 471 i = bzivsc_trace_ptr; 472 printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr); 473 do { 474 if (bzivsc_trace[i].hardbits == 0) { 475 i = (i + 1) & 127; 476 continue; 477 } 478 printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits, 479 bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy); 480 if (bzivsc_trace[i].status & NCRSTAT_INT) 481 printf("NCRINT/"); 482 if (bzivsc_trace[i].status & NCRSTAT_TC) 483 printf("NCRTC/"); 484 switch(bzivsc_trace[i].status & NCRSTAT_PHASE) { 485 case 0: 486 printf("dataout"); break; 487 case 1: 488 printf("datain"); break; 489 case 2: 490 printf("cmdout"); break; 491 case 3: 492 printf("status"); break; 493 case 6: 494 printf("msgout"); break; 495 case 7: 496 printf("msgin"); break; 497 default: 498 printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE); 499 } 500 printf(") "); 501 i = (i + 1) & 127; 502 } while (i != bzivsc_trace_ptr); 503 printf("\n"); 504 } 505 #endif 506