1 /* $NetBSD: bzivsc.c,v 1.26 2008/04/13 04:55:52 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product contains software written by Michael L. Hitch for 19 * the NetBSD project. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: bzivsc.c,v 1.26 2008/04/13 04:55:52 tsutsui Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/ioctl.h> 47 #include <sys/device.h> 48 #include <sys/buf.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/queue.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <dev/scsipi/scsi_all.h> 56 #include <dev/scsipi/scsipi_all.h> 57 #include <dev/scsipi/scsiconf.h> 58 #include <dev/scsipi/scsi_message.h> 59 60 #include <machine/cpu.h> 61 #include <machine/param.h> 62 63 #include <dev/ic/ncr53c9xreg.h> 64 #include <dev/ic/ncr53c9xvar.h> 65 66 #include <amiga/amiga/isr.h> 67 #include <amiga/dev/bzivscvar.h> 68 #include <amiga/dev/zbusvar.h> 69 70 #ifdef __powerpc__ 71 #define badaddr(a) badaddr_read(a, 2, NULL) 72 #endif 73 74 int bzivscmatch(device_t, cfdata_t, void *); 75 void bzivscattach(device_t, device_t, void *); 76 77 /* Linkup to the rest of the kernel */ 78 CFATTACH_DECL_NEW(bzivsc, sizeof(struct bzivsc_softc), 79 bzivscmatch, bzivscattach, NULL, NULL); 80 81 /* 82 * Functions and the switch for the MI code. 83 */ 84 uint8_t bzivsc_read_reg(struct ncr53c9x_softc *, int); 85 void bzivsc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 86 int bzivsc_dma_isintr(struct ncr53c9x_softc *); 87 void bzivsc_dma_reset(struct ncr53c9x_softc *); 88 int bzivsc_dma_intr(struct ncr53c9x_softc *); 89 int bzivsc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 90 size_t *, int, size_t *); 91 void bzivsc_dma_go(struct ncr53c9x_softc *); 92 void bzivsc_dma_stop(struct ncr53c9x_softc *); 93 int bzivsc_dma_isactive(struct ncr53c9x_softc *); 94 95 struct ncr53c9x_glue bzivsc_glue = { 96 bzivsc_read_reg, 97 bzivsc_write_reg, 98 bzivsc_dma_isintr, 99 bzivsc_dma_reset, 100 bzivsc_dma_intr, 101 bzivsc_dma_setup, 102 bzivsc_dma_go, 103 bzivsc_dma_stop, 104 bzivsc_dma_isactive, 105 NULL, 106 }; 107 108 /* Maximum DMA transfer length to reduce impact on high-speed serial input */ 109 u_long bzivsc_max_dma = 1024; 110 extern int ser_open_speed; 111 112 u_long bzivsc_cnt_pio = 0; /* number of PIO transfers */ 113 u_long bzivsc_cnt_dma = 0; /* number of DMA transfers */ 114 u_long bzivsc_cnt_dma2 = 0; /* number of DMA transfers broken up */ 115 u_long bzivsc_cnt_dma3 = 0; /* number of pages combined */ 116 117 #ifdef DEBUG 118 struct { 119 uint8_t hardbits; 120 uint8_t status; 121 uint8_t xx; 122 uint8_t yy; 123 } bzivsc_trace[128]; 124 int bzivsc_trace_ptr = 0; 125 int bzivsc_trace_enable = 1; 126 void bzivsc_dump(void); 127 #endif 128 129 /* 130 * if we are a Phase5 Blizzard 12x0-IV 131 */ 132 int 133 bzivscmatch(device_t parent, cfdata_t cf, void *aux) 134 { 135 struct zbus_args *zap; 136 volatile uint8_t *regs; 137 138 zap = aux; 139 if (zap->manid != 0x2140) 140 return 0; /* It's not Phase 5 */ 141 if (zap->prodid != 11 && zap->prodid != 17) 142 return 0; /* Not Blizzard 12x0 */ 143 if (!is_a1200()) 144 return 0; /* And not A1200 */ 145 regs = &((volatile u_char *)zap->va)[0x8000]; 146 if (badaddr((void *)__UNVOLATILE(regs))) 147 return 0; 148 regs[NCR_CFG1 * 4] = 0; 149 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7; 150 delay(5); 151 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7)) 152 return 0; 153 return 1; 154 } 155 156 /* 157 * Attach this instance, and then all the sub-devices 158 */ 159 void 160 bzivscattach(device_t parent, device_t self, void *aux) 161 { 162 struct bzivsc_softc *bsc = device_private(self); 163 struct ncr53c9x_softc *sc = &bsc->sc_ncr53c9x; 164 struct zbus_args *zap; 165 extern u_long scsi_nosync; 166 extern int shift_nosync; 167 extern int ncr53c9x_debug; 168 169 /* 170 * Set up the glue for MI code early; we use some of it here. 171 */ 172 sc->sc_dev = self; 173 sc->sc_glue = &bzivsc_glue; 174 175 /* 176 * Save the regs 177 */ 178 zap = aux; 179 bsc->sc_reg = &((volatile uint8_t *)zap->va)[0x8000]; 180 bsc->sc_dmabase = &bsc->sc_reg[0x8000]; 181 182 sc->sc_freq = 40; /* Clocked at 40 MHz */ 183 184 aprint_normal(": address %p", bsc->sc_reg); 185 186 sc->sc_id = 7; 187 188 /* 189 * It is necessary to try to load the 2nd config register here, 190 * to find out what rev the FAS chip is, else the ncr53c9x_reset 191 * will not set up the defaults correctly. 192 */ 193 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 194 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 195 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB; 196 sc->sc_rev = NCR_VARIANT_FAS216; 197 198 /* 199 * This is the value used to start sync negotiations 200 * Note that the NCR register "SYNCTP" is programmed 201 * in "clocks per byte", and has a minimum value of 4. 202 * The SCSI period used in negotiation is one-fourth 203 * of the time (in nanoseconds) needed to transfer one byte. 204 * Since the chip's clock is given in MHz, we have the following 205 * formula: 4 * period = (1000 / freq) * 4 206 */ 207 sc->sc_minsync = 1000 / sc->sc_freq; 208 209 /* 210 * get flags from -I argument and set cf_flags. 211 * NOTE: low 8 bits are to disable disconnect, and the next 212 * 8 bits are to disable sync. 213 */ 214 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync) 215 & 0xffff; 216 shift_nosync += 16; 217 218 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */ 219 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff; 220 shift_nosync += 16; 221 222 #if 1 223 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00) 224 sc->sc_minsync = 0; 225 #endif 226 227 /* Really no limit, but since we want to fit into the TCR... */ 228 sc->sc_maxxfer = 64 * 1024; 229 230 /* 231 * Configure interrupts. 232 */ 233 bsc->sc_isr.isr_intr = ncr53c9x_intr; 234 bsc->sc_isr.isr_arg = sc; 235 bsc->sc_isr.isr_ipl = 2; 236 add_isr(&bsc->sc_isr); 237 238 /* 239 * Now try to attach all the sub-devices 240 */ 241 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 242 sc->sc_adapter.adapt_minphys = minphys; 243 ncr53c9x_attach(sc); 244 } 245 246 /* 247 * Glue functions. 248 */ 249 250 uint8_t 251 bzivsc_read_reg(struct ncr53c9x_softc *sc, int reg) 252 { 253 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 254 255 return bsc->sc_reg[reg * 4]; 256 } 257 258 void 259 bzivsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 260 { 261 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 262 uint8_t v = val; 263 264 bsc->sc_reg[reg * 4] = v; 265 #ifdef DEBUG 266 if (bzivsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL */ && 267 reg == NCR_CMD/* && bsc->sc_active*/) { 268 bzivsc_trace[(bzivsc_trace_ptr - 1) & 127].yy = v; 269 /* printf(" cmd %x", v);*/ 270 } 271 #endif 272 } 273 274 int 275 bzivsc_dma_isintr(struct ncr53c9x_softc *sc) 276 { 277 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 278 279 if ((bsc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0) 280 return 0; 281 282 #ifdef DEBUG 283 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ bzivsc_trace_enable) { 284 bzivsc_trace[bzivsc_trace_ptr].status = bsc->sc_reg[NCR_STAT * 4]; 285 bzivsc_trace[bzivsc_trace_ptr].xx = bsc->sc_reg[NCR_CMD * 4]; 286 bzivsc_trace[bzivsc_trace_ptr].yy = bsc->sc_active; 287 bzivsc_trace_ptr = (bzivsc_trace_ptr + 1) & 127; 288 } 289 #endif 290 return 1; 291 } 292 293 void 294 bzivsc_dma_reset(struct ncr53c9x_softc *sc) 295 { 296 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 297 298 bsc->sc_active = 0; 299 } 300 301 int 302 bzivsc_dma_intr(struct ncr53c9x_softc *sc) 303 { 304 register struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 305 register int cnt; 306 307 NCR_DMA(("bzivsc_dma_intr: cnt %d int %x stat %x fifo %d ", 308 bsc->sc_dmasize, sc->sc_espintr, sc->sc_espstat, 309 bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF)); 310 if (bsc->sc_active == 0) { 311 printf("bzivsc_intr--inactive DMA\n"); 312 return -1; 313 } 314 315 /* update sc_dmaaddr and sc_pdmalen */ 316 cnt = bsc->sc_reg[NCR_TCL * 4]; 317 cnt += bsc->sc_reg[NCR_TCM * 4] << 8; 318 cnt += bsc->sc_reg[NCR_TCH * 4] << 16; 319 if (!bsc->sc_datain) { 320 cnt += bsc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF; 321 bsc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH; 322 } 323 cnt = bsc->sc_dmasize - cnt; /* number of bytes transferred */ 324 NCR_DMA(("DMA xferred %d\n", cnt)); 325 if (bsc->sc_xfr_align) { 326 memcpy(*bsc->sc_dmaaddr, bsc->sc_alignbuf, cnt); 327 bsc->sc_xfr_align = 0; 328 } 329 *bsc->sc_dmaaddr += cnt; 330 *bsc->sc_pdmalen -= cnt; 331 bsc->sc_active = 0; 332 return 0; 333 } 334 335 int 336 bzivsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 337 int datain, size_t *dmasize) 338 { 339 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 340 paddr_t pa; 341 uint8_t *ptr; 342 size_t xfer; 343 344 bsc->sc_dmaaddr = addr; 345 bsc->sc_pdmalen = len; 346 bsc->sc_datain = datain; 347 bsc->sc_dmasize = *dmasize; 348 /* 349 * DMA can be nasty for high-speed serial input, so limit the 350 * size of this DMA operation if the serial port is running at 351 * a high speed (higher than 19200 for now - should be adjusted 352 * based on CPU type and speed?). 353 * XXX - add serial speed check XXX 354 */ 355 if (ser_open_speed > 19200 && bzivsc_max_dma != 0 && 356 bsc->sc_dmasize > bzivsc_max_dma) 357 bsc->sc_dmasize = bzivsc_max_dma; 358 ptr = *addr; /* Kernel virtual address */ 359 pa = kvtop(ptr); /* Physical address of DMA */ 360 xfer = min(bsc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1))); 361 bsc->sc_xfr_align = 0; 362 /* 363 * If output and unaligned, stuff odd byte into FIFO 364 */ 365 if (datain == 0 && (int)ptr & 1) { 366 NCR_DMA(("bzivsc_dma_setup: align byte written to fifo\n")); 367 pa++; 368 xfer--; /* XXXX CHECK THIS !!!! XXXX */ 369 bsc->sc_reg[NCR_FIFO * 4] = *ptr++; 370 } 371 /* 372 * If unaligned address, read unaligned bytes into alignment buffer 373 */ 374 else if ((int)ptr & 1) { 375 pa = kvtop((void *)&bsc->sc_alignbuf); 376 xfer = bsc->sc_dmasize = min(xfer, sizeof(bsc->sc_alignbuf)); 377 NCR_DMA(("bzivsc_dma_setup: align read by %d bytes\n", xfer)); 378 bsc->sc_xfr_align = 1; 379 } 380 ++bzivsc_cnt_dma; /* number of DMA operations */ 381 382 while (xfer < bsc->sc_dmasize) { 383 if ((pa + xfer) != kvtop(*addr + xfer)) 384 break; 385 if ((bsc->sc_dmasize - xfer) < PAGE_SIZE) 386 xfer = bsc->sc_dmasize; 387 else 388 xfer += PAGE_SIZE; 389 ++bzivsc_cnt_dma3; 390 } 391 if (xfer != *len) 392 ++bzivsc_cnt_dma2; 393 394 bsc->sc_dmasize = xfer; 395 *dmasize = bsc->sc_dmasize; 396 bsc->sc_pa = pa; 397 #if defined(M68040) || defined(M68060) 398 if (mmutype == MMU_68040) { 399 if (bsc->sc_xfr_align) { 400 dma_cachectl(bsc->sc_alignbuf, 401 sizeof(bsc->sc_alignbuf)); 402 } 403 else 404 dma_cachectl(*bsc->sc_dmaaddr, bsc->sc_dmasize); 405 } 406 #endif 407 408 pa >>= 1; 409 if (!bsc->sc_datain) 410 pa |= 0x80000000; 411 bsc->sc_dmabase[0x8000] = (uint8_t)(pa >> 24); 412 bsc->sc_dmabase[0] = (uint8_t)(pa >> 24); 413 bsc->sc_dmabase[0] = (uint8_t)(pa >> 16); 414 bsc->sc_dmabase[0] = (uint8_t)(pa >> 8); 415 bsc->sc_dmabase[0] = (uint8_t)(pa); 416 bsc->sc_active = 1; 417 return 0; 418 } 419 420 void 421 bzivsc_dma_go(struct ncr53c9x_softc *sc) 422 { 423 } 424 425 void 426 bzivsc_dma_stop(struct ncr53c9x_softc *sc) 427 { 428 } 429 430 int 431 bzivsc_dma_isactive(struct ncr53c9x_softc *sc) 432 { 433 struct bzivsc_softc *bsc = (struct bzivsc_softc *)sc; 434 435 return bsc->sc_active; 436 } 437 438 #ifdef DEBUG 439 void 440 bzivsc_dump(void) 441 { 442 int i; 443 444 i = bzivsc_trace_ptr; 445 printf("bzivsc_trace dump: ptr %x\n", bzivsc_trace_ptr); 446 do { 447 if (bzivsc_trace[i].hardbits == 0) { 448 i = (i + 1) & 127; 449 continue; 450 } 451 printf("%02x%02x%02x%02x(", bzivsc_trace[i].hardbits, 452 bzivsc_trace[i].status, bzivsc_trace[i].xx, bzivsc_trace[i].yy); 453 if (bzivsc_trace[i].status & NCRSTAT_INT) 454 printf("NCRINT/"); 455 if (bzivsc_trace[i].status & NCRSTAT_TC) 456 printf("NCRTC/"); 457 switch(bzivsc_trace[i].status & NCRSTAT_PHASE) { 458 case 0: 459 printf("dataout"); break; 460 case 1: 461 printf("datain"); break; 462 case 2: 463 printf("cmdout"); break; 464 case 3: 465 printf("status"); break; 466 case 6: 467 printf("msgout"); break; 468 case 7: 469 printf("msgin"); break; 470 default: 471 printf("phase%d?", bzivsc_trace[i].status & NCRSTAT_PHASE); 472 } 473 printf(") "); 474 i = (i + 1) & 127; 475 } while (i != bzivsc_trace_ptr); 476 printf("\n"); 477 } 478 #endif 479