1 /* $NetBSD: pmap.h,v 1.22 2008/10/26 00:08:15 mrg Exp $ */ 2 3 /* 4 * 5 * Copyright (c) 1997 Charles D. Cranor and Washington University. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgment: 18 * This product includes software developed by Charles D. Cranor and 19 * Washington University. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 2001 Wasabi Systems, Inc. 37 * All rights reserved. 38 * 39 * Written by Frank van der Linden for Wasabi Systems, Inc. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed for the NetBSD Project by 52 * Wasabi Systems, Inc. 53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 54 * or promote products derived from this software without specific prior 55 * written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 67 * POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #ifndef _AMD64_PMAP_H_ 71 #define _AMD64_PMAP_H_ 72 73 #ifdef __x86_64__ 74 75 #if defined(_KERNEL_OPT) 76 #include "opt_xen.h" 77 #endif 78 79 #include <sys/atomic.h> 80 81 #include <machine/pte.h> 82 #include <machine/segments.h> 83 #ifdef _KERNEL 84 #include <machine/cpufunc.h> 85 #endif 86 87 #include <uvm/uvm_object.h> 88 #ifdef XEN 89 #include <xen/xenfunc.h> 90 #include <xen/xenpmap.h> 91 #endif /* XEN */ 92 93 /* 94 * The x86_64 pmap module closely resembles the i386 one. It uses 95 * the same recursive entry scheme, and the same alternate area 96 * trick for accessing non-current pmaps. See the i386 pmap.h 97 * for a description. The obvious difference is that 3 extra 98 * levels of page table need to be dealt with. The level 1 page 99 * table pages are at: 100 * 101 * l1: 0x00007f8000000000 - 0x00007fffffffffff (39 bits, needs PML4 entry) 102 * 103 * The alternate space is at: 104 * 105 * l1: 0xffffff8000000000 - 0xffffffffffffffff (39 bits, needs PML4 entry) 106 * 107 * The rest is kept as physical pages in 3 UVM objects, and is 108 * temporarily mapped for virtual access when needed. 109 * 110 * Note that address space is signed, so the layout for 48 bits is: 111 * 112 * +---------------------------------+ 0xffffffffffffffff 113 * | | 114 * | alt.L1 table (PTE pages) | 115 * | | 116 * +---------------------------------+ 0xffffff8000000000 117 * ~ ~ 118 * | | 119 * | Kernel Space | 120 * | | 121 * | | 122 * +---------------------------------+ 0xffff800000000000 = 0x0000800000000000 123 * | | 124 * | alt.L1 table (PTE pages) | 125 * | | 126 * +---------------------------------+ 0x00007f8000000000 127 * ~ ~ 128 * | | 129 * | User Space | 130 * | | 131 * | | 132 * +---------------------------------+ 0x0000000000000000 133 * 134 * In other words, there is a 'VA hole' at 0x0000800000000000 - 135 * 0xffff800000000000 which will trap, just as on, for example, 136 * sparcv9. 137 * 138 * The unused space can be used if needed, but it adds a little more 139 * complexity to the calculations. 140 */ 141 142 /* 143 * The first generation of Hammer processors can use 48 bits of 144 * virtual memory, and 40 bits of physical memory. This will be 145 * more for later generations. These defines can be changed to 146 * variable names containing the # of bits, extracted from an 147 * extended cpuid instruction (variables are harder to use during 148 * bootstrap, though) 149 */ 150 #define VIRT_BITS 48 151 #define PHYS_BITS 40 152 153 /* 154 * Mask to get rid of the sign-extended part of addresses. 155 */ 156 #define VA_SIGN_MASK 0xffff000000000000 157 #define VA_SIGN_NEG(va) ((va) | VA_SIGN_MASK) 158 /* 159 * XXXfvdl this one's not right. 160 */ 161 #define VA_SIGN_POS(va) ((va) & ~VA_SIGN_MASK) 162 163 #define L4_SLOT_PTE 255 164 #ifndef XEN 165 #define L4_SLOT_KERN 256 166 #else 167 /* Xen use slots 256-272, let's move farther */ 168 #define L4_SLOT_KERN 320 169 #endif 170 #define L4_SLOT_KERNBASE 511 171 #define L4_SLOT_APTE 510 172 173 #define PDIR_SLOT_KERN L4_SLOT_KERN 174 #define PDIR_SLOT_PTE L4_SLOT_PTE 175 #define PDIR_SLOT_APTE L4_SLOT_APTE 176 177 /* 178 * the following defines give the virtual addresses of various MMU 179 * data structures: 180 * PTE_BASE and APTE_BASE: the base VA of the linear PTE mappings 181 * PTD_BASE and APTD_BASE: the base VA of the recursive mapping of the PTD 182 * PDP_PDE and APDP_PDE: the VA of the PDE that points back to the PDP/APDP 183 * 184 */ 185 186 #define PTE_BASE ((pt_entry_t *) (L4_SLOT_PTE * NBPD_L4)) 187 #define APTE_BASE ((pt_entry_t *) (VA_SIGN_NEG((L4_SLOT_APTE * NBPD_L4)))) 188 189 #define L1_BASE PTE_BASE 190 #define AL1_BASE APTE_BASE 191 192 #define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3)) 193 #define L3_BASE ((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2)) 194 #define L4_BASE ((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1)) 195 196 #define AL2_BASE ((pd_entry_t *)((char *)AL1_BASE + L4_SLOT_PTE * NBPD_L3)) 197 #define AL3_BASE ((pd_entry_t *)((char *)AL2_BASE + L4_SLOT_PTE * NBPD_L2)) 198 #define AL4_BASE ((pd_entry_t *)((char *)AL3_BASE + L4_SLOT_PTE * NBPD_L1)) 199 200 #define PDP_PDE (L4_BASE + PDIR_SLOT_PTE) 201 #define APDP_PDE (L4_BASE + PDIR_SLOT_APTE) 202 203 #define PDP_BASE L4_BASE 204 #define APDP_BASE AL4_BASE 205 206 #define NKL4_MAX_ENTRIES (unsigned long)1 207 #define NKL3_MAX_ENTRIES (unsigned long)(NKL4_MAX_ENTRIES * 512) 208 #define NKL2_MAX_ENTRIES (unsigned long)(NKL3_MAX_ENTRIES * 512) 209 #define NKL1_MAX_ENTRIES (unsigned long)(NKL2_MAX_ENTRIES * 512) 210 211 #define NKL4_KIMG_ENTRIES 1 212 #define NKL3_KIMG_ENTRIES 1 213 #define NKL2_KIMG_ENTRIES 10 214 215 /* 216 * Since kva space is below the kernel in its entirety, we start off 217 * with zero entries on each level. 218 */ 219 #define NKL4_START_ENTRIES 0 220 #define NKL3_START_ENTRIES 0 221 #define NKL2_START_ENTRIES 0 222 #define NKL1_START_ENTRIES 0 /* XXX */ 223 224 #define NTOPLEVEL_PDES (PAGE_SIZE / (sizeof (pd_entry_t))) 225 226 #define NPDPG (PAGE_SIZE / sizeof (pd_entry_t)) 227 228 #define PTP_MASK_INITIALIZER { L1_FRAME, L2_FRAME, L3_FRAME, L4_FRAME } 229 #define PTP_SHIFT_INITIALIZER { L1_SHIFT, L2_SHIFT, L3_SHIFT, L4_SHIFT } 230 #define NKPTP_INITIALIZER { NKL1_START_ENTRIES, NKL2_START_ENTRIES, \ 231 NKL3_START_ENTRIES, NKL4_START_ENTRIES } 232 #define NKPTPMAX_INITIALIZER { NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES, \ 233 NKL3_MAX_ENTRIES, NKL4_MAX_ENTRIES } 234 #define NBPD_INITIALIZER { NBPD_L1, NBPD_L2, NBPD_L3, NBPD_L4 } 235 #define PDES_INITIALIZER { L2_BASE, L3_BASE, L4_BASE } 236 #define APDES_INITIALIZER { AL2_BASE, AL3_BASE, AL4_BASE } 237 238 #define PTP_LEVELS 4 239 240 /* 241 * PG_AVAIL usage: we make use of the ignored bits of the PTE 242 */ 243 244 #define PG_W PG_AVAIL1 /* "wired" mapping */ 245 #define PG_PVLIST PG_AVAIL2 /* mapping has entry on pvlist */ 246 /* PG_AVAIL3 not used */ 247 248 #define PG_X 0 /* XXX dummy */ 249 250 /* 251 * Number of PTE's per cache line. 8 byte pte, 64-byte cache line 252 * Used to avoid false sharing of cache lines. 253 */ 254 #define NPTECL 8 255 256 #include <x86/pmap.h> 257 258 #ifndef XEN 259 #define pmap_pa2pte(a) (a) 260 #define pmap_pte2pa(a) ((a) & PG_FRAME) 261 #define pmap_pte_set(p, n) do { *(p) = (n); } while (0) 262 #define pmap_pte_cas(p, o, n) atomic_cas_64((p), (o), (n)) 263 #define pmap_pte_testset(p, n) \ 264 atomic_swap_ulong((volatile unsigned long *)p, n) 265 #define pmap_pte_setbits(p, b) \ 266 atomic_or_ulong((volatile unsigned long *)p, b) 267 #define pmap_pte_clearbits(p, b) \ 268 atomic_and_ulong((volatile unsigned long *)p, ~(b)) 269 #define pmap_pte_flush() /* nothing */ 270 #else 271 static __inline pt_entry_t 272 pmap_pa2pte(paddr_t pa) 273 { 274 return (pt_entry_t)xpmap_ptom_masked(pa); 275 } 276 277 static __inline paddr_t 278 pmap_pte2pa(pt_entry_t pte) 279 { 280 return xpmap_mtop_masked(pte & PG_FRAME); 281 } 282 static __inline void 283 pmap_pte_set(pt_entry_t *pte, pt_entry_t npte) 284 { 285 int s = splvm(); 286 xpq_queue_pte_update(xpmap_ptetomach(pte), npte); 287 splx(s); 288 } 289 290 static __inline pt_entry_t 291 pmap_pte_cas(volatile pt_entry_t *ptep, pt_entry_t o, pt_entry_t n) 292 { 293 int s = splvm(); 294 pt_entry_t opte = *ptep; 295 296 if (opte == o) { 297 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(ptep)), n); 298 xpq_flush_queue(); 299 } 300 splx(s); 301 return opte; 302 } 303 304 static __inline pt_entry_t 305 pmap_pte_testset(volatile pt_entry_t *pte, pt_entry_t npte) 306 { 307 int s = splvm(); 308 pt_entry_t opte = *pte; 309 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), npte); 310 xpq_flush_queue(); 311 splx(s); 312 return opte; 313 } 314 315 static __inline void 316 pmap_pte_setbits(volatile pt_entry_t *pte, pt_entry_t bits) 317 { 318 int s = splvm(); 319 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), (*pte) | bits); 320 xpq_flush_queue(); 321 splx(s); 322 } 323 324 static __inline void 325 pmap_pte_clearbits(volatile pt_entry_t *pte, pt_entry_t bits) 326 { 327 int s = splvm(); 328 xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), 329 (*pte) & ~bits); 330 xpq_flush_queue(); 331 splx(s); 332 } 333 334 static __inline void 335 pmap_pte_flush(void) 336 { 337 int s = splvm(); 338 xpq_flush_queue(); 339 splx(s); 340 } 341 #endif 342 343 void pmap_prealloc_lowmem_ptps(void); 344 void pmap_changeprot_local(vaddr_t, vm_prot_t); 345 346 #else /* __x86_64__ */ 347 348 #include <i386/pmap.h> 349 350 #endif /* __x86_64__ */ 351 352 #endif /* _AMD64_PMAP_H_ */ 353