1 /* $NetBSD: cpufunc.h,v 1.3 2003/05/08 10:27:43 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _AMD64_CPUFUNC_H_ 40 #define _AMD64_CPUFUNC_H_ 41 42 /* 43 * Functions to provide access to i386-specific instructions. 44 */ 45 46 #include <sys/cdefs.h> 47 #include <sys/types.h> 48 49 #include <machine/specialreg.h> 50 51 static __inline void 52 x86_pause(void) 53 { 54 /* nothing */ 55 } 56 57 #ifdef _KERNEL 58 59 extern int cpu_feature; 60 61 static __inline void 62 invlpg(u_int64_t addr) 63 { 64 __asm __volatile("invlpg (%0)" : : "r" (addr) : "memory"); 65 } 66 67 static __inline void 68 lidt(void *p) 69 { 70 __asm __volatile("lidt (%0)" : : "r" (p)); 71 } 72 73 static __inline void 74 lldt(u_short sel) 75 { 76 __asm __volatile("lldt %0" : : "r" (sel)); 77 } 78 79 static __inline void 80 ltr(u_short sel) 81 { 82 __asm __volatile("ltr %0" : : "r" (sel)); 83 } 84 85 static __inline void 86 lcr8(u_int val) 87 { 88 u_int64_t val64 = val; 89 __asm __volatile("movq %0,%%cr8" : : "r" (val64)); 90 } 91 92 /* 93 * Upper 32 bits are reserved anyway, so just keep this 32bits. 94 */ 95 static __inline void 96 lcr0(u_int val) 97 { 98 u_int64_t val64 = val; 99 __asm __volatile("movq %0,%%cr0" : : "r" (val64)); 100 } 101 102 static __inline u_int 103 rcr0(void) 104 { 105 u_int64_t val64; 106 u_int val; 107 __asm __volatile("movq %%cr0,%0" : "=r" (val64)); 108 val = val64; 109 return val; 110 } 111 112 static __inline u_int64_t 113 rcr2(void) 114 { 115 u_int64_t val; 116 __asm __volatile("movq %%cr2,%0" : "=r" (val)); 117 return val; 118 } 119 120 static __inline void 121 lcr3(u_int64_t val) 122 { 123 __asm __volatile("movq %0,%%cr3" : : "r" (val)); 124 } 125 126 static __inline u_int64_t 127 rcr3(void) 128 { 129 u_int64_t val; 130 __asm __volatile("movq %%cr3,%0" : "=r" (val)); 131 return val; 132 } 133 134 /* 135 * Same as for cr0. Don't touch upper 32 bits. 136 */ 137 static __inline void 138 lcr4(u_int val) 139 { 140 u_int64_t val64 = val; 141 142 __asm __volatile("movq %0,%%cr4" : : "r" (val64)); 143 } 144 145 static __inline u_int 146 rcr4(void) 147 { 148 u_int val; 149 u_int64_t val64; 150 __asm __volatile("movq %%cr4,%0" : "=r" (val64)); 151 val = val64; 152 return val; 153 } 154 155 static __inline void 156 tlbflush(void) 157 { 158 u_int64_t val; 159 __asm __volatile("movq %%cr3,%0" : "=r" (val)); 160 __asm __volatile("movq %0,%%cr3" : : "r" (val)); 161 } 162 163 static __inline void 164 tlbflushg(void) 165 { 166 /* 167 * Big hammer: flush all TLB entries, including ones from PTE's 168 * with the G bit set. This should only be necessary if TLB 169 * shootdown falls far behind. 170 * 171 * Intel Architecture Software Developer's Manual, Volume 3, 172 * System Programming, section 9.10, "Invalidating the 173 * Translation Lookaside Buffers (TLBS)": 174 * "The following operations invalidate all TLB entries, irrespective 175 * of the setting of the G flag: 176 * ... 177 * "(P6 family processors only): Writing to control register CR4 to 178 * modify the PSE, PGE, or PAE flag." 179 * 180 * (the alternatives not quoted above are not an option here.) 181 * 182 * If PGE is not in use, we reload CR3 for the benefit of 183 * pre-P6-family processors. 184 */ 185 186 if (cpu_feature & CPUID_PGE) { 187 u_int cr4 = rcr4(); 188 lcr4(cr4 & ~CR4_PGE); 189 lcr4(cr4); 190 } else 191 tlbflush(); 192 } 193 194 #ifdef notyet 195 void setidt __P((int idx, /*XXX*/caddr_t func, int typ, int dpl)); 196 #endif 197 198 199 /* XXXX ought to be in psl.h with spl() functions */ 200 201 static __inline void 202 disable_intr(void) 203 { 204 __asm __volatile("cli"); 205 } 206 207 static __inline void 208 enable_intr(void) 209 { 210 __asm __volatile("sti"); 211 } 212 213 static __inline u_long 214 read_rflags(void) 215 { 216 u_long ef; 217 218 __asm __volatile("pushfq; popq %0" : "=r" (ef)); 219 return (ef); 220 } 221 222 static __inline void 223 write_rflags(u_long ef) 224 { 225 __asm __volatile("pushq %0; popfq" : : "r" (ef)); 226 } 227 228 static __inline u_int64_t 229 rdmsr(u_int msr) 230 { 231 uint32_t hi, lo; 232 __asm __volatile("rdmsr" : "=d" (hi), "=a" (lo) : "c" (msr)); 233 return (((uint64_t)hi << 32) | (uint64_t) lo); 234 } 235 236 static __inline void 237 wrmsr(u_int msr, u_int64_t newval) 238 { 239 __asm __volatile("wrmsr" : 240 : "a" (newval & 0xffffffff), "d" (newval >> 32), "c" (msr)); 241 } 242 243 static __inline void 244 wbinvd(void) 245 { 246 __asm __volatile("wbinvd"); 247 } 248 249 static __inline u_int64_t 250 rdtsc(void) 251 { 252 uint32_t hi, lo; 253 254 __asm __volatile("rdtsc" : "=d" (hi), "=a" (lo)); 255 return (((uint64_t)hi << 32) | (uint64_t) lo); 256 } 257 258 static __inline u_int64_t 259 rdpmc(u_int pmc) 260 { 261 uint32_t hi, lo; 262 263 __asm __volatile("rdpmc" : "=d" (hi), "=a" (lo) : "c" (pmc)); 264 return (((uint64_t)hi << 32) | (uint64_t) lo); 265 } 266 267 /* Break into DDB/KGDB. */ 268 static __inline void 269 breakpoint(void) 270 { 271 __asm __volatile("int $3"); 272 } 273 274 #define read_psl() read_rflags() 275 #define write_psl(x) write_rflags(x) 276 277 #endif /* _KERNEL */ 278 279 #endif /* !_AMD64_CPUFUNC_H_ */ 280