1 /* $NetBSD: cpufunc.h,v 1.9 2006/08/26 20:08:07 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _AMD64_CPUFUNC_H_ 40 #define _AMD64_CPUFUNC_H_ 41 42 /* 43 * Functions to provide access to i386-specific instructions. 44 */ 45 46 #include <sys/cdefs.h> 47 #include <sys/types.h> 48 49 #include <machine/segments.h> 50 #include <machine/specialreg.h> 51 52 static __inline void 53 x86_pause(void) 54 { 55 /* nothing */ 56 } 57 58 /* 59 * XXX if lfence isn't available... 60 * 61 * memory clobber to avoid compiler reordering. 62 */ 63 static __inline void 64 x86_lfence(void) 65 { 66 67 __asm volatile("lfence" : : : "memory"); 68 } 69 70 static __inline void 71 x86_sfence(void) 72 { 73 74 __asm volatile("sfence" : : : "memory"); 75 } 76 77 static __inline void 78 x86_mfence(void) 79 { 80 81 __asm volatile("mfence" : : : "memory"); 82 } 83 84 #ifdef _KERNEL 85 86 extern int cpu_feature; 87 88 static __inline void 89 invlpg(u_int64_t addr) 90 { 91 __asm volatile("invlpg (%0)" : : "r" (addr) : "memory"); 92 } 93 94 static __inline void 95 lidt(struct region_descriptor *region) 96 { 97 __asm volatile("lidt %0" : : "m" (*region)); 98 } 99 100 static __inline void 101 lldt(u_short sel) 102 { 103 __asm volatile("lldt %0" : : "r" (sel)); 104 } 105 106 static __inline void 107 ltr(u_short sel) 108 { 109 __asm volatile("ltr %0" : : "r" (sel)); 110 } 111 112 static __inline void 113 lcr8(u_int val) 114 { 115 u_int64_t val64 = val; 116 __asm volatile("movq %0,%%cr8" : : "r" (val64)); 117 } 118 119 /* 120 * Upper 32 bits are reserved anyway, so just keep this 32bits. 121 */ 122 static __inline void 123 lcr0(u_int val) 124 { 125 u_int64_t val64 = val; 126 __asm volatile("movq %0,%%cr0" : : "r" (val64)); 127 } 128 129 static __inline u_int 130 rcr0(void) 131 { 132 u_int64_t val64; 133 u_int val; 134 __asm volatile("movq %%cr0,%0" : "=r" (val64)); 135 val = val64; 136 return val; 137 } 138 139 static __inline u_int64_t 140 rcr2(void) 141 { 142 u_int64_t val; 143 __asm volatile("movq %%cr2,%0" : "=r" (val)); 144 return val; 145 } 146 147 static __inline void 148 lcr3(u_int64_t val) 149 { 150 __asm volatile("movq %0,%%cr3" : : "r" (val)); 151 } 152 153 static __inline u_int64_t 154 rcr3(void) 155 { 156 u_int64_t val; 157 __asm volatile("movq %%cr3,%0" : "=r" (val)); 158 return val; 159 } 160 161 /* 162 * Same as for cr0. Don't touch upper 32 bits. 163 */ 164 static __inline void 165 lcr4(u_int val) 166 { 167 u_int64_t val64 = val; 168 169 __asm volatile("movq %0,%%cr4" : : "r" (val64)); 170 } 171 172 static __inline u_int 173 rcr4(void) 174 { 175 u_int val; 176 u_int64_t val64; 177 __asm volatile("movq %%cr4,%0" : "=r" (val64)); 178 val = val64; 179 return val; 180 } 181 182 static __inline void 183 tlbflush(void) 184 { 185 u_int64_t val; 186 __asm volatile("movq %%cr3,%0" : "=r" (val)); 187 __asm volatile("movq %0,%%cr3" : : "r" (val)); 188 } 189 190 static __inline void 191 tlbflushg(void) 192 { 193 /* 194 * Big hammer: flush all TLB entries, including ones from PTE's 195 * with the G bit set. This should only be necessary if TLB 196 * shootdown falls far behind. 197 * 198 * Intel Architecture Software Developer's Manual, Volume 3, 199 * System Programming, section 9.10, "Invalidating the 200 * Translation Lookaside Buffers (TLBS)": 201 * "The following operations invalidate all TLB entries, irrespective 202 * of the setting of the G flag: 203 * ... 204 * "(P6 family processors only): Writing to control register CR4 to 205 * modify the PSE, PGE, or PAE flag." 206 * 207 * (the alternatives not quoted above are not an option here.) 208 * 209 * If PGE is not in use, we reload CR3 for the benefit of 210 * pre-P6-family processors. 211 */ 212 213 if (cpu_feature & CPUID_PGE) { 214 u_int cr4 = rcr4(); 215 lcr4(cr4 & ~CR4_PGE); 216 lcr4(cr4); 217 } else 218 tlbflush(); 219 } 220 221 #ifdef notyet 222 void setidt __P((int idx, /*XXX*/caddr_t func, int typ, int dpl)); 223 #endif 224 225 226 /* XXXX ought to be in psl.h with spl() functions */ 227 228 static __inline void 229 disable_intr(void) 230 { 231 __asm volatile("cli"); 232 } 233 234 static __inline void 235 enable_intr(void) 236 { 237 __asm volatile("sti"); 238 } 239 240 static __inline u_long 241 read_rflags(void) 242 { 243 u_long ef; 244 245 __asm volatile("pushfq; popq %0" : "=r" (ef)); 246 return (ef); 247 } 248 249 static __inline void 250 write_rflags(u_long ef) 251 { 252 __asm volatile("pushq %0; popfq" : : "r" (ef)); 253 } 254 255 static __inline u_int64_t 256 rdmsr(u_int msr) 257 { 258 uint32_t hi, lo; 259 __asm volatile("rdmsr" : "=d" (hi), "=a" (lo) : "c" (msr)); 260 return (((uint64_t)hi << 32) | (uint64_t) lo); 261 } 262 263 static __inline void 264 wrmsr(u_int msr, u_int64_t newval) 265 { 266 __asm volatile("wrmsr" : 267 : "a" (newval & 0xffffffff), "d" (newval >> 32), "c" (msr)); 268 } 269 270 static __inline void 271 wbinvd(void) 272 { 273 __asm volatile("wbinvd"); 274 } 275 276 static __inline u_int64_t 277 rdtsc(void) 278 { 279 uint32_t hi, lo; 280 281 __asm volatile("rdtsc" : "=d" (hi), "=a" (lo)); 282 return (((uint64_t)hi << 32) | (uint64_t) lo); 283 } 284 285 static __inline u_int64_t 286 rdpmc(u_int pmc) 287 { 288 uint32_t hi, lo; 289 290 __asm volatile("rdpmc" : "=d" (hi), "=a" (lo) : "c" (pmc)); 291 return (((uint64_t)hi << 32) | (uint64_t) lo); 292 } 293 294 /* Break into DDB/KGDB. */ 295 static __inline void 296 breakpoint(void) 297 { 298 __asm volatile("int $3"); 299 } 300 301 #define read_psl() read_rflags() 302 #define write_psl(x) write_rflags(x) 303 304 #endif /* _KERNEL */ 305 306 #endif /* !_AMD64_CPUFUNC_H_ */ 307