xref: /netbsd-src/sys/arch/amd64/acpi/acpi_wakecode.S (revision b7b7574d3bf8eeb51a1fa3977b59142ec6434a55)
1/*	$NetBSD: acpi_wakecode.S,v 1.12 2014/01/15 22:24:41 joerg Exp $	*/
2
3/*-
4 * Copyright (c) 2007 Joerg Sonnenberger <joerg@netbsd.org>
5 *
6 * Copyright (c) 2002 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to The NetBSD Foundation
10 * by Takuya SHIOZAKI.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34
35/*
36 * This code is derived from FreeBSD.  Original copyrights:
37 *
38 * Copyright (c) 2001 Takanori Watanabe <takawata@jp.freebsd.org>
39 * Copyright (c) 2001 Mitsuru IWASAKI <iwasaki@jp.freebsd.org>
40 * All rights reserved.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
44 * are met:
45 * 1. Redistributions of source code must retain the above copyright
46 *    notice, this list of conditions and the following disclaimer.
47 * 2. Redistributions in binary form must reproduce the above copyright
48 *    notice, this list of conditions and the following disclaimer in the
49 *    documentation and/or other materials provided with the distribution.
50 *
51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
52 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
53 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
54 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
55 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
56 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
57 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
58 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
59 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
60 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
61 * SUCH DAMAGE.
62 *
63 *	FreeBSD: src/sys/i386/acpica/acpi_wakecode.S,v 1.1 2001/07/20 06:07:31 takawata Exp
64 */
65
66#define _LOCORE
67
68#include <machine/psl.h>
69#include <machine/segments.h>
70#include <machine/specialreg.h>
71
72#define	ACPI_WAKEUP_ADDR	0x3000
73
74	.text
75	.code16
76	.org 0	/* ACPI spec says: cs==(phys>>8), ip==(phys&0x000F) */
77	.globl wakeup_16
78wakeup_16:
79	nop
80	cli
81	cld
82
83	/* Set up segment registers for real mode */
84	movw	%cs,%ax
85	movw	%ax,%ds
86	movw	%ax,%ss
87
88	/* Small call stack */
89	mov	$0x1000,%sp
90
91	/* Clear flags */
92	pushl	$0
93	popfl
94
95	/* Only beep on reset if machdep.acpi_beep_on_reset=1 */
96	cmpb	$1,WAKEUP_beep_on_reset
97	jne	1f
98	movb	$0xc0,%al
99	outb	%al,$0x42
100	movb	$0x04,%al
101	outb	%al,$0x42
102	inb	$0x61,%al
103	orb	$0x3,%al
104	outb	%al,$0x61
1051:
106
107	/* Only reset the VBIOS if machdep.acpi_vbios_reset=1 */
108	cmpb	$1,WAKEUP_vbios_reset
109	jne	1f
110
111	/* Kick the VBIOS. */
112	lcall	$0xc000,$3
113
114	/* Reset registers in case the VBIOS changed them. */
115	movw	%cs,%ax
116	movw	%ax,%ds
117	movw	%ax,%ss
118
119	/* If we need to restore a VESA VBE mode, do it now */
120	cmpb	$0,WAKEUP_vesa_modenum
121	je	1f
122	movw	WAKEUP_vesa_modenum,%bx
123	orw	$0x4000,%bx
124	movw	$0x4f02,%ax
125	int	$0x10
126
127	movw	%cs,%ax
128	movw	%ax,%ds
129	movw	%ax,%ss
1301:
131
132	/* Disable beep again if machdep.acpi_beep_on_reset=1 */
133	cmpb	$1,WAKEUP_beep_on_reset
134	jne	1f
135	inb	$0x61,%al
136	andb	$0xfc,%al
137	outb	%al,$0x61
1381:
139
140	/* Load temporary 32bit GDT */
141#ifdef __clang__
142	lgdt	tmp_gdt
143#else
144	data32 addr32 lgdt	tmp_gdt
145#endif
146
147	/* Enable protected mode w/o paging */
148	mov	%cr0,%eax
149	orl	$(CR0_PE),%eax
150	mov	%eax,%cr0
151
152wakeup_sw32:
153	/*
154	 * Switch to protected mode by intersegmental jump.
155	 * Target and everything else has to compensate for the new origin
156	 * as this is using the flat memory model now.
157	 */
158
159	ljmpl	$0x8,$wakeup_32 + ACPI_WAKEUP_ADDR
160
161	.code32
162	.align	16
163wakeup_32:
164	/*
165	 * Switched to protected mode w/o paging
166	 */
167
168	nop
169	/* Set up segment registers and initial stack for protected mode */
170	movw	$0x10, %ax
171	movw	%ax,%ds
172	movw	%ax,%ss
173
174	movl	$(ACPI_WAKEUP_ADDR + 4096),%esp
175
176	/* First, reset the PSL. */
177	pushl	$PSL_MBO
178	popfl
179
180	/* Enable PAE and potentially PSE */
181	movl	$(CR4_PAE|CR4_OSFXSR|CR4_OSXMMEXCPT|CR4_PSE),%eax
182	movl	%eax,%cr4
183
184	/*
185	 * First switch to Long Mode.  Do not restore the original
186	 * MSR EFER value directly, as enabling the NX bit without
187	 * paging will result in a GPF on AMD CPUs.
188	 *
189	 * Load the correct MSR EFER value now to not depend on the
190	 * data segment register directly after switching to Long Mode.
191	 * After this point, no instruction is allowed to clobber %ebx.
192	 */
193	movl	WAKEUP_efer + ACPI_WAKEUP_ADDR,%ebx
194	movl	$MSR_EFER,%ecx
195	rdmsr
196	orl	$EFER_LME, %eax
197	wrmsr
198
199	/* Load temporary PML4, code will switch to full PML4 later */
200	movl	WAKEUP_r_cr3 + ACPI_WAKEUP_ADDR,%eax
201	movl	%eax,%cr3
202
203	/* Enable paging */
204	movl	%cr0,%eax
205	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP|CR0_AM),%eax
206	movl	%eax,%cr0
207	/* Flush prefetch queue */
208	jmp	1f
2091:
210	/* Switch to temporary 64bit GDT */
211	lgdt	tmp_gdt64 + ACPI_WAKEUP_ADDR
212
213	/* Switch to long mode using intersegmental jump. */
214	ljmp	$0x8, $wakeup_64 + ACPI_WAKEUP_ADDR
215
216	.code64
217wakeup_64:
218
219	/*
220	 * Load the normal system value of MSR EFER.  This includes
221	 * enabling the SYSCALL extension and NXE (if supported).
222	 */
223	movl	%ebx, %eax
224	movl	$MSR_EFER,%ecx
225	wrmsr
226
227	/* Reload data segment with default value */
228	movw	$GSEL(GDATA_SEL, SEL_KPL),%ax
229	movw	%ax,%ds
230
231	movq	WAKEUP_curcpu + ACPI_WAKEUP_ADDR,%r8
232	movq	WAKEUP_restorecpu + ACPI_WAKEUP_ADDR,%rbx
233
234	/* Continue with wakeup in the high-level wakeup code */
235	jmp	*%rbx
236
237	.align	8
238tmp_gdt:
239	.word	0xffff
240	.long	tmp_gdtable + ACPI_WAKEUP_ADDR
241
242	.align	8, 0
243tmp_gdtable:
244	/* null */
245	.word	0, 0
246	.byte	0, 0, 0, 0
247	/* code */
248	.word	0xffff, 0
249	.byte	0, 0x9f, 0xcf, 0
250	/* data */
251	.word	0xffff, 0
252	.byte	0, 0x93, 0xcf, 0
253
254tmp_gdt64:
255	.word 0xffff
256	.long tmp_gdtable64 + ACPI_WAKEUP_ADDR
257
258tmp_gdtable64:
259	.quad 0x0000000000000000
260	.quad 0x00af9a000000ffff
261	.quad 0x00cf92000000ffff
262
263	.align	16, 0
264	.global WAKEUP_r_cr3
265WAKEUP_r_cr3:		.quad 0
266
267	.global WAKEUP_restorecpu
268WAKEUP_restorecpu:	.quad 0
269
270	.global WAKEUP_vbios_reset
271WAKEUP_vbios_reset:	.byte 0
272	.global WAKEUP_vesa_modenum
273WAKEUP_vesa_modenum:    .word 0
274	.global WAKEUP_beep_on_reset
275WAKEUP_beep_on_reset:	.byte 0
276
277	.global WAKEUP_curcpu
278WAKEUP_curcpu:		.quad 0
279	.global WAKEUP_efer
280WAKEUP_efer:		.long 0
281