xref: /netbsd-src/sys/arch/alpha/tlsb/tlsb.c (revision bdc22b2e01993381dcefeff2bc9b56ca75a4235c)
1 /* $NetBSD: tlsb.c,v 1.38 2014/03/26 08:09:06 christos Exp $ */
2 /*
3  * Copyright (c) 1997 by Matthew Jacob
4  * NASA AMES Research Center.
5  * All rights reserved.
6  *
7  * Based in part upon a prototype version by Jason Thorpe
8  * Copyright (c) 1996, 1998 by Jason Thorpe.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice immediately at the beginning of the file, without modification,
15  *    this list of conditions, and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
26  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  */
34 
35 /*
36  * Autoconfiguration and support routines for the TurboLaser System Bus
37  * found on AlphaServer 8200 and 8400 systems.
38  */
39 
40 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
41 
42 __KERNEL_RCSID(0, "$NetBSD: tlsb.c,v 1.38 2014/03/26 08:09:06 christos Exp $");
43 
44 #include "opt_multiprocessor.h"
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49 #include <sys/malloc.h>
50 
51 #include <machine/autoconf.h>
52 #include <machine/cpu.h>
53 #include <machine/cpuvar.h>
54 #include <machine/rpb.h>
55 #include <machine/pte.h>
56 #include <machine/alpha.h>
57 
58 #include <alpha/tlsb/tlsbreg.h>
59 #include <alpha/tlsb/tlsbvar.h>
60 
61 #include "locators.h"
62 
63 #define KV(_addr)	((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
64 
65 static int	tlsbmatch(device_t, cfdata_t, void *);
66 static void	tlsbattach(device_t, device_t, void *);
67 
68 CFATTACH_DECL_NEW(tlsb, 0,
69     tlsbmatch, tlsbattach, NULL, NULL);
70 
71 extern struct cfdriver tlsb_cd;
72 
73 static int	tlsbprint(void *, const char *);
74 static const char *tlsb_node_type_str(uint32_t);
75 
76 /*
77  * There can be only one TurboLaser, and we'll overload it
78  * with a bitmap of found turbo laser nodes. Note that
79  * these are just the actual hard TL node IDS that we
80  * discover here, not the virtual IDs that get assigned
81  * to CPUs. During TLSB specific error handling we
82  * only need to know which actual TLSB slots have boards
83  * in them (irrespective of how many CPUs they have).
84  */
85 int	tlsb_found;
86 
87 static int
88 tlsbprint(void *aux, const char *pnp)
89 {
90 	struct tlsb_dev_attach_args *tap = aux;
91 
92 	if (pnp)
93 		aprint_normal("%s at %s node %d",
94 		    tlsb_node_type_str(tap->ta_dtype), pnp, tap->ta_node);
95 	else
96 		aprint_normal(" node %d: %s", tap->ta_node,
97 		    tlsb_node_type_str(tap->ta_dtype));
98 
99 	return (UNCONF);
100 }
101 
102 static int
103 tlsbmatch(device_t parent, cfdata_t cf, void *aux)
104 {
105 	struct mainbus_attach_args *ma = aux;
106 
107 	/* Make sure we're looking for a TurboLaser. */
108 	if (strcmp(ma->ma_name, tlsb_cd.cd_name) != 0)
109 		return (0);
110 
111 	/*
112 	 * Only one instance of TurboLaser allowed,
113 	 * and only available on 21000 processor type
114 	 * platforms.
115 	 */
116 	if ((cputype != ST_DEC_21000) || tlsb_found)
117 		return (0);
118 
119 	return (1);
120 }
121 
122 static void
123 tlsbattach(device_t parent, device_t self, void *aux)
124 {
125 	struct tlsb_dev_attach_args ta;
126 	uint32_t tldev;
127 	int node;
128 	int locs[TLSBCF_NLOCS];
129 
130 	printf("\n");
131 
132 	/*
133 	 * Attempt to find all devices on the bus, including
134 	 * CPUs, memory modules, and I/O modules.
135 	 */
136 
137 	/*
138 	 * Sigh. I would like to just start off nicely,
139 	 * but I need to treat I/O modules differently-
140 	 * The highest priority I/O node has to be in
141 	 * node #8, and I want to find it *first*, since
142 	 * it will have the primary disks (most likely)
143 	 * on it.
144 	 */
145 	for (node = 0; node <= TLSB_NODE_MAX; ++node) {
146 		/*
147 		 * Check for invalid address.  This may not really
148 		 * be necessary, but what the heck...
149 		 */
150 		if (badaddr(TLSB_NODE_REG_ADDR(node, TLDEV), sizeof(uint32_t)))
151 			continue;
152 		tldev = TLSB_GET_NODEREG(node, TLDEV);
153 		if (tldev == 0) {
154 			/* Nothing at this node. */
155 			continue;
156 		}
157 		/*
158 		 * Store up that we found something at this node.
159 		 * We do this so that we don't have to do something
160 		 * silly at fault time like try a 'baddadr'...
161 		 */
162 		tlsb_found |= (1 << node);
163 		if (TLDEV_ISIOPORT(tldev))
164 			continue;	/* not interested right now */
165 		ta.ta_node = node;
166 		ta.ta_dtype = TLDEV_DTYPE(tldev);
167 		ta.ta_swrev = TLDEV_SWREV(tldev);
168 		ta.ta_hwrev = TLDEV_HWREV(tldev);
169 
170 		/*
171 		 * Deal with hooking CPU instances to TurboLaser nodes.
172 		 */
173 		if (TLDEV_ISCPU(tldev)) {
174 			aprint_normal("%s node %d: %s\n", device_xname(self),
175 			    node, tlsb_node_type_str(tldev));
176 		}
177 		/*
178 		 * Attach any children nodes, including a CPU's GBus
179 		 */
180 		locs[TLSBCF_NODE] = node;
181 		locs[TLSBCF_OFFSET] = 0; /* XXX unused? */
182 
183 		config_found_sm_loc(self, "tlsb", locs, &ta,
184 				    tlsbprint, config_stdsubmatch);
185 	}
186 	/*
187 	 * *Now* search for I/O nodes (in descending order)
188 	 */
189 	while (--node > 0) {
190 		if (badaddr(TLSB_NODE_REG_ADDR(node, TLDEV), sizeof(uint32_t)))
191 			continue;
192 		tldev = TLSB_GET_NODEREG(node, TLDEV);
193 		if (tldev == 0) {
194 			continue;
195 		}
196 		if (TLDEV_ISIOPORT(tldev)) {
197 #if defined(MULTIPROCESSOR)
198 			/*
199 			 * XXX Eventually, we want to select a secondary
200 			 * XXX processor on which to field interrupts for
201 			 * XXX this node.  However, we just send them to
202 			 * XXX the primary CPU for now.
203 			 *
204 			 * XXX Maybe multiple CPUs?  Does the hardware
205 			 * XXX round-robin, or check the length of the
206 			 * XXX per-CPU interrupt queue?
207 			 */
208 			printf("%s node %d: routing interrupts to %s\n",
209 			  device_xname(self), node,
210 			  device_xname(cpu_info[hwrpb->rpb_primary_cpu_id]->ci_softc->sc_dev));
211 			TLSB_PUT_NODEREG(node, TLCPUMASK,
212 			    (1UL << hwrpb->rpb_primary_cpu_id));
213 #else
214 			/*
215 			 * Make sure interrupts are sent to the primary CPU.
216 			 */
217 			TLSB_PUT_NODEREG(node, TLCPUMASK,
218 			    (1UL << hwrpb->rpb_primary_cpu_id));
219 #endif /* MULTIPROCESSOR */
220 
221 			ta.ta_node = node;
222 			ta.ta_dtype = TLDEV_DTYPE(tldev);
223 			ta.ta_swrev = TLDEV_SWREV(tldev);
224 			ta.ta_hwrev = TLDEV_HWREV(tldev);
225 
226 			locs[TLSBCF_NODE] = node;
227 			locs[TLSBCF_OFFSET] = 0; /* XXX unused? */
228 
229 			config_found_sm_loc(self, "tlsb", locs, &ta,
230 					    tlsbprint, config_stdsubmatch);
231 		}
232 	}
233 }
234 
235 static const char *
236 tlsb_node_type_str(uint32_t dtype)
237 {
238 	static char	tlsb_line[64];
239 
240 	switch (dtype & TLDEV_DTYPE_MASK) {
241 	case TLDEV_DTYPE_KFTHA:
242 		return ("KFTHA I/O interface");
243 
244 	case TLDEV_DTYPE_KFTIA:
245 		return ("KFTIA I/O interface");
246 
247 	case TLDEV_DTYPE_MS7CC:
248 		return ("MS7CC Memory Module");
249 
250 	case TLDEV_DTYPE_SCPU4:
251 		return ("Single CPU, 4MB cache");
252 
253 	case TLDEV_DTYPE_SCPU16:
254 		return ("Single CPU, 16MB cache");
255 
256 	case TLDEV_DTYPE_DCPU4:
257 		return ("Dual CPU, 4MB cache");
258 
259 	case TLDEV_DTYPE_DCPU16:
260 		return ("Dual CPU, 16MB cache");
261 
262 	default:
263 		snprintf(tlsb_line, sizeof(tlsb_line), "unknown, dtype 0x%x",
264 		    dtype);
265 		return (tlsb_line);
266 	}
267 	/* NOTREACHED */
268 }
269