xref: /netbsd-src/sys/arch/alpha/tlsb/tlsb.c (revision 8b0f9554ff8762542c4defc4f70e1eb76fb508fa)
1 /* $NetBSD: tlsb.c,v 1.32 2007/03/04 05:59:12 christos Exp $ */
2 /*
3  * Copyright (c) 1997 by Matthew Jacob
4  * NASA AMES Research Center.
5  * All rights reserved.
6  *
7  * Based in part upon a prototype version by Jason Thorpe
8  * Copyright (c) 1996, 1998 by Jason Thorpe.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice immediately at the beginning of the file, without modification,
15  *    this list of conditions, and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
26  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32  * SUCH DAMAGE.
33  */
34 
35 /*
36  * Autoconfiguration and support routines for the TurboLaser System Bus
37  * found on AlphaServer 8200 and 8400 systems.
38  */
39 
40 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
41 
42 __KERNEL_RCSID(0, "$NetBSD: tlsb.c,v 1.32 2007/03/04 05:59:12 christos Exp $");
43 
44 #include "opt_multiprocessor.h"
45 
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/device.h>
49 #include <sys/malloc.h>
50 
51 #include <machine/autoconf.h>
52 #include <machine/cpu.h>
53 #include <machine/cpuvar.h>
54 #include <machine/rpb.h>
55 #include <machine/pte.h>
56 #include <machine/alpha.h>
57 
58 #include <alpha/tlsb/tlsbreg.h>
59 #include <alpha/tlsb/tlsbvar.h>
60 
61 #include "locators.h"
62 
63 #define KV(_addr)	((void *)ALPHA_PHYS_TO_K0SEG((_addr)))
64 
65 static int	tlsbmatch __P((struct device *, struct cfdata *, void *));
66 static void	tlsbattach __P((struct device *, struct device *, void *));
67 
68 CFATTACH_DECL(tlsb, sizeof (struct device),
69     tlsbmatch, tlsbattach, NULL, NULL);
70 
71 extern struct cfdriver tlsb_cd;
72 
73 static int	tlsbprint __P((void *, const char *));
74 static const char *tlsb_node_type_str __P((u_int32_t));
75 
76 /*
77  * There can be only one TurboLaser, and we'll overload it
78  * with a bitmap of found turbo laser nodes. Note that
79  * these are just the actual hard TL node IDS that we
80  * discover here, not the virtual IDs that get assigned
81  * to CPUs. During TLSB specific error handling we
82  * only need to know which actual TLSB slots have boards
83  * in them (irrespective of how many CPUs they have).
84  */
85 int	tlsb_found;
86 
87 static int
88 tlsbprint(aux, pnp)
89 	void *aux;
90 	const char *pnp;
91 {
92 	struct tlsb_dev_attach_args *tap = aux;
93 
94 	if (pnp)
95 		aprint_normal("%s at %s node %d",
96 		    tlsb_node_type_str(tap->ta_dtype), pnp, tap->ta_node);
97 	else
98 		aprint_normal(" node %d: %s", tap->ta_node,
99 		    tlsb_node_type_str(tap->ta_dtype));
100 
101 	return (UNCONF);
102 }
103 
104 static int
105 tlsbmatch(parent, cf, aux)
106 	struct device *parent;
107 	struct cfdata *cf;
108 	void *aux;
109 {
110 	struct mainbus_attach_args *ma = aux;
111 
112 	/* Make sure we're looking for a TurboLaser. */
113 	if (strcmp(ma->ma_name, tlsb_cd.cd_name) != 0)
114 		return (0);
115 
116 	/*
117 	 * Only one instance of TurboLaser allowed,
118 	 * and only available on 21000 processor type
119 	 * platforms.
120 	 */
121 	if ((cputype != ST_DEC_21000) || tlsb_found)
122 		return (0);
123 
124 	return (1);
125 }
126 
127 static void
128 tlsbattach(parent, self, aux)
129 	struct device *parent;
130 	struct device *self;
131 	void *aux;
132 {
133 	struct tlsb_dev_attach_args ta;
134 	u_int32_t tldev;
135 	int node;
136 	int locs[TLSBCF_NLOCS];
137 
138 	printf("\n");
139 
140 	/*
141 	 * Attempt to find all devices on the bus, including
142 	 * CPUs, memory modules, and I/O modules.
143 	 */
144 
145 	/*
146 	 * Sigh. I would like to just start off nicely,
147 	 * but I need to treat I/O modules differently-
148 	 * The highest priority I/O node has to be in
149 	 * node #8, and I want to find it *first*, since
150 	 * it will have the primary disks (most likely)
151 	 * on it.
152 	 */
153 	for (node = 0; node <= TLSB_NODE_MAX; ++node) {
154 		/*
155 		 * Check for invalid address.  This may not really
156 		 * be necessary, but what the heck...
157 		 */
158 		if (badaddr(TLSB_NODE_REG_ADDR(node, TLDEV), sizeof(u_int32_t)))
159 			continue;
160 		tldev = TLSB_GET_NODEREG(node, TLDEV);
161 		if (tldev == 0) {
162 			/* Nothing at this node. */
163 			continue;
164 		}
165 		/*
166 		 * Store up that we found something at this node.
167 		 * We do this so that we don't have to do something
168 		 * silly at fault time like try a 'baddadr'...
169 		 */
170 		tlsb_found |= (1 << node);
171 		if (TLDEV_ISIOPORT(tldev))
172 			continue;	/* not interested right now */
173 		ta.ta_node = node;
174 		ta.ta_dtype = TLDEV_DTYPE(tldev);
175 		ta.ta_swrev = TLDEV_SWREV(tldev);
176 		ta.ta_hwrev = TLDEV_HWREV(tldev);
177 
178 		/*
179 		 * Deal with hooking CPU instances to TurboLaser nodes.
180 		 */
181 		if (TLDEV_ISCPU(tldev)) {
182 			printf("%s node %d: %s\n", self->dv_xname,
183 			    node, tlsb_node_type_str(tldev));
184 		}
185 		/*
186 		 * Attach any children nodes, including a CPU's GBus
187 		 */
188 		locs[TLSBCF_NODE] = node;
189 		locs[TLSBCF_OFFSET] = 0; /* XXX unused? */
190 
191 		config_found_sm_loc(self, "tlsb", locs, &ta,
192 				    tlsbprint, config_stdsubmatch);
193 	}
194 	/*
195 	 * *Now* search for I/O nodes (in descending order)
196 	 */
197 	while (--node > 0) {
198 		if (badaddr(TLSB_NODE_REG_ADDR(node, TLDEV), sizeof(u_int32_t)))
199 			continue;
200 		tldev = TLSB_GET_NODEREG(node, TLDEV);
201 		if (tldev == 0) {
202 			continue;
203 		}
204 		if (TLDEV_ISIOPORT(tldev)) {
205 #if defined(MULTIPROCESSOR)
206 			/*
207 			 * XXX Eventually, we want to select a secondary
208 			 * XXX processor on which to field interrupts for
209 			 * XXX this node.  However, we just send them to
210 			 * XXX the primary CPU for now.
211 			 *
212 			 * XXX Maybe multiple CPUs?  Does the hardware
213 			 * XXX round-robin, or check the length of the
214 			 * XXX per-CPU interrupt queue?
215 			 */
216 			printf("%s node %d: routing interrupts to %s\n",
217 			  self->dv_xname, node,
218 			  cpu_info[hwrpb->rpb_primary_cpu_id]->ci_softc->sc_dev.dv_xname);
219 			TLSB_PUT_NODEREG(node, TLCPUMASK,
220 			    (1UL << hwrpb->rpb_primary_cpu_id));
221 #else
222 			/*
223 			 * Make sure interrupts are sent to the primary CPU.
224 			 */
225 			TLSB_PUT_NODEREG(node, TLCPUMASK,
226 			    (1UL << hwrpb->rpb_primary_cpu_id));
227 #endif /* MULTIPROCESSOR */
228 
229 			ta.ta_node = node;
230 			ta.ta_dtype = TLDEV_DTYPE(tldev);
231 			ta.ta_swrev = TLDEV_SWREV(tldev);
232 			ta.ta_hwrev = TLDEV_HWREV(tldev);
233 
234 			locs[TLSBCF_NODE] = node;
235 			locs[TLSBCF_OFFSET] = 0; /* XXX unused? */
236 
237 			config_found_sm_loc(self, "tlsb", locs, &ta,
238 					    tlsbprint, config_stdsubmatch);
239 		}
240 	}
241 }
242 
243 static const char *
244 tlsb_node_type_str(dtype)
245 	u_int32_t dtype;
246 {
247 	static char	tlsb_line[64];
248 
249 	switch (dtype & TLDEV_DTYPE_MASK) {
250 	case TLDEV_DTYPE_KFTHA:
251 		return ("KFTHA I/O interface");
252 
253 	case TLDEV_DTYPE_KFTIA:
254 		return ("KFTIA I/O interface");
255 
256 	case TLDEV_DTYPE_MS7CC:
257 		return ("MS7CC Memory Module");
258 
259 	case TLDEV_DTYPE_SCPU4:
260 		return ("Single CPU, 4MB cache");
261 
262 	case TLDEV_DTYPE_SCPU16:
263 		return ("Single CPU, 16MB cache");
264 
265 	case TLDEV_DTYPE_DCPU4:
266 		return ("Dual CPU, 4MB cache");
267 
268 	case TLDEV_DTYPE_DCPU16:
269 		return ("Dual CPU, 16MB cache");
270 
271 	default:
272 		memset(tlsb_line, 0, sizeof(tlsb_line));
273 		sprintf(tlsb_line, "unknown, dtype 0x%x", dtype);
274 		return (tlsb_line);
275 	}
276 	/* NOTREACHED */
277 }
278