1 /* $NetBSD: ioasic.c,v 1.42 2009/03/14 21:04:03 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Keith Bostic, Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include "opt_dec_3000_300.h" 61 62 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 63 64 __KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.42 2009/03/14 21:04:03 dsl Exp $"); 65 66 #include <sys/param.h> 67 #include <sys/kernel.h> 68 #include <sys/systm.h> 69 #include <sys/device.h> 70 #include <sys/malloc.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/bus.h> 74 #include <machine/pte.h> 75 #include <machine/rpb.h> 76 77 #include <dev/tc/tcvar.h> 78 #include <dev/tc/ioasicreg.h> 79 #include <dev/tc/ioasicvar.h> 80 81 /* Definition of the driver for autoconfig. */ 82 int ioasicmatch(struct device *, struct cfdata *, void *); 83 void ioasicattach(struct device *, struct device *, void *); 84 85 CFATTACH_DECL(ioasic, sizeof(struct ioasic_softc), 86 ioasicmatch, ioasicattach, NULL, NULL); 87 88 int ioasic_intr(void *); 89 int ioasic_intrnull(void *); 90 91 #define C(x) ((void *)(x)) 92 93 #define IOASIC_DEV_LANCE 0 94 #define IOASIC_DEV_SCC0 1 95 #define IOASIC_DEV_SCC1 2 96 #define IOASIC_DEV_ISDN 3 97 98 #define IOASIC_DEV_BOGUS -1 99 100 #define IOASIC_NCOOKIES 4 101 102 struct ioasic_dev ioasic_devs[] = { 103 { "PMAD-BA ", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE), 104 IOASIC_INTR_LANCE, }, 105 { "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0), 106 IOASIC_INTR_SCC_0, }, 107 { "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1), 108 IOASIC_INTR_SCC_1, }, 109 { "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS), 110 0, }, 111 { "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN), 112 IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD, }, 113 }; 114 int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]); 115 116 struct ioasicintr { 117 int (*iai_func)(void *); 118 void *iai_arg; 119 struct evcnt iai_evcnt; 120 } ioasicintrs[IOASIC_NCOOKIES]; 121 122 tc_addr_t ioasic_base; /* XXX XXX XXX */ 123 124 /* There can be only one. */ 125 int ioasicfound; 126 127 int 128 ioasicmatch(struct device *parent, struct cfdata *cfdata, void *aux) 129 { 130 struct tc_attach_args *ta = aux; 131 132 /* Make sure that we're looking for this type of device. */ 133 if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN)) 134 return (0); 135 136 /* Check that it can actually exist. */ 137 if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300)) 138 panic("ioasicmatch: how did we get here?"); 139 140 if (ioasicfound) 141 return (0); 142 143 return (1); 144 } 145 146 void 147 ioasicattach(struct device *parent, struct device *self, void *aux) 148 { 149 struct ioasic_softc *sc = (struct ioasic_softc *)self; 150 struct tc_attach_args *ta = aux; 151 #ifdef DEC_3000_300 152 u_long ssr; 153 #endif 154 u_long i, imsk; 155 const struct evcnt *pevcnt; 156 char *cp; 157 158 ioasicfound = 1; 159 160 sc->sc_bst = ta->ta_memt; 161 if (bus_space_map(ta->ta_memt, ta->ta_addr, 162 0x400000, 0, &sc->sc_bsh)) { 163 printf("%s: unable to map device\n", sc->sc_dv.dv_xname); 164 return; 165 } 166 sc->sc_dmat = ta->ta_dmat; 167 168 ioasic_base = sc->sc_base = ta->ta_addr; /* XXX XXX XXX */ 169 170 #ifdef DEC_3000_300 171 if (cputype == ST_DEC_3000_300) { 172 ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR); 173 ssr |= IOASIC_CSR_FASTMODE; 174 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr); 175 printf(": slow mode\n"); 176 } else 177 #endif 178 printf(": fast mode\n"); 179 180 /* 181 * Turn off all device interrupt bits. 182 * (This does _not_ include 3000/300 TC option slot bits. 183 */ 184 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 185 for (i = 0; i < ioasic_ndevs; i++) 186 imsk &= ~ioasic_devs[i].iad_intrbits; 187 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 188 189 /* 190 * Set up interrupt handlers. 191 */ 192 pevcnt = tc_intr_evcnt(parent, ta->ta_cookie); 193 for (i = 0; i < IOASIC_NCOOKIES; i++) { 194 ioasicintrs[i].iai_func = ioasic_intrnull; 195 ioasicintrs[i].iai_arg = (void *)i; 196 197 cp = malloc(12, M_DEVBUF, M_NOWAIT); 198 if (cp == NULL) 199 panic("ioasicattach"); 200 sprintf(cp, "slot %lu", i); 201 evcnt_attach_dynamic(&ioasicintrs[i].iai_evcnt, 202 EVCNT_TYPE_INTR, pevcnt, self->dv_xname, cp); 203 } 204 tc_intr_establish(parent, ta->ta_cookie, TC_IPL_NONE, ioasic_intr, sc); 205 206 /* 207 * Try to configure each device. 208 */ 209 ioasic_attach_devs(sc, ioasic_devs, ioasic_ndevs); 210 } 211 212 void 213 ioasic_intr_establish(device_t ioa, void *cookie, tc_intrlevel_t level, 214 int (*func)(void *), void *arg) 215 { 216 struct ioasic_softc *sc = device_lookup_private(&ioasic_cd,0); 217 u_long dev, i, imsk; 218 219 dev = (u_long)cookie; 220 #ifdef DIAGNOSTIC 221 /* XXX check cookie. */ 222 #endif 223 224 if (ioasicintrs[dev].iai_func != ioasic_intrnull) 225 panic("ioasic_intr_establish: cookie %lu twice", dev); 226 227 ioasicintrs[dev].iai_func = func; 228 ioasicintrs[dev].iai_arg = arg; 229 230 /* Enable interrupts for the device. */ 231 for (i = 0; i < ioasic_ndevs; i++) 232 if (ioasic_devs[i].iad_cookie == cookie) 233 break; 234 if (i == ioasic_ndevs) 235 panic("ioasic_intr_establish: invalid cookie."); 236 237 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 238 imsk |= ioasic_devs[i].iad_intrbits; 239 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 240 } 241 242 void 243 ioasic_intr_disestablish(device_t ioa, void *cookie) 244 { 245 struct ioasic_softc *sc = device_lookup_private(&ioasic_cd,0); 246 u_long dev, i, imsk; 247 248 dev = (u_long)cookie; 249 #ifdef DIAGNOSTIC 250 /* XXX check cookie. */ 251 #endif 252 253 if (ioasicintrs[dev].iai_func == ioasic_intrnull) 254 panic("ioasic_intr_disestablish: cookie %lu missing intr", dev); 255 256 /* Enable interrupts for the device. */ 257 for (i = 0; i < ioasic_ndevs; i++) 258 if (ioasic_devs[i].iad_cookie == cookie) 259 break; 260 if (i == ioasic_ndevs) 261 panic("ioasic_intr_disestablish: invalid cookie."); 262 263 imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK); 264 imsk &= ~ioasic_devs[i].iad_intrbits; 265 bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk); 266 267 ioasicintrs[dev].iai_func = ioasic_intrnull; 268 ioasicintrs[dev].iai_arg = (void *)dev; 269 } 270 271 int 272 ioasic_intrnull(void *val) 273 { 274 275 panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld", 276 (u_long)val); 277 } 278 279 /* 280 * ASIC interrupt handler. 281 */ 282 int 283 ioasic_intr(void *val) 284 { 285 register struct ioasic_softc *sc = val; 286 register int ifound; 287 int gifound; 288 u_int32_t sir, osir; 289 290 gifound = 0; 291 do { 292 ifound = 0; 293 tc_syncbus(); 294 295 osir = sir = 296 bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR); 297 298 #define INCRINTRCNT(slot) ioasicintrs[slot].iai_evcnt.ev_count++ 299 300 /* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */ 301 #define CHECKINTR(slot, bits, clear) \ 302 if (sir & (bits)) { \ 303 ifound = 1; \ 304 INCRINTRCNT(slot); \ 305 (*ioasicintrs[slot].iai_func) \ 306 (ioasicintrs[slot].iai_arg); \ 307 if (clear) \ 308 sir &= ~(bits); \ 309 } 310 CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0, 0); 311 CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1, 0); 312 CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE, 0); 313 CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN_TXLOAD | 314 IOASIC_INTR_ISDN_RXLOAD | IOASIC_INTR_ISDN_OVRUN, 1); 315 316 if (sir != osir) 317 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 318 IOASIC_INTR, sir); 319 320 gifound |= ifound; 321 } while (ifound); 322 323 return (gifound); 324 } 325