1 /* $NetBSD: tsc.c,v 1.22 2013/09/23 16:50:12 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include "opt_dec_6600.h" 35 36 #include <sys/cdefs.h> 37 38 __KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.22 2013/09/23 16:50:12 tsutsui Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <machine/autoconf.h> 46 #include <machine/rpb.h> 47 #include <machine/sysarch.h> 48 49 #include <dev/isa/isareg.h> 50 #include <dev/isa/isavar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <alpha/pci/tsreg.h> 54 #include <alpha/pci/tsvar.h> 55 56 #ifdef DEC_6600 57 #include <alpha/pci/pci_6600.h> 58 #endif 59 60 #define tsc() { Generate ctags(1) key. } 61 62 static int tscmatch(device_t, cfdata_t, void *); 63 static void tscattach(device_t, device_t, void *); 64 65 CFATTACH_DECL_NEW(tsc, 0, tscmatch, tscattach, NULL, NULL); 66 67 extern struct cfdriver tsc_cd; 68 69 struct tsp_config tsp_configuration[4]; 70 71 static int tscprint(void *, const char *pnp); 72 73 static int tspmatch(device_t, cfdata_t, void *); 74 static void tspattach(device_t, device_t, void *); 75 76 CFATTACH_DECL_NEW(tsp, 0, tspmatch, tspattach, NULL, NULL); 77 78 extern struct cfdriver tsp_cd; 79 80 static int tsp_bus_get_window(int, int, 81 struct alpha_bus_space_translation *); 82 83 /* There can be only one */ 84 static int tscfound; 85 86 /* Which hose is the display console connected to? */ 87 int tsp_console_hose; 88 89 static int 90 tscmatch(device_t parent, cfdata_t match, void *aux) 91 { 92 struct mainbus_attach_args *ma = aux; 93 94 switch (cputype) { 95 case ST_DEC_6600: 96 case ST_DEC_TITAN: 97 return strcmp(ma->ma_name, tsc_cd.cd_name) == 0 && !tscfound; 98 default: 99 return 0; 100 } 101 } 102 103 static void 104 tscattach(device_t parent, device_t self, void * aux) 105 { 106 int i; 107 int nbus; 108 uint64_t csc, aar; 109 struct tsp_attach_args tsp; 110 struct mainbus_attach_args *ma = aux; 111 int titan = cputype == ST_DEC_TITAN; 112 113 tscfound = 1; 114 115 csc = LDQP(TS_C_CSC); 116 117 nbus = 1 + (CSC_BC(csc) >= 2); 118 printf(": 2127%c Core Logic Chipset, Cchip rev %d\n" 119 "%s%d: %c Dchips, %d memory bus%s of %d bytes\n", 120 titan ? '4' : '2', (int)MISC_REV(LDQP(TS_C_MISC)), 121 ma->ma_name, ma->ma_slot, "2448"[CSC_BC(csc)], 122 nbus, nbus > 1 ? "es" : "", 16 + 16 * ((csc & CSC_AW) != 0)); 123 printf("%s%d: arrays present: ", ma->ma_name, ma->ma_slot); 124 for (i = 0; i < 4; ++i) { 125 aar = LDQP(TS_C_AAR0 + i * TS_STEP); 126 printf("%s%dMB%s", i ? ", " : "", (8 << AAR_ASIZ(aar)) & ~0xf, 127 aar & AAR_SPLIT ? " (split)" : ""); 128 } 129 printf(", Dchip 0 rev %d\n", (int)LDQP(TS_D_DREV) & 0xf); 130 131 memset(&tsp, 0, sizeof tsp); 132 tsp.tsp_name = "tsp"; 133 tsp.tsp_slot = 0; 134 135 config_found(self, &tsp, tscprint); 136 if (titan) { 137 tsp.tsp_slot += 2; 138 config_found(self, &tsp, tscprint); 139 } 140 141 if (csc & CSC_P1P) { 142 tsp.tsp_slot = 1; 143 config_found(self, &tsp, tscprint); 144 if (titan) { 145 tsp.tsp_slot += 2; 146 config_found(self, &tsp, tscprint); 147 } 148 } 149 } 150 151 static int 152 tscprint(void *aux, const char *p) 153 { 154 struct tsp_attach_args *tsp = aux; 155 156 if (p) 157 aprint_normal("%s%d at %s", tsp->tsp_name, tsp->tsp_slot, p); 158 return UNCONF; 159 } 160 161 #define tsp() { Generate ctags(1) key. } 162 163 static int 164 tspmatch(device_t parent, cfdata_t match, void *aux) 165 { 166 struct tsp_attach_args *t = aux; 167 168 switch (cputype) { 169 case ST_DEC_6600: 170 case ST_DEC_TITAN: 171 return strcmp(t->tsp_name, tsp_cd.cd_name) == 0; 172 default: 173 return 0; 174 } 175 } 176 177 static void 178 tspattach(device_t parent, device_t self, void *aux) 179 { 180 struct pcibus_attach_args pba; 181 struct tsp_attach_args *t = aux; 182 struct tsp_config *pcp; 183 184 printf("\n"); 185 pcp = tsp_init(1, t->tsp_slot); 186 187 tsp_dma_init(pcp); 188 189 /* 190 * Do PCI memory initialization that needs to be deferred until 191 * malloc is safe. On the Tsunami, we need to do this after 192 * DMA is initialized, as well. 193 */ 194 tsp_bus_mem_init2(&pcp->pc_memt, pcp); 195 196 pci_6600_pickintr(pcp); 197 198 pba.pba_iot = &pcp->pc_iot; 199 pba.pba_memt = &pcp->pc_memt; 200 pba.pba_dmat = 201 alphabus_dma_get_tag(&pcp->pc_dmat_direct, ALPHA_BUS_PCI); 202 pba.pba_dmat64 = NULL; 203 pba.pba_pc = &pcp->pc_pc; 204 pba.pba_bus = 0; 205 pba.pba_bridgetag = NULL; 206 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 207 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 208 config_found_ia(self, "pcibus", &pba, pcibusprint); 209 } 210 211 struct tsp_config * 212 tsp_init(int mallocsafe, int n) 213 /* n: Pchip number */ 214 { 215 struct tsp_config *pcp; 216 int titan = cputype == ST_DEC_TITAN; 217 218 KASSERT(n >= 0 && n < __arraycount(tsp_configuration)); 219 pcp = &tsp_configuration[n]; 220 pcp->pc_pslot = n; 221 pcp->pc_iobase = TS_Pn(n, 0); 222 pcp->pc_csr = S_PAGE(TS_Pn(n & 1, P_CSRBASE)); 223 if (n & 2) { 224 /* `A' port of PA Chip */ 225 pcp->pc_csr++; 226 } 227 if (titan) { 228 /* same address on G and A ports */ 229 pcp->pc_tlbia = &pcp->pc_csr->port.g.tsp_tlbia.tsg_r; 230 } else { 231 pcp->pc_tlbia = &pcp->pc_csr->port.p.tsp_tlbia.tsg_r; 232 } 233 234 if (!pcp->pc_initted) { 235 tsp_bus_io_init(&pcp->pc_iot, pcp); 236 tsp_bus_mem_init(&pcp->pc_memt, pcp); 237 238 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1; 239 alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1; 240 241 alpha_bus_get_window = tsp_bus_get_window; 242 } 243 pcp->pc_mallocsafe = mallocsafe; 244 tsp_pci_init(&pcp->pc_pc, pcp); 245 pcp->pc_initted = 1; 246 return pcp; 247 } 248 249 static int 250 tsp_bus_get_window(int type, int window, 251 struct alpha_bus_space_translation *abst) 252 { 253 struct tsp_config *tsp = &tsp_configuration[tsp_console_hose]; 254 bus_space_tag_t st; 255 int error; 256 257 switch (type) { 258 case ALPHA_BUS_TYPE_PCI_IO: 259 st = &tsp->pc_iot; 260 break; 261 262 case ALPHA_BUS_TYPE_PCI_MEM: 263 st = &tsp->pc_memt; 264 break; 265 266 default: 267 panic("tsp_bus_get_window"); 268 } 269 270 error = alpha_bus_space_get_window(st, window, abst); 271 if (error) 272 return error; 273 274 abst->abst_sys_start = TS_PHYSADDR(abst->abst_sys_start); 275 abst->abst_sys_end = TS_PHYSADDR(abst->abst_sys_end); 276 277 return 0; 278 } 279 280 void 281 tsc_print_dir(unsigned int indent, unsigned long dir) 282 { 283 char buf[60]; 284 285 snprintb(buf, 60, 286 "\177\20" 287 "b\77Internal Cchip asynchronous error\0" 288 "b\76Pchip 0 error\0" 289 "b\75Pchip 1 error\0" 290 "b\74Pchip 2 error\0" 291 "b\73Pchip 3 error\0", 292 dir); 293 IPRINTF(indent, "DIR = %s\n", buf); 294 } 295 296 void 297 tsc_print_misc(unsigned int indent, unsigned long misc) 298 { 299 unsigned long tmp = MISC_NXM_SRC(misc); 300 301 if (!MISC_NXM(misc)) 302 return; 303 304 IPRINTF(indent, "NXM address detected\n"); 305 IPRINTF(indent, "NXM source = %s %lu\n", 306 tmp <= 3 ? "CPU" : "Pchip", tmp <= 3 ? tmp : tmp - 4); 307 } 308