1 /* $NetBSD: sio_pic.c,v 1.34 2005/12/11 12:16:17 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.34 2005/12/11 12:16:17 christos Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 #include <sys/syslog.h> 76 77 #include <machine/intr.h> 78 #include <machine/bus.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/cy82c693reg.h> 85 #include <dev/pci/cy82c693var.h> 86 87 #include <dev/isa/isareg.h> 88 #include <dev/isa/isavar.h> 89 #include <alpha/pci/siovar.h> 90 91 #include "sio.h" 92 93 /* 94 * To add to the long history of wonderful PROM console traits, 95 * AlphaStation PROMs don't reset themselves completely on boot! 96 * Therefore, if an interrupt was turned on when the kernel was 97 * started, we're not going to EVER turn it off... I don't know 98 * what will happen if new interrupts (that the PROM console doesn't 99 * want) are turned on. I'll burn that bridge when I come to it. 100 */ 101 #define BROKEN_PROM_CONSOLE 102 103 /* 104 * Private functions and variables. 105 */ 106 107 bus_space_tag_t sio_iot; 108 pci_chipset_tag_t sio_pc; 109 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2; 110 111 #define ICU_LEN 16 /* number of ISA IRQs */ 112 113 static struct alpha_shared_intr *sio_intr; 114 115 #ifndef STRAY_MAX 116 #define STRAY_MAX 5 117 #endif 118 119 #ifdef BROKEN_PROM_CONSOLE 120 /* 121 * If prom console is broken, must remember the initial interrupt 122 * settings and enforce them. WHEE! 123 */ 124 u_int8_t initial_ocw1[2]; 125 u_int8_t initial_elcr[2]; 126 #endif 127 128 void sio_setirqstat __P((int, int, int)); 129 130 u_int8_t (*sio_read_elcr) __P((int)); 131 void (*sio_write_elcr) __P((int, u_int8_t)); 132 static void specific_eoi __P((int)); 133 #ifdef BROKEN_PROM_CONSOLE 134 void sio_intr_shutdown __P((void *)); 135 #endif 136 137 /******************** i82378 SIO ELCR functions ********************/ 138 139 int i82378_setup_elcr __P((void)); 140 u_int8_t i82378_read_elcr __P((int)); 141 void i82378_write_elcr __P((int, u_int8_t)); 142 143 bus_space_handle_t sio_ioh_elcr; 144 145 int 146 i82378_setup_elcr() 147 { 148 int rv; 149 150 /* 151 * We could probe configuration space to see that there's 152 * actually an SIO present, but we are using this as a 153 * fall-back in case nothing else matches. 154 */ 155 156 rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr); 157 158 if (rv == 0) { 159 sio_read_elcr = i82378_read_elcr; 160 sio_write_elcr = i82378_write_elcr; 161 } 162 163 return (rv); 164 } 165 166 u_int8_t 167 i82378_read_elcr(elcr) 168 int elcr; 169 { 170 171 return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr)); 172 } 173 174 void 175 i82378_write_elcr(elcr, val) 176 int elcr; 177 u_int8_t val; 178 { 179 180 bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val); 181 } 182 183 /******************** Cypress CY82C693 ELCR functions ********************/ 184 185 int cy82c693_setup_elcr __P((void)); 186 u_int8_t cy82c693_read_elcr __P((int)); 187 void cy82c693_write_elcr __P((int, u_int8_t)); 188 189 const struct cy82c693_handle *sio_cy82c693_handle; 190 191 int 192 cy82c693_setup_elcr() 193 { 194 int device, maxndevs; 195 pcitag_t tag; 196 pcireg_t id; 197 198 /* 199 * Search PCI configuration space for a Cypress CY82C693. 200 * 201 * Note we can make some assumptions about our bus number 202 * here, because: 203 * 204 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 205 * 206 * (2) any ISA/EISA bridges must be attached to primary PCI 207 * busses (i.e. bus zero). 208 */ 209 210 maxndevs = pci_bus_maxdevs(sio_pc, 0); 211 212 for (device = 0; device < maxndevs; device++) { 213 tag = pci_make_tag(sio_pc, 0, device, 0); 214 id = pci_conf_read(sio_pc, tag, PCI_ID_REG); 215 216 /* Invalid vendor ID value? */ 217 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 218 continue; 219 /* XXX Not invalid, but we've done this ~forever. */ 220 if (PCI_VENDOR(id) == 0) 221 continue; 222 223 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ || 224 PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693) 225 continue; 226 227 /* 228 * Found one! 229 */ 230 231 #if 0 232 printf("cy82c693_setup_elcr: found 82C693 at device %d\n", 233 device); 234 #endif 235 236 sio_cy82c693_handle = cy82c693_init(sio_iot); 237 sio_read_elcr = cy82c693_read_elcr; 238 sio_write_elcr = cy82c693_write_elcr; 239 240 return (0); 241 } 242 243 /* 244 * Didn't find a CY82C693. 245 */ 246 return (ENODEV); 247 } 248 249 u_int8_t 250 cy82c693_read_elcr(elcr) 251 int elcr; 252 { 253 254 return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr)); 255 } 256 257 void 258 cy82c693_write_elcr(elcr, val) 259 int elcr; 260 u_int8_t val; 261 { 262 263 cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val); 264 } 265 266 /******************** ELCR access function configuration ********************/ 267 268 /* 269 * Put the Intel SIO at the end, so we fall back on it if we don't 270 * find anything else. If any of the non-Intel functions find a 271 * matching device, but are unable to map it for whatever reason, 272 * they should panic. 273 */ 274 275 int (*sio_elcr_setup_funcs[]) __P((void)) = { 276 cy82c693_setup_elcr, 277 i82378_setup_elcr, 278 NULL, 279 }; 280 281 /******************** Shared SIO/Cypress functions ********************/ 282 283 void 284 sio_setirqstat(irq, enabled, type) 285 int irq, enabled; 286 int type; 287 { 288 u_int8_t ocw1[2], elcr[2]; 289 int icu, bit; 290 291 #if 0 292 printf("sio_setirqstat: irq %d: %s, %s\n", irq, 293 enabled ? "enabled" : "disabled", isa_intr_typename(type)); 294 #endif 295 296 icu = irq / 8; 297 bit = irq % 8; 298 299 ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 300 ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 301 elcr[0] = (*sio_read_elcr)(0); /* XXX */ 302 elcr[1] = (*sio_read_elcr)(1); /* XXX */ 303 304 /* 305 * interrupt enable: set bit to mask (disable) interrupt. 306 */ 307 if (enabled) 308 ocw1[icu] &= ~(1 << bit); 309 else 310 ocw1[icu] |= 1 << bit; 311 312 /* 313 * interrupt type select: set bit to get level-triggered. 314 */ 315 if (type == IST_LEVEL) 316 elcr[icu] |= 1 << bit; 317 else 318 elcr[icu] &= ~(1 << bit); 319 320 #ifdef not_here 321 /* see the init function... */ 322 ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */ 323 elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */ 324 elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */ 325 #endif 326 327 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); 328 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); 329 (*sio_write_elcr)(0, elcr[0]); /* XXX */ 330 (*sio_write_elcr)(1, elcr[1]); /* XXX */ 331 } 332 333 void 334 sio_intr_setup(pc, iot) 335 pci_chipset_tag_t pc; 336 bus_space_tag_t iot; 337 { 338 char *cp; 339 int i; 340 341 sio_iot = iot; 342 sio_pc = pc; 343 344 if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) || 345 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2)) 346 panic("sio_intr_setup: can't map ICU I/O ports"); 347 348 for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++) 349 if ((*sio_elcr_setup_funcs[i])() == 0) 350 break; 351 if (sio_elcr_setup_funcs[i] == NULL) 352 panic("sio_intr_setup: can't map ELCR"); 353 354 #ifdef BROKEN_PROM_CONSOLE 355 /* 356 * Remember the initial values, so we can restore them later. 357 */ 358 initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 359 initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 360 initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */ 361 initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */ 362 shutdownhook_establish(sio_intr_shutdown, 0); 363 #endif 364 365 sio_intr = alpha_shared_intr_alloc(ICU_LEN, 8); 366 367 /* 368 * set up initial values for interrupt enables. 369 */ 370 for (i = 0; i < ICU_LEN; i++) { 371 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX); 372 373 cp = alpha_shared_intr_string(sio_intr, i); 374 sprintf(cp, "irq %d", i); 375 evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i), 376 EVCNT_TYPE_INTR, NULL, "isa", cp); 377 378 switch (i) { 379 case 0: 380 case 1: 381 case 8: 382 case 13: 383 /* 384 * IRQs 0, 1, 8, and 13 must always be 385 * edge-triggered. 386 */ 387 sio_setirqstat(i, 0, IST_EDGE); 388 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 389 IST_EDGE); 390 specific_eoi(i); 391 break; 392 393 case 2: 394 /* 395 * IRQ 2 must be edge-triggered, and should be 396 * enabled (otherwise IRQs 8-15 are ignored). 397 */ 398 sio_setirqstat(i, 1, IST_EDGE); 399 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 400 IST_UNUSABLE); 401 break; 402 403 default: 404 /* 405 * Otherwise, disable the IRQ and set its 406 * type to (effectively) "unknown." 407 */ 408 sio_setirqstat(i, 0, IST_NONE); 409 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 410 IST_NONE); 411 specific_eoi(i); 412 break; 413 } 414 } 415 } 416 417 #ifdef BROKEN_PROM_CONSOLE 418 void 419 sio_intr_shutdown(arg) 420 void *arg; 421 { 422 /* 423 * Restore the initial values, to make the PROM happy. 424 */ 425 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]); 426 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]); 427 (*sio_write_elcr)(0, initial_elcr[0]); /* XXX */ 428 (*sio_write_elcr)(1, initial_elcr[1]); /* XXX */ 429 } 430 #endif 431 432 const char * 433 sio_intr_string(v, irq) 434 void *v; 435 int irq; 436 { 437 static char irqstr[12]; /* 8 + 2 + NULL + sanity */ 438 439 if (irq == 0 || irq >= ICU_LEN || irq == 2) 440 panic("sio_intr_string: bogus isa irq 0x%x", irq); 441 442 sprintf(irqstr, "isa irq %d", irq); 443 return (irqstr); 444 } 445 446 const struct evcnt * 447 sio_intr_evcnt(v, irq) 448 void *v; 449 int irq; 450 { 451 452 if (irq == 0 || irq >= ICU_LEN || irq == 2) 453 panic("sio_intr_evcnt: bogus isa irq 0x%x", irq); 454 455 return (alpha_shared_intr_evcnt(sio_intr, irq)); 456 } 457 458 void * 459 sio_intr_establish(v, irq, type, level, fn, arg) 460 void *v, *arg; 461 int irq; 462 int type; 463 int level; 464 int (*fn)(void *); 465 { 466 void *cookie; 467 468 if (irq > ICU_LEN || type == IST_NONE) 469 panic("sio_intr_establish: bogus irq or type"); 470 471 cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn, 472 arg, "isa irq"); 473 474 if (cookie != NULL && 475 alpha_shared_intr_firstactive(sio_intr, irq)) { 476 scb_set(0x800 + SCB_IDXTOVEC(irq), sio_iointr, NULL); 477 sio_setirqstat(irq, 1, 478 alpha_shared_intr_get_sharetype(sio_intr, irq)); 479 } 480 481 return (cookie); 482 } 483 484 void 485 sio_intr_disestablish(v, cookie) 486 void *v; 487 void *cookie; 488 { 489 struct alpha_shared_intrhand *ih = cookie; 490 int s, ist, irq = ih->ih_num; 491 492 s = splhigh(); 493 494 /* Remove it from the link. */ 495 alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq"); 496 497 /* 498 * Decide if we should disable the interrupt. We must ensure 499 * that: 500 * 501 * - An initially-enabled interrupt is never disabled. 502 * - An initially-LT interrupt is never untyped. 503 */ 504 if (alpha_shared_intr_isactive(sio_intr, irq) == 0) { 505 /* 506 * IRQs 0, 1, 8, and 13 must always be edge-triggered 507 * (see setup). 508 */ 509 switch (irq) { 510 case 0: 511 case 1: 512 case 8: 513 case 13: 514 /* 515 * If the interrupt was initially level-triggered 516 * a warning was printed in setup. 517 */ 518 ist = IST_EDGE; 519 break; 520 521 default: 522 ist = IST_NONE; 523 break; 524 } 525 sio_setirqstat(irq, 0, ist); 526 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist); 527 528 /* Release our SCB vector. */ 529 scb_free(0x800 + SCB_IDXTOVEC(irq)); 530 } 531 532 splx(s); 533 } 534 535 void 536 sio_iointr(arg, vec) 537 void *arg; 538 unsigned long vec; 539 { 540 int irq; 541 542 irq = SCB_VECTOIDX(vec - 0x800); 543 544 #ifdef DIAGNOSTIC 545 if (irq > ICU_LEN || irq < 0) 546 panic("sio_iointr: irq out of range (%d)", irq); 547 #endif 548 549 if (!alpha_shared_intr_dispatch(sio_intr, irq)) 550 alpha_shared_intr_stray(sio_intr, irq, "isa irq"); 551 else 552 alpha_shared_intr_reset_strays(sio_intr, irq); 553 554 /* 555 * Some versions of the machines which use the SIO 556 * (or is it some PALcode revisions on those machines?) 557 * require the non-specific EOI to be fed to the PIC(s) 558 * by the interrupt handler. 559 */ 560 specific_eoi(irq); 561 } 562 563 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 564 565 int 566 sio_intr_alloc(v, mask, type, irq) 567 void *v; 568 int mask; 569 int type; 570 int *irq; 571 { 572 int i, tmp, bestirq, count; 573 struct alpha_shared_intrhand **p, *q; 574 575 if (type == IST_NONE) 576 panic("intr_alloc: bogus type"); 577 578 bestirq = -1; 579 count = -1; 580 581 /* some interrupts should never be dynamically allocated */ 582 mask &= 0xdef8; 583 584 /* 585 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 586 * the right answer is to do "breadth-first" searching of devices. 587 */ 588 mask &= 0xefbf; 589 590 for (i = 0; i < ICU_LEN; i++) { 591 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 592 continue; 593 594 switch(sio_intr[i].intr_sharetype) { 595 case IST_NONE: 596 /* 597 * if nothing's using the irq, just return it 598 */ 599 *irq = i; 600 return (0); 601 602 case IST_EDGE: 603 case IST_LEVEL: 604 if (type != sio_intr[i].intr_sharetype) 605 continue; 606 /* 607 * if the irq is shareable, count the number of other 608 * handlers, and if it's smaller than the last irq like 609 * this, remember it 610 * 611 * XXX We should probably also consider the 612 * interrupt level and stick IPL_TTY with other 613 * IPL_TTY, etc. 614 */ 615 for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0; 616 (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++) 617 ; 618 if ((bestirq == -1) || (count > tmp)) { 619 bestirq = i; 620 count = tmp; 621 } 622 break; 623 624 case IST_PULSE: 625 /* this just isn't shareable */ 626 continue; 627 } 628 } 629 630 if (bestirq == -1) 631 return (1); 632 633 *irq = bestirq; 634 635 return (0); 636 } 637 638 static void 639 specific_eoi(irq) 640 int irq; 641 { 642 if (irq > 7) 643 bus_space_write_1(sio_iot, 644 sio_ioh_icu2, 0, 0x60 | (irq & 0x07)); /* XXX */ 645 bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x60 | (irq > 7 ? 2 : irq)); 646 } 647