1 /* $NetBSD: sio_pic.c,v 1.29 2000/12/18 21:49:08 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.29 2000/12/18 21:49:08 thorpej Exp $"); 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/malloc.h> 75 #include <sys/syslog.h> 76 77 #include <machine/intr.h> 78 #include <machine/bus.h> 79 80 #include <dev/pci/pcireg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcidevs.h> 83 84 #include <dev/pci/cy82c693reg.h> 85 #include <dev/pci/cy82c693var.h> 86 87 #include <dev/isa/isareg.h> 88 #include <dev/isa/isavar.h> 89 #include <alpha/pci/siovar.h> 90 91 #include "sio.h" 92 93 /* 94 * To add to the long history of wonderful PROM console traits, 95 * AlphaStation PROMs don't reset themselves completely on boot! 96 * Therefore, if an interrupt was turned on when the kernel was 97 * started, we're not going to EVER turn it off... I don't know 98 * what will happen if new interrupts (that the PROM console doesn't 99 * want) are turned on. I'll burn that bridge when I come to it. 100 */ 101 #define BROKEN_PROM_CONSOLE 102 103 /* 104 * Private functions and variables. 105 */ 106 107 bus_space_tag_t sio_iot; 108 pci_chipset_tag_t sio_pc; 109 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2; 110 111 #define ICU_LEN 16 /* number of ISA IRQs */ 112 113 static struct alpha_shared_intr *sio_intr; 114 115 #ifndef STRAY_MAX 116 #define STRAY_MAX 5 117 #endif 118 119 #ifdef BROKEN_PROM_CONSOLE 120 /* 121 * If prom console is broken, must remember the initial interrupt 122 * settings and enforce them. WHEE! 123 */ 124 #define INITIALLY_ENABLED(irq) \ 125 ((initial_ocw1[(irq) / 8] & (1 << ((irq) % 8))) == 0) 126 #define INITIALLY_LEVEL_TRIGGERED(irq) \ 127 ((initial_elcr[(irq) / 8] & (1 << ((irq) % 8))) != 0) 128 u_int8_t initial_ocw1[2]; 129 u_int8_t initial_elcr[2]; 130 #else 131 #define INITIALLY_ENABLED(irq) ((irq) == 2 ? 1 : 0) 132 #define INITIALLY_LEVEL_TRIGGERED(irq) 0 133 #endif 134 135 void sio_setirqstat __P((int, int, int)); 136 137 u_int8_t (*sio_read_elcr) __P((int)); 138 void (*sio_write_elcr) __P((int, u_int8_t)); 139 static void specific_eoi __P((int)); 140 #ifdef BROKEN_PROM_CONSOLE 141 void sio_intr_shutdown __P((void *)); 142 #endif 143 144 /******************** i82378 SIO ELCR functions ********************/ 145 146 int i82378_setup_elcr __P((void)); 147 u_int8_t i82378_read_elcr __P((int)); 148 void i82378_write_elcr __P((int, u_int8_t)); 149 150 bus_space_handle_t sio_ioh_elcr; 151 152 int 153 i82378_setup_elcr() 154 { 155 int rv; 156 157 /* 158 * We could probe configuration space to see that there's 159 * actually an SIO present, but we are using this as a 160 * fall-back in case nothing else matches. 161 */ 162 163 rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr); 164 165 if (rv == 0) { 166 sio_read_elcr = i82378_read_elcr; 167 sio_write_elcr = i82378_write_elcr; 168 } 169 170 return (rv); 171 } 172 173 u_int8_t 174 i82378_read_elcr(elcr) 175 int elcr; 176 { 177 178 return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr)); 179 } 180 181 void 182 i82378_write_elcr(elcr, val) 183 int elcr; 184 u_int8_t val; 185 { 186 187 bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val); 188 } 189 190 /******************** Cypress CY82C693 ELCR functions ********************/ 191 192 int cy82c693_setup_elcr __P((void)); 193 u_int8_t cy82c693_read_elcr __P((int)); 194 void cy82c693_write_elcr __P((int, u_int8_t)); 195 196 const struct cy82c693_handle *sio_cy82c693_handle; 197 198 int 199 cy82c693_setup_elcr() 200 { 201 int device, maxndevs; 202 pcitag_t tag; 203 pcireg_t id; 204 205 /* 206 * Search PCI configuration space for a Cypress CY82C693. 207 * 208 * Note we can make some assumptions about our bus number 209 * here, because: 210 * 211 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 212 * 213 * (2) any ISA/EISA bridges must be attached to primary PCI 214 * busses (i.e. bus zero). 215 */ 216 217 maxndevs = pci_bus_maxdevs(sio_pc, 0); 218 219 for (device = 0; device < maxndevs; device++) { 220 tag = pci_make_tag(sio_pc, 0, device, 0); 221 id = pci_conf_read(sio_pc, tag, PCI_ID_REG); 222 223 /* Invalid vendor ID value? */ 224 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 225 continue; 226 /* XXX Not invalid, but we've done this ~forever. */ 227 if (PCI_VENDOR(id) == 0) 228 continue; 229 230 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ || 231 PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693) 232 continue; 233 234 /* 235 * Found one! 236 */ 237 238 #if 0 239 printf("cy82c693_setup_elcr: found 82C693 at device %d\n", 240 device); 241 #endif 242 243 sio_cy82c693_handle = cy82c693_init(sio_iot); 244 sio_read_elcr = cy82c693_read_elcr; 245 sio_write_elcr = cy82c693_write_elcr; 246 247 return (0); 248 } 249 250 /* 251 * Didn't find a CY82C693. 252 */ 253 return (ENODEV); 254 } 255 256 u_int8_t 257 cy82c693_read_elcr(elcr) 258 int elcr; 259 { 260 261 return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr)); 262 } 263 264 void 265 cy82c693_write_elcr(elcr, val) 266 int elcr; 267 u_int8_t val; 268 { 269 270 cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val); 271 } 272 273 /******************** ELCR access function configuration ********************/ 274 275 /* 276 * Put the Intel SIO at the end, so we fall back on it if we don't 277 * find anything else. If any of the non-Intel functions find a 278 * matching device, but are unable to map it for whatever reason, 279 * they should panic. 280 */ 281 282 int (*sio_elcr_setup_funcs[]) __P((void)) = { 283 cy82c693_setup_elcr, 284 i82378_setup_elcr, 285 NULL, 286 }; 287 288 /******************** Shared SIO/Cypress functions ********************/ 289 290 void 291 sio_setirqstat(irq, enabled, type) 292 int irq, enabled; 293 int type; 294 { 295 u_int8_t ocw1[2], elcr[2]; 296 int icu, bit; 297 298 #if 0 299 printf("sio_setirqstat: irq %d: %s, %s\n", irq, 300 enabled ? "enabled" : "disabled", isa_intr_typename(type)); 301 #endif 302 303 icu = irq / 8; 304 bit = irq % 8; 305 306 ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 307 ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 308 elcr[0] = (*sio_read_elcr)(0); /* XXX */ 309 elcr[1] = (*sio_read_elcr)(1); /* XXX */ 310 311 /* 312 * interrupt enable: set bit to mask (disable) interrupt. 313 */ 314 if (enabled) 315 ocw1[icu] &= ~(1 << bit); 316 else 317 ocw1[icu] |= 1 << bit; 318 319 /* 320 * interrupt type select: set bit to get level-triggered. 321 */ 322 if (type == IST_LEVEL) 323 elcr[icu] |= 1 << bit; 324 else 325 elcr[icu] &= ~(1 << bit); 326 327 #ifdef not_here 328 /* see the init function... */ 329 ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */ 330 elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */ 331 elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */ 332 #endif 333 334 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); 335 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); 336 (*sio_write_elcr)(0, elcr[0]); /* XXX */ 337 (*sio_write_elcr)(1, elcr[1]); /* XXX */ 338 } 339 340 void 341 sio_intr_setup(pc, iot) 342 pci_chipset_tag_t pc; 343 bus_space_tag_t iot; 344 { 345 char *cp; 346 int i; 347 348 sio_iot = iot; 349 sio_pc = pc; 350 351 if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) || 352 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2)) 353 panic("sio_intr_setup: can't map ICU I/O ports"); 354 355 for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++) 356 if ((*sio_elcr_setup_funcs[i])() == 0) 357 break; 358 if (sio_elcr_setup_funcs[i] == NULL) 359 panic("sio_intr_setup: can't map ELCR"); 360 361 #ifdef BROKEN_PROM_CONSOLE 362 /* 363 * Remember the initial values, so we can restore them later. 364 */ 365 initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 366 initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 367 initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */ 368 initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */ 369 shutdownhook_establish(sio_intr_shutdown, 0); 370 #endif 371 372 sio_intr = alpha_shared_intr_alloc(ICU_LEN, 8); 373 374 /* 375 * set up initial values for interrupt enables. 376 */ 377 for (i = 0; i < ICU_LEN; i++) { 378 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX); 379 380 cp = alpha_shared_intr_string(sio_intr, i); 381 sprintf(cp, "irq %d", i); 382 evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i), 383 EVCNT_TYPE_INTR, NULL, "isa", cp); 384 385 switch (i) { 386 case 0: 387 case 1: 388 case 8: 389 case 13: 390 /* 391 * IRQs 0, 1, 8, and 13 must always be 392 * edge-triggered. 393 */ 394 if (INITIALLY_LEVEL_TRIGGERED(i)) 395 printf("sio_intr_setup: %d level-triggered\n", 396 i); 397 sio_setirqstat(i, INITIALLY_ENABLED(i), IST_EDGE); 398 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 399 IST_EDGE); 400 specific_eoi(i); 401 break; 402 403 case 2: 404 /* 405 * IRQ 2 must be edge-triggered, and should be 406 * enabled (otherwise IRQs 8-15 are ignored). 407 */ 408 sio_setirqstat(i, 1, IST_EDGE); 409 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 410 IST_UNUSABLE); 411 break; 412 413 default: 414 /* 415 * Otherwise, disable the IRQ and set its 416 * type to (effectively) "unknown." 417 */ 418 sio_setirqstat(i, INITIALLY_ENABLED(i), 419 INITIALLY_LEVEL_TRIGGERED(i) ? 420 IST_LEVEL : IST_NONE); 421 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 422 INITIALLY_LEVEL_TRIGGERED(i) ? 423 IST_LEVEL : IST_NONE); 424 specific_eoi(i); 425 break; 426 } 427 } 428 } 429 430 #ifdef BROKEN_PROM_CONSOLE 431 void 432 sio_intr_shutdown(arg) 433 void *arg; 434 { 435 /* 436 * Restore the initial values, to make the PROM happy. 437 */ 438 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]); 439 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]); 440 (*sio_write_elcr)(0, initial_elcr[0]); /* XXX */ 441 (*sio_write_elcr)(1, initial_elcr[1]); /* XXX */ 442 } 443 #endif 444 445 const char * 446 sio_intr_string(v, irq) 447 void *v; 448 int irq; 449 { 450 static char irqstr[12]; /* 8 + 2 + NULL + sanity */ 451 452 if (irq == 0 || irq >= ICU_LEN || irq == 2) 453 panic("sio_intr_string: bogus isa irq 0x%x\n", irq); 454 455 sprintf(irqstr, "isa irq %d", irq); 456 return (irqstr); 457 } 458 459 const struct evcnt * 460 sio_intr_evcnt(v, irq) 461 void *v; 462 int irq; 463 { 464 465 if (irq == 0 || irq >= ICU_LEN || irq == 2) 466 panic("sio_intr_evcnt: bogus isa irq 0x%x\n", irq); 467 468 return (alpha_shared_intr_evcnt(sio_intr, irq)); 469 } 470 471 void * 472 sio_intr_establish(v, irq, type, level, fn, arg) 473 void *v, *arg; 474 int irq; 475 int type; 476 int level; 477 int (*fn)(void *); 478 { 479 void *cookie; 480 481 if (irq > ICU_LEN || type == IST_NONE) 482 panic("sio_intr_establish: bogus irq or type"); 483 484 cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn, 485 arg, "isa irq"); 486 487 if (cookie) 488 sio_setirqstat(irq, alpha_shared_intr_isactive(sio_intr, irq), 489 alpha_shared_intr_get_sharetype(sio_intr, irq)); 490 491 return (cookie); 492 } 493 494 void 495 sio_intr_disestablish(v, cookie) 496 void *v; 497 void *cookie; 498 { 499 struct alpha_shared_intrhand *ih = cookie; 500 int s, ist, irq = ih->ih_num; 501 502 s = splhigh(); 503 504 /* Remove it from the link. */ 505 alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq"); 506 507 /* 508 * Decide if we should disable the interrupt. We must ensure 509 * that: 510 * 511 * - An initially-enabled interrupt is never disabled. 512 * - An initially-LT interrupt is never untyped. 513 */ 514 if (alpha_shared_intr_isactive(sio_intr, irq) == 0) { 515 /* 516 * IRQs 0, 1, 8, and 13 must always be edge-triggered 517 * (see setup). 518 */ 519 switch (irq) { 520 case 0: 521 case 1: 522 case 8: 523 case 13: 524 /* 525 * If the interrupt was initially level-triggered 526 * a warning was printed in setup. 527 */ 528 ist = IST_EDGE; 529 break; 530 531 default: 532 ist = INITIALLY_LEVEL_TRIGGERED(irq) ? 533 IST_LEVEL : IST_NONE; 534 break; 535 } 536 sio_setirqstat(irq, INITIALLY_ENABLED(irq), ist); 537 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist); 538 } 539 540 splx(s); 541 } 542 543 void 544 sio_iointr(framep, vec) 545 void *framep; 546 unsigned long vec; 547 { 548 int irq; 549 550 irq = (vec - 0x800) >> 4; 551 #ifdef DIAGNOSTIC 552 if (irq > ICU_LEN || irq < 0) 553 panic("sio_iointr: irq out of range (%d)", irq); 554 #endif 555 556 if (!alpha_shared_intr_dispatch(sio_intr, irq)) 557 alpha_shared_intr_stray(sio_intr, irq, "isa irq"); 558 559 /* 560 * Some versions of the machines which use the SIO 561 * (or is it some PALcode revisions on those machines?) 562 * require the non-specific EOI to be fed to the PIC(s) 563 * by the interrupt handler. 564 */ 565 specific_eoi(irq); 566 } 567 568 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 569 570 int 571 sio_intr_alloc(v, mask, type, irq) 572 void *v; 573 int mask; 574 int type; 575 int *irq; 576 { 577 int i, tmp, bestirq, count; 578 struct alpha_shared_intrhand **p, *q; 579 580 if (type == IST_NONE) 581 panic("intr_alloc: bogus type"); 582 583 bestirq = -1; 584 count = -1; 585 586 /* some interrupts should never be dynamically allocated */ 587 mask &= 0xdef8; 588 589 /* 590 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 591 * the right answer is to do "breadth-first" searching of devices. 592 */ 593 mask &= 0xefbf; 594 595 for (i = 0; i < ICU_LEN; i++) { 596 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 597 continue; 598 599 switch(sio_intr[i].intr_sharetype) { 600 case IST_NONE: 601 /* 602 * if nothing's using the irq, just return it 603 */ 604 *irq = i; 605 return (0); 606 607 case IST_EDGE: 608 case IST_LEVEL: 609 if (type != sio_intr[i].intr_sharetype) 610 continue; 611 /* 612 * if the irq is shareable, count the number of other 613 * handlers, and if it's smaller than the last irq like 614 * this, remember it 615 * 616 * XXX We should probably also consider the 617 * interrupt level and stick IPL_TTY with other 618 * IPL_TTY, etc. 619 */ 620 for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0; 621 (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++) 622 ; 623 if ((bestirq == -1) || (count > tmp)) { 624 bestirq = i; 625 count = tmp; 626 } 627 break; 628 629 case IST_PULSE: 630 /* this just isn't shareable */ 631 continue; 632 } 633 } 634 635 if (bestirq == -1) 636 return (1); 637 638 *irq = bestirq; 639 640 return (0); 641 } 642 643 static void 644 specific_eoi(irq) 645 int irq; 646 { 647 if (irq > 7) 648 bus_space_write_1(sio_iot, 649 sio_ioh_icu2, 0, 0x20 | (irq & 0x07)); /* XXX */ 650 bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq)); 651 } 652