1 /* $NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.41 2008/04/28 20:23:11 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 34 * All rights reserved. 35 * 36 * Author: Chris G. Demetriou 37 * 38 * Permission to use, copy, modify and distribute this software and 39 * its documentation is hereby granted, provided that both the copyright 40 * notice and this permission notice appear in all copies of the 41 * software, derivative works or modified versions, and any portions 42 * thereof, and that both notices appear in supporting documentation. 43 * 44 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 45 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 46 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 47 * 48 * Carnegie Mellon requests users of this software to return to 49 * 50 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 51 * School of Computer Science 52 * Carnegie Mellon University 53 * Pittsburgh PA 15213-3890 54 * 55 * any improvements or extensions that they make and grant Carnegie the 56 * rights to redistribute these changes. 57 */ 58 59 /* 60 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 61 * deal with only a single PCI interface chip in a machine. 62 * 63 * uses: 64 * CHIP name of the 'chip' it's being compiled for. 65 * CHIP_D_MEM_W1_SYS_START Dense Mem space base to use. 66 * CHIP_D_MEM_EX_STORE 67 * If defined, device-provided static storage area 68 * for the dense memory space extent. If this is 69 * defined, CHIP_D_MEM_EX_STORE_SIZE must also be 70 * defined. If this is not defined, a static area 71 * will be declared. 72 * CHIP_D_MEM_EX_STORE_SIZE 73 * Size of the device-provided static storage area 74 * for the dense memory space extent. 75 * CHIP_S_MEM_BASE Sparse Mem space base to use. 76 * CHIP_S_MEM_EX_STORE 77 * If defined, device-provided static storage area 78 * for the sparse memory space extent. If this is 79 * defined, CHIP_S_MEM_EX_STORE_SIZE must also be 80 * defined. If this is not defined, a static area 81 * will be declared. 82 * CHIP_S_MEM_EX_STORE_SIZE 83 * Size of the device-provided static storage area 84 * for the sparse memory space extent. 85 */ 86 87 #include <sys/cdefs.h> 88 __KERNEL_RCSID(1, "$NetBSD: pci_swiz_bus_mem_chipdep.c,v 1.41 2008/04/28 20:23:11 martin Exp $"); 89 90 #include <sys/extent.h> 91 92 #define __C(A,B) __CONCAT(A,B) 93 #define __S(S) __STRING(S) 94 95 /* mapping/unmapping */ 96 int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int, 97 bus_space_handle_t *, int)); 98 void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t, 99 bus_size_t, int)); 100 int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t, 101 bus_size_t, bus_size_t, bus_space_handle_t *)); 102 103 int __C(CHIP,_mem_translate) __P((void *, bus_addr_t, bus_size_t, 104 int, struct alpha_bus_space_translation *)); 105 int __C(CHIP,_mem_get_window) __P((void *, int, 106 struct alpha_bus_space_translation *)); 107 108 /* allocation/deallocation */ 109 int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t, 110 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 111 bus_space_handle_t *)); 112 void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t, 113 bus_size_t)); 114 115 /* get kernel virtual address */ 116 void * __C(CHIP,_mem_vaddr) __P((void *, bus_space_handle_t)); 117 118 /* mmap for user */ 119 paddr_t __C(CHIP,_mem_mmap) __P((void *, bus_addr_t, off_t, int, int)); 120 121 /* barrier */ 122 inline void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t, 123 bus_size_t, bus_size_t, int)); 124 125 /* read (single) */ 126 inline u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t, 127 bus_size_t)); 128 inline u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t, 129 bus_size_t)); 130 inline u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t, 131 bus_size_t)); 132 inline u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t, 133 bus_size_t)); 134 135 /* read multiple */ 136 void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int8_t *, bus_size_t)); 138 void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t, 139 bus_size_t, u_int16_t *, bus_size_t)); 140 void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int32_t *, bus_size_t)); 142 void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int64_t *, bus_size_t)); 144 145 /* read region */ 146 void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int8_t *, bus_size_t)); 148 void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t, 149 bus_size_t, u_int16_t *, bus_size_t)); 150 void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t, 151 bus_size_t, u_int32_t *, bus_size_t)); 152 void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t, 153 bus_size_t, u_int64_t *, bus_size_t)); 154 155 /* write (single) */ 156 inline void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t, 157 bus_size_t, u_int8_t)); 158 inline void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t, 159 bus_size_t, u_int16_t)); 160 inline void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t, 161 bus_size_t, u_int32_t)); 162 inline void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t, 163 bus_size_t, u_int64_t)); 164 165 /* write multiple */ 166 void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int8_t *, bus_size_t)); 168 void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t, 169 bus_size_t, const u_int16_t *, bus_size_t)); 170 void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t, 171 bus_size_t, const u_int32_t *, bus_size_t)); 172 void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t, 173 bus_size_t, const u_int64_t *, bus_size_t)); 174 175 /* write region */ 176 void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t, 177 bus_size_t, const u_int8_t *, bus_size_t)); 178 void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t, 179 bus_size_t, const u_int16_t *, bus_size_t)); 180 void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t, 181 bus_size_t, const u_int32_t *, bus_size_t)); 182 void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t, 183 bus_size_t, const u_int64_t *, bus_size_t)); 184 185 /* set multiple */ 186 void __C(CHIP,_mem_set_multi_1) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int8_t, bus_size_t)); 188 void __C(CHIP,_mem_set_multi_2) __P((void *, bus_space_handle_t, 189 bus_size_t, u_int16_t, bus_size_t)); 190 void __C(CHIP,_mem_set_multi_4) __P((void *, bus_space_handle_t, 191 bus_size_t, u_int32_t, bus_size_t)); 192 void __C(CHIP,_mem_set_multi_8) __P((void *, bus_space_handle_t, 193 bus_size_t, u_int64_t, bus_size_t)); 194 195 /* set region */ 196 void __C(CHIP,_mem_set_region_1) __P((void *, bus_space_handle_t, 197 bus_size_t, u_int8_t, bus_size_t)); 198 void __C(CHIP,_mem_set_region_2) __P((void *, bus_space_handle_t, 199 bus_size_t, u_int16_t, bus_size_t)); 200 void __C(CHIP,_mem_set_region_4) __P((void *, bus_space_handle_t, 201 bus_size_t, u_int32_t, bus_size_t)); 202 void __C(CHIP,_mem_set_region_8) __P((void *, bus_space_handle_t, 203 bus_size_t, u_int64_t, bus_size_t)); 204 205 /* copy */ 206 void __C(CHIP,_mem_copy_region_1) __P((void *, bus_space_handle_t, 207 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 208 void __C(CHIP,_mem_copy_region_2) __P((void *, bus_space_handle_t, 209 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 210 void __C(CHIP,_mem_copy_region_4) __P((void *, bus_space_handle_t, 211 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 212 void __C(CHIP,_mem_copy_region_8) __P((void *, bus_space_handle_t, 213 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 214 215 #ifdef CHIP_D_MEM_W1_SYS_START 216 #ifndef CHIP_D_MEM_EX_STORE 217 static long 218 __C(CHIP,_dmem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 219 #define CHIP_D_MEM_EX_STORE(v) (__C(CHIP,_dmem_ex_storage)) 220 #define CHIP_D_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_dmem_ex_storage)) 221 #endif 222 #endif /* CHIP_D_MEM_W1_SYS_START */ 223 224 #ifndef CHIP_S_MEM_EX_STORE 225 static long 226 __C(CHIP,_smem_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 227 #define CHIP_S_MEM_EX_STORE(v) (__C(CHIP,_smem_ex_storage)) 228 #define CHIP_S_MEM_EX_STORE_SIZE(v) (sizeof __C(CHIP,_smem_ex_storage)) 229 #endif 230 231 #ifndef CHIP_ADDR_SHIFT 232 #define CHIP_ADDR_SHIFT 5 233 #endif 234 235 #ifndef CHIP_SIZE_SHIFT 236 #define CHIP_SIZE_SHIFT 3 237 #endif 238 239 void 240 __C(CHIP,_bus_mem_init)(t, v) 241 bus_space_tag_t t; 242 void *v; 243 { 244 #ifdef CHIP_D_MEM_W1_SYS_START 245 struct extent *dex; 246 #endif 247 struct extent *sex; 248 249 /* 250 * Initialize the bus space tag. 251 */ 252 253 /* cookie */ 254 t->abs_cookie = v; 255 256 /* mapping/unmapping */ 257 t->abs_map = __C(CHIP,_mem_map); 258 t->abs_unmap = __C(CHIP,_mem_unmap); 259 t->abs_subregion = __C(CHIP,_mem_subregion); 260 261 t->abs_translate = __C(CHIP,_mem_translate); 262 t->abs_get_window = __C(CHIP,_mem_get_window); 263 264 /* allocation/deallocation */ 265 t->abs_alloc = __C(CHIP,_mem_alloc); 266 t->abs_free = __C(CHIP,_mem_free); 267 268 /* get kernel virtual address */ 269 t->abs_vaddr = __C(CHIP,_mem_vaddr); 270 271 /* mmap for user */ 272 t->abs_mmap = __C(CHIP,_mem_mmap); 273 274 /* barrier */ 275 t->abs_barrier = __C(CHIP,_mem_barrier); 276 277 /* read (single) */ 278 t->abs_r_1 = __C(CHIP,_mem_read_1); 279 t->abs_r_2 = __C(CHIP,_mem_read_2); 280 t->abs_r_4 = __C(CHIP,_mem_read_4); 281 t->abs_r_8 = __C(CHIP,_mem_read_8); 282 283 /* read multiple */ 284 t->abs_rm_1 = __C(CHIP,_mem_read_multi_1); 285 t->abs_rm_2 = __C(CHIP,_mem_read_multi_2); 286 t->abs_rm_4 = __C(CHIP,_mem_read_multi_4); 287 t->abs_rm_8 = __C(CHIP,_mem_read_multi_8); 288 289 /* read region */ 290 t->abs_rr_1 = __C(CHIP,_mem_read_region_1); 291 t->abs_rr_2 = __C(CHIP,_mem_read_region_2); 292 t->abs_rr_4 = __C(CHIP,_mem_read_region_4); 293 t->abs_rr_8 = __C(CHIP,_mem_read_region_8); 294 295 /* write (single) */ 296 t->abs_w_1 = __C(CHIP,_mem_write_1); 297 t->abs_w_2 = __C(CHIP,_mem_write_2); 298 t->abs_w_4 = __C(CHIP,_mem_write_4); 299 t->abs_w_8 = __C(CHIP,_mem_write_8); 300 301 /* write multiple */ 302 t->abs_wm_1 = __C(CHIP,_mem_write_multi_1); 303 t->abs_wm_2 = __C(CHIP,_mem_write_multi_2); 304 t->abs_wm_4 = __C(CHIP,_mem_write_multi_4); 305 t->abs_wm_8 = __C(CHIP,_mem_write_multi_8); 306 307 /* write region */ 308 t->abs_wr_1 = __C(CHIP,_mem_write_region_1); 309 t->abs_wr_2 = __C(CHIP,_mem_write_region_2); 310 t->abs_wr_4 = __C(CHIP,_mem_write_region_4); 311 t->abs_wr_8 = __C(CHIP,_mem_write_region_8); 312 313 /* set multiple */ 314 t->abs_sm_1 = __C(CHIP,_mem_set_multi_1); 315 t->abs_sm_2 = __C(CHIP,_mem_set_multi_2); 316 t->abs_sm_4 = __C(CHIP,_mem_set_multi_4); 317 t->abs_sm_8 = __C(CHIP,_mem_set_multi_8); 318 319 /* set region */ 320 t->abs_sr_1 = __C(CHIP,_mem_set_region_1); 321 t->abs_sr_2 = __C(CHIP,_mem_set_region_2); 322 t->abs_sr_4 = __C(CHIP,_mem_set_region_4); 323 t->abs_sr_8 = __C(CHIP,_mem_set_region_8); 324 325 /* copy */ 326 t->abs_c_1 = __C(CHIP,_mem_copy_region_1); 327 t->abs_c_2 = __C(CHIP,_mem_copy_region_2); 328 t->abs_c_4 = __C(CHIP,_mem_copy_region_4); 329 t->abs_c_8 = __C(CHIP,_mem_copy_region_8); 330 331 #ifdef CHIP_D_MEM_W1_SYS_START 332 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 333 dex = extent_create(__S(__C(CHIP,_bus_dmem)), 0x0UL, 334 0xffffffffffffffffUL, M_DEVBUF, 335 (void *)CHIP_D_MEM_EX_STORE(v), CHIP_D_MEM_EX_STORE_SIZE(v), 336 EX_NOWAIT); 337 extent_alloc_region(dex, 0, 0xffffffffffffffffUL, EX_NOWAIT); 338 339 #ifdef CHIP_D_MEM_W1_BUS_START 340 #ifdef EXTENT_DEBUG 341 printf("dmem: freeing from 0x%lx to 0x%lx\n", 342 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v)); 343 #endif 344 extent_free(dex, CHIP_D_MEM_W1_BUS_START(v), 345 CHIP_D_MEM_W1_BUS_END(v) - CHIP_D_MEM_W1_BUS_START(v) + 1, 346 EX_NOWAIT); 347 #endif 348 349 #ifdef EXTENT_DEBUG 350 extent_print(dex); 351 #endif 352 CHIP_D_MEM_EXTENT(v) = dex; 353 #endif /* CHIP_D_MEM_W1_SYS_START */ 354 355 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 356 sex = extent_create(__S(__C(CHIP,_bus_smem)), 0x0UL, 357 0xffffffffffffffffUL, M_DEVBUF, 358 (void *)CHIP_S_MEM_EX_STORE(v), CHIP_S_MEM_EX_STORE_SIZE(v), 359 EX_NOWAIT); 360 extent_alloc_region(sex, 0, 0xffffffffffffffffUL, EX_NOWAIT); 361 362 #ifdef CHIP_S_MEM_W1_BUS_START 363 #ifdef EXTENT_DEBUG 364 printf("smem: freeing from 0x%lx to 0x%lx\n", 365 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v)); 366 #endif 367 extent_free(sex, CHIP_S_MEM_W1_BUS_START(v), 368 CHIP_S_MEM_W1_BUS_END(v) - CHIP_S_MEM_W1_BUS_START(v) + 1, 369 EX_NOWAIT); 370 #endif 371 #ifdef CHIP_S_MEM_W2_BUS_START 372 if (CHIP_S_MEM_W2_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v)) { 373 #ifdef EXTENT_DEBUG 374 printf("smem: freeing from 0x%lx to 0x%lx\n", 375 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 376 #endif 377 extent_free(sex, CHIP_S_MEM_W2_BUS_START(v), 378 CHIP_S_MEM_W2_BUS_END(v) - CHIP_S_MEM_W2_BUS_START(v) + 1, 379 EX_NOWAIT); 380 } else { 381 #ifdef EXTENT_DEBUG 382 printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n", 383 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 384 #endif 385 } 386 #endif 387 #ifdef CHIP_S_MEM_W3_BUS_START 388 if (CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W1_BUS_START(v) && 389 CHIP_S_MEM_W3_BUS_START(v) != CHIP_S_MEM_W2_BUS_START(v)) { 390 #ifdef EXTENT_DEBUG 391 printf("smem: freeing from 0x%lx to 0x%lx\n", 392 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v)); 393 #endif 394 extent_free(sex, CHIP_S_MEM_W3_BUS_START(v), 395 CHIP_S_MEM_W3_BUS_END(v) - CHIP_S_MEM_W3_BUS_START(v) + 1, 396 EX_NOWAIT); 397 } else { 398 #ifdef EXTENT_DEBUG 399 printf("smem: window 2 (0x%lx to 0x%lx) overlaps window 1\n", 400 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 401 #endif 402 } 403 #endif 404 405 #ifdef EXTENT_DEBUG 406 extent_print(sex); 407 #endif 408 CHIP_S_MEM_EXTENT(v) = sex; 409 } 410 411 #ifdef CHIP_D_MEM_W1_SYS_START 412 static int __C(CHIP,_xlate_addr_to_dense_handle) __P((void *, 413 bus_addr_t, bus_space_handle_t *)); 414 static int __C(CHIP,_xlate_dense_handle_to_addr) __P((void *, 415 bus_space_handle_t, bus_addr_t *)); 416 #endif /* CHIP_D_MEM_W1_SYS_START */ 417 static int __C(CHIP,_xlate_addr_to_sparse_handle) __P((void *, 418 bus_addr_t, bus_space_handle_t *)); 419 static int __C(CHIP,_xlate_sparse_handle_to_addr) __P((void *, 420 bus_space_handle_t, bus_addr_t *)); 421 422 #ifdef CHIP_D_MEM_W1_SYS_START 423 static int 424 __C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, memhp) 425 void *v; 426 bus_addr_t memaddr; 427 bus_space_handle_t *memhp; 428 { 429 #ifdef CHIP_D_MEM_W1_BUS_START 430 if (memaddr >= CHIP_D_MEM_W1_BUS_START(v) && 431 memaddr <= CHIP_D_MEM_W1_BUS_END(v)) { 432 if (memhp != NULL) 433 *memhp = 434 ALPHA_PHYS_TO_K0SEG(CHIP_D_MEM_W1_SYS_START(v)) + 435 (memaddr - CHIP_D_MEM_W1_BUS_START(v)); 436 return (1); 437 } else 438 #endif 439 return (0); 440 } 441 442 static int 443 __C(CHIP,_xlate_dense_handle_to_addr)(v, memh, memaddrp) 444 void *v; 445 bus_space_handle_t memh; 446 bus_addr_t *memaddrp; 447 { 448 449 memh = ALPHA_K0SEG_TO_PHYS(memh); 450 451 #ifdef CHIP_D_MEM_W1_BUS_START 452 if (memh >= CHIP_D_MEM_W1_SYS_START(v) && 453 memh <= CHIP_D_MEM_W1_SYS_END(v)) { 454 *memaddrp = CHIP_D_MEM_W1_BUS_START(v) + 455 (memh - CHIP_D_MEM_W1_SYS_START(v)); 456 return (1); 457 } else 458 #endif 459 return (0); 460 } 461 #endif /* CHIP_D_MEM_W1_SYS_START */ 462 463 static int 464 __C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, memhp) 465 void *v; 466 bus_addr_t memaddr; 467 bus_space_handle_t *memhp; 468 { 469 470 #ifdef CHIP_S_MEM_W1_BUS_START 471 if (memaddr >= CHIP_S_MEM_W1_BUS_START(v) && 472 memaddr <= CHIP_S_MEM_W1_BUS_END(v)) { 473 if (memhp != NULL) 474 *memhp = 475 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W1_SYS_START(v)) >> 476 CHIP_ADDR_SHIFT) + 477 (memaddr - CHIP_S_MEM_W1_BUS_START(v)); 478 return (1); 479 } else 480 #endif 481 #ifdef CHIP_S_MEM_W2_BUS_START 482 if (memaddr >= CHIP_S_MEM_W2_BUS_START(v) && 483 memaddr <= CHIP_S_MEM_W2_BUS_END(v)) { 484 if (memhp != NULL) 485 *memhp = 486 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W2_SYS_START(v)) >> 487 CHIP_ADDR_SHIFT) + 488 (memaddr - CHIP_S_MEM_W2_BUS_START(v)); 489 return (1); 490 } else 491 #endif 492 #ifdef CHIP_S_MEM_W3_BUS_START 493 if (memaddr >= CHIP_S_MEM_W3_BUS_START(v) && 494 memaddr <= CHIP_S_MEM_W3_BUS_END(v)) { 495 if (memhp != NULL) 496 *memhp = 497 (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W3_SYS_START(v)) >> 498 CHIP_ADDR_SHIFT) + 499 (memaddr - CHIP_S_MEM_W3_BUS_START(v)); 500 return (1); 501 } else 502 #endif 503 return (0); 504 } 505 506 static int 507 __C(CHIP,_xlate_sparse_handle_to_addr)(v, memh, memaddrp) 508 void *v; 509 bus_space_handle_t memh; 510 bus_addr_t *memaddrp; 511 { 512 513 memh = ALPHA_K0SEG_TO_PHYS(memh << CHIP_ADDR_SHIFT) >> CHIP_ADDR_SHIFT; 514 515 #ifdef CHIP_S_MEM_W1_BUS_START 516 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W1_SYS_START(v) && 517 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W1_SYS_END(v)) { 518 *memaddrp = CHIP_S_MEM_W1_BUS_START(v) + 519 (memh - (CHIP_S_MEM_W1_SYS_START(v) >> CHIP_ADDR_SHIFT)); 520 return (1); 521 } else 522 #endif 523 #ifdef CHIP_S_MEM_W2_BUS_START 524 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W2_SYS_START(v) && 525 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W2_SYS_END(v)) { 526 *memaddrp = CHIP_S_MEM_W2_BUS_START(v) + 527 (memh - (CHIP_S_MEM_W2_SYS_START(v) >> CHIP_ADDR_SHIFT)); 528 return (1); 529 } else 530 #endif 531 #ifdef CHIP_S_MEM_W3_BUS_START 532 if ((memh << CHIP_ADDR_SHIFT) >= CHIP_S_MEM_W3_SYS_START(v) && 533 (memh << CHIP_ADDR_SHIFT) <= CHIP_S_MEM_W3_SYS_END(v)) { 534 *memaddrp = CHIP_S_MEM_W3_BUS_START(v) + 535 (memh - (CHIP_S_MEM_W3_SYS_START(v) >> CHIP_ADDR_SHIFT)); 536 return (1); 537 } else 538 #endif 539 return (0); 540 } 541 542 int 543 __C(CHIP,_mem_translate)(v, memaddr, memlen, flags, abst) 544 void *v; 545 bus_addr_t memaddr; 546 bus_size_t memlen; 547 int flags; 548 struct alpha_bus_space_translation *abst; 549 { 550 551 /* XXX */ 552 return (EOPNOTSUPP); 553 } 554 555 int 556 __C(CHIP,_mem_get_window)(v, window, abst) 557 void *v; 558 int window; 559 struct alpha_bus_space_translation *abst; 560 { 561 562 #ifdef CHIP_D_MEM_W1_BUS_START 563 #define FIRST_SPARSE 1 564 #else 565 #define FIRST_SPARSE 0 566 #endif 567 568 switch (window) { 569 #ifdef CHIP_D_MEM_W1_BUS_START 570 case 0: 571 abst->abst_bus_start = CHIP_D_MEM_W1_BUS_START(v); 572 abst->abst_bus_end = CHIP_D_MEM_W1_BUS_END(v); 573 abst->abst_sys_start = CHIP_D_MEM_W1_SYS_START(v); 574 abst->abst_sys_end = CHIP_D_MEM_W1_SYS_END(v); 575 abst->abst_addr_shift = 0; 576 abst->abst_size_shift = 0; 577 abst->abst_flags = ABST_DENSE; 578 break; 579 #endif 580 581 #ifdef CHIP_S_MEM_W1_BUS_START 582 case (FIRST_SPARSE): 583 abst->abst_bus_start = CHIP_S_MEM_W1_BUS_START(v); 584 abst->abst_bus_end = CHIP_S_MEM_W1_BUS_END(v); 585 abst->abst_sys_start = CHIP_S_MEM_W1_SYS_START(v); 586 abst->abst_sys_end = CHIP_S_MEM_W1_SYS_END(v); 587 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 588 abst->abst_size_shift = CHIP_SIZE_SHIFT; 589 abst->abst_flags = 0; 590 break; 591 #endif 592 593 #ifdef CHIP_S_MEM_W2_BUS_START 594 case (FIRST_SPARSE + 1): 595 abst->abst_bus_start = CHIP_S_MEM_W2_BUS_START(v); 596 abst->abst_bus_end = CHIP_S_MEM_W2_BUS_END(v); 597 abst->abst_sys_start = CHIP_S_MEM_W2_SYS_START(v); 598 abst->abst_sys_end = CHIP_S_MEM_W2_SYS_END(v); 599 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 600 abst->abst_size_shift = CHIP_SIZE_SHIFT; 601 abst->abst_flags = 0; 602 break; 603 #endif 604 605 #ifdef CHIP_S_MEM_W3_BUS_START 606 case (FIRST_SPARSE + 2): 607 abst->abst_bus_start = CHIP_S_MEM_W3_BUS_START(v); 608 abst->abst_bus_end = CHIP_S_MEM_W3_BUS_END(v); 609 abst->abst_sys_start = CHIP_S_MEM_W3_SYS_START(v); 610 abst->abst_sys_end = CHIP_S_MEM_W3_SYS_END(v); 611 abst->abst_addr_shift = CHIP_ADDR_SHIFT; 612 abst->abst_size_shift = CHIP_SIZE_SHIFT; 613 abst->abst_flags = 0; 614 break; 615 #endif 616 } 617 618 #undef FIRST_SPARSE 619 620 return (0); 621 } 622 623 int 624 __C(CHIP,_mem_map)(v, memaddr, memsize, flags, memhp, acct) 625 void *v; 626 bus_addr_t memaddr; 627 bus_size_t memsize; 628 int flags; 629 bus_space_handle_t *memhp; 630 int acct; 631 { 632 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */ 633 int didd, dids, errord, errors, mustd, musts; 634 int prefectchable = flags & BUS_SPACE_MAP_PREFETCHABLE; 635 int linear = flags & BUS_SPACE_MAP_LINEAR; 636 637 /* 638 * XXX Too hairy to not do accounting in this space. Nothing 639 * XXX much uses this anyhow (only ISA PnP does, and only via 640 * XXX a machine-dependent hook), so we don't have to care. 641 */ 642 if (acct == 0) 643 return (EOPNOTSUPP); 644 645 #ifdef CHIP_D_MEM_W1_SYS_START 646 mustd = 1; 647 if (!__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, NULL)) { 648 /* 649 * This address isn't mapped into dense space; don't 650 * require it. 651 */ 652 mustd = 0; 653 } 654 #else 655 mustd = 0; 656 #endif 657 658 /* No prefectchable space without dense. */ 659 if (mustd == 0) 660 prefectchable = 0; 661 662 /* 663 * We must have dense space to map memory linearly. 664 */ 665 if (linear && !prefectchable) 666 return (EOPNOTSUPP); 667 668 musts = (prefectchable == 0); 669 if (!__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, NULL)) { 670 /* 671 * This address isn't mapped into sparse space; don't 672 * require it. 673 */ 674 musts = 0; 675 } 676 677 /* 678 * If this address isn't mapped into dense or sparse, we lose. 679 */ 680 if (mustd == 0 && musts == 0) { 681 #ifdef EXTENT_DEBUG 682 printf("mem: address 0x%lx not in dense or sparse space\n", 683 memaddr); 684 #endif 685 return (EINVAL); 686 } 687 688 #ifdef EXTENT_DEBUG 689 printf("mem: allocating 0x%lx to 0x%lx\n", memaddr, 690 memaddr + memsize - 1); 691 printf("mem: %s dense, %s sparse\n", mustd ? "need" : "want", 692 musts ? "need" : "want"); 693 #endif 694 #ifdef CHIP_D_MEM_W1_SYS_START 695 errord = extent_alloc_region(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 696 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 697 #else 698 errord = EINVAL; 699 #endif 700 didd = (errord == 0); 701 errors = extent_alloc_region(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 702 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 703 dids = (errors == 0); 704 705 #ifdef EXTENT_DEBUG 706 if (!didd) 707 printf("mem: failed to get dense (%d)\n", errord); 708 if (!dids) 709 printf("mem: failed to get sparse (%d)\n", errors); 710 #endif 711 712 if ((mustd && !didd) || (musts && !dids)) 713 goto bad; 714 715 #ifdef CHIP_D_MEM_W1_SYS_START 716 if (didd && !__C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, &dh)) { 717 printf("\n"); 718 #ifdef CHIP_D_MEM_W1_BUS_START 719 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 720 CHIP_D_MEM_W1_BUS_START(v), CHIP_D_MEM_W1_BUS_END(v)); 721 #endif 722 panic("%s: don't know how to map %lx prefectchable", 723 __S(__C(CHIP,_mem_map)), memaddr); 724 } 725 #endif /* CHIP_D_MEM_W1_SYS_START */ 726 727 if (dids && !__C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, &sh)) { 728 printf("\n"); 729 #ifdef CHIP_S_MEM_W1_BUS_START 730 printf("%s: window[1]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 731 CHIP_S_MEM_W1_BUS_START(v), CHIP_S_MEM_W1_BUS_END(v)); 732 #endif 733 #ifdef CHIP_S_MEM_W2_BUS_START 734 printf("%s: window[2]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 735 CHIP_S_MEM_W2_BUS_START(v), CHIP_S_MEM_W2_BUS_END(v)); 736 #endif 737 #ifdef CHIP_S_MEM_W3_BUS_START 738 printf("%s: window[3]=0x%lx-0x%lx\n", __S(__C(CHIP,_mem_map)), 739 CHIP_S_MEM_W3_BUS_START(v), CHIP_S_MEM_W3_BUS_END(v)); 740 #endif 741 panic("%s: don't know how to map %lx non-prefectchable", 742 __S(__C(CHIP,_mem_map)), memaddr); 743 } 744 745 if (prefectchable) 746 *memhp = dh; 747 else 748 *memhp = sh; 749 return (0); 750 751 bad: 752 #ifdef EXTENT_DEBUG 753 printf("mem: failed\n"); 754 #endif 755 #ifdef CHIP_D_MEM_W1_SYS_START 756 if (didd) { 757 #ifdef EXTENT_DEBUG 758 printf("mem: freeing dense\n"); 759 #endif 760 if (extent_free(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 761 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 762 printf("%s: WARNING: couldn't free dense 0x%lx-0x%lx\n", 763 __S(__C(CHIP,_mem_map)), memaddr, 764 memaddr + memsize - 1); 765 } 766 } 767 #endif /* CHIP_D_MEM_W1_SYS_START */ 768 if (dids) { 769 #ifdef EXTENT_DEBUG 770 printf("mem: freeing sparse\n"); 771 #endif 772 if (extent_free(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 773 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 774 printf("%s: WARNING: couldn't free sparse 0x%lx-0x%lx\n", 775 __S(__C(CHIP,_mem_map)), memaddr, 776 memaddr + memsize - 1); 777 } 778 } 779 780 #ifdef EXTENT_DEBUG 781 #ifdef CHIP_D_MEM_W1_SYS_START 782 extent_print(CHIP_D_MEM_EXTENT(v)); 783 #endif 784 extent_print(CHIP_S_MEM_EXTENT(v)); 785 #endif 786 787 /* 788 * return dense error if we needed it but couldn't get it, else 789 * sparse error. The error _has_ to be one of the two... 790 */ 791 return (mustd && !didd ? errord : (musts && !dids ? errors : EINVAL)); 792 } 793 794 void 795 __C(CHIP,_mem_unmap)(v, memh, memsize, acct) 796 void *v; 797 bus_space_handle_t memh; 798 bus_size_t memsize; 799 int acct; 800 { 801 bus_addr_t memaddr; 802 #ifdef CHIP_D_MEM_W1_SYS_START 803 bus_space_handle_t temph; 804 #endif 805 int sparse, haves, haved; 806 807 if (acct == 0) 808 return; 809 810 #ifdef EXTENT_DEBUG 811 printf("mem: freeing handle 0x%lx for 0x%lx\n", memh, memsize); 812 #endif 813 814 /* 815 * Find out what space we're in. 816 */ 817 sparse = ((memh >> 63) == 0); 818 819 /* 820 * Find out what address we're in in that space. 821 */ 822 haves = haved = 0; 823 if (sparse) 824 haves = __C(CHIP,_xlate_sparse_handle_to_addr)(v, memh, 825 &memaddr); 826 #ifdef CHIP_D_MEM_W1_SYS_START 827 else 828 haved = __C(CHIP,_xlate_dense_handle_to_addr)(v, memh, 829 &memaddr); 830 #endif /* CHIP_D_MEM_W1_SYS_START */ 831 832 if (!haves && !haved) 833 panic("%s: couldn't get addr from %s handle 0x%lx", 834 __S(__C(CHIP,_mem_unmap)), sparse ? "sparse" : "dense", 835 memh); 836 837 #ifdef CHIP_D_MEM_W1_SYS_START 838 /* 839 * Find out were/if that address lives in the other space. 840 */ 841 if (sparse) 842 haved = __C(CHIP,_xlate_addr_to_dense_handle)(v, memaddr, 843 &temph); 844 else 845 haves = __C(CHIP,_xlate_addr_to_sparse_handle)(v, memaddr, 846 &temph); 847 #endif /* CHIP_D_MEM_W1_SYS_START */ 848 849 /* 850 * Free any ranges we have. 851 */ 852 #ifdef EXTENT_DEBUG 853 printf("mem: it's at 0x%lx (%sdense, %ssparse)\n", memaddr, 854 haved ? "" : "not ", haves ? "" : "not "); 855 #endif 856 #ifdef CHIP_D_MEM_W1_SYS_START 857 if (haved && extent_free(CHIP_D_MEM_EXTENT(v), memaddr, memsize, 858 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 859 printf("%s: WARNING: couldn't free dense 0x%lx-0x%lx\n", 860 __S(__C(CHIP,_mem_map)), memaddr, 861 memaddr + memsize - 1); 862 } 863 #endif 864 if (haves && extent_free(CHIP_S_MEM_EXTENT(v), memaddr, memsize, 865 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)) != 0) { 866 printf("%s: WARNING: couldn't free sparse 0x%lx-0x%lx\n", 867 __S(__C(CHIP,_mem_map)), memaddr, 868 memaddr + memsize - 1); 869 } 870 } 871 872 int 873 __C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh) 874 void *v; 875 bus_space_handle_t memh, *nmemh; 876 bus_size_t offset, size; 877 { 878 879 *nmemh = memh + offset; 880 return (0); 881 } 882 883 int 884 __C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, flags, 885 addrp, bshp) 886 void *v; 887 bus_addr_t rstart, rend, *addrp; 888 bus_size_t size, align, boundary; 889 int flags; 890 bus_space_handle_t *bshp; 891 { 892 893 /* XXX XXX XXX XXX XXX XXX */ 894 panic("%s not implemented", __S(__C(CHIP,_mem_alloc))); 895 } 896 897 void 898 __C(CHIP,_mem_free)(v, bsh, size) 899 void *v; 900 bus_space_handle_t bsh; 901 bus_size_t size; 902 { 903 904 /* XXX XXX XXX XXX XXX XXX */ 905 panic("%s not implemented", __S(__C(CHIP,_mem_free))); 906 } 907 908 void * 909 __C(CHIP,_mem_vaddr)(v, bsh) 910 void *v; 911 bus_space_handle_t bsh; 912 { 913 #ifdef CHIP_D_MEM_W1_SYS_START 914 /* 915 * XXX should check that the range was mapped 916 * with BUS_SPACE_MAP_LINEAR for sanity 917 */ 918 if ((bsh >> 63) != 0) 919 return ((void *)bsh); 920 #endif 921 return (0); 922 } 923 924 paddr_t 925 __C(CHIP,_mem_mmap)(v, addr, off, prot, flags) 926 void *v; 927 bus_addr_t addr; 928 off_t off; 929 int prot; 930 int flags; 931 { 932 bus_space_handle_t dh = 0, sh = 0; /* XXX -Wuninitialized */ 933 int linear = flags & BUS_SPACE_MAP_LINEAR; 934 int haved = 0, haves = 0; 935 936 #ifdef CHIP_D_MEM_W1_SYS_START 937 if (__C(CHIP,_xlate_addr_to_dense_handle)(v, addr + off, &dh)) { 938 haved = 1; 939 dh = ALPHA_K0SEG_TO_PHYS(dh); 940 } 941 #endif 942 if (__C(CHIP,_xlate_addr_to_sparse_handle)(v, addr + off, &sh)) { 943 haves = 1; 944 sh = ALPHA_K0SEG_TO_PHYS(sh); 945 } 946 947 if (linear) { 948 if (haved == 0) 949 return (-1); 950 return (alpha_btop(dh)); 951 } 952 953 if (haves == 0) 954 return (-1); 955 return (alpha_btop(sh)); 956 } 957 958 inline void 959 __C(CHIP,_mem_barrier)(v, h, o, l, f) 960 void *v; 961 bus_space_handle_t h; 962 bus_size_t o, l; 963 int f; 964 { 965 966 if ((f & BUS_SPACE_BARRIER_READ) != 0) 967 alpha_mb(); 968 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 969 alpha_wmb(); 970 } 971 972 inline u_int8_t 973 __C(CHIP,_mem_read_1)(v, memh, off) 974 void *v; 975 bus_space_handle_t memh; 976 bus_size_t off; 977 { 978 register bus_space_handle_t tmpmemh; 979 register u_int32_t *port, val; 980 register u_int8_t rval; 981 register int offset; 982 983 alpha_mb(); 984 985 #ifdef CHIP_D_MEM_W1_SYS_START 986 if ((memh >> 63) != 0) 987 return (*(u_int8_t *)(memh + off)); 988 #endif 989 990 tmpmemh = memh + off; 991 offset = tmpmemh & 3; 992 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 993 (0 << CHIP_SIZE_SHIFT)); 994 val = *port; 995 rval = ((val) >> (8 * offset)) & 0xff; 996 997 return rval; 998 } 999 1000 inline u_int16_t 1001 __C(CHIP,_mem_read_2)(v, memh, off) 1002 void *v; 1003 bus_space_handle_t memh; 1004 bus_size_t off; 1005 { 1006 register bus_space_handle_t tmpmemh; 1007 register u_int32_t *port, val; 1008 register u_int16_t rval; 1009 register int offset; 1010 1011 alpha_mb(); 1012 1013 #ifdef CHIP_D_MEM_W1_SYS_START 1014 if ((memh >> 63) != 0) 1015 return (*(u_int16_t *)(memh + off)); 1016 #endif 1017 1018 tmpmemh = memh + off; 1019 offset = tmpmemh & 3; 1020 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1021 (1 << CHIP_SIZE_SHIFT)); 1022 val = *port; 1023 rval = ((val) >> (8 * offset)) & 0xffff; 1024 1025 return rval; 1026 } 1027 1028 inline u_int32_t 1029 __C(CHIP,_mem_read_4)(v, memh, off) 1030 void *v; 1031 bus_space_handle_t memh; 1032 bus_size_t off; 1033 { 1034 register bus_space_handle_t tmpmemh; 1035 register u_int32_t *port, val; 1036 register u_int32_t rval; 1037 register int offset; 1038 1039 alpha_mb(); 1040 1041 #ifdef CHIP_D_MEM_W1_SYS_START 1042 if ((memh >> 63) != 0) 1043 return (*(u_int32_t *)(memh + off)); 1044 #endif 1045 1046 tmpmemh = memh + off; 1047 offset = tmpmemh & 3; 1048 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1049 (3 << CHIP_SIZE_SHIFT)); 1050 val = *port; 1051 #if 0 1052 rval = ((val) >> (8 * offset)) & 0xffffffff; 1053 #else 1054 rval = val; 1055 #endif 1056 1057 return rval; 1058 } 1059 1060 inline u_int64_t 1061 __C(CHIP,_mem_read_8)(v, memh, off) 1062 void *v; 1063 bus_space_handle_t memh; 1064 bus_size_t off; 1065 { 1066 1067 alpha_mb(); 1068 1069 #ifdef CHIP_D_MEM_W1_SYS_START 1070 if ((memh >> 63) != 0) 1071 return (*(u_int64_t *)(memh + off)); 1072 #endif 1073 1074 /* XXX XXX XXX */ 1075 panic("%s not implemented", __S(__C(CHIP,_mem_read_8))); 1076 } 1077 1078 #define CHIP_mem_read_multi_N(BYTES,TYPE) \ 1079 void \ 1080 __C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \ 1081 void *v; \ 1082 bus_space_handle_t h; \ 1083 bus_size_t o, c; \ 1084 TYPE *a; \ 1085 { \ 1086 \ 1087 while (c-- > 0) { \ 1088 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 1089 BUS_SPACE_BARRIER_READ); \ 1090 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 1091 } \ 1092 } 1093 CHIP_mem_read_multi_N(1,u_int8_t) 1094 CHIP_mem_read_multi_N(2,u_int16_t) 1095 CHIP_mem_read_multi_N(4,u_int32_t) 1096 CHIP_mem_read_multi_N(8,u_int64_t) 1097 1098 #define CHIP_mem_read_region_N(BYTES,TYPE) \ 1099 void \ 1100 __C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \ 1101 void *v; \ 1102 bus_space_handle_t h; \ 1103 bus_size_t o, c; \ 1104 TYPE *a; \ 1105 { \ 1106 \ 1107 while (c-- > 0) { \ 1108 *a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \ 1109 o += sizeof *a; \ 1110 } \ 1111 } 1112 CHIP_mem_read_region_N(1,u_int8_t) 1113 CHIP_mem_read_region_N(2,u_int16_t) 1114 CHIP_mem_read_region_N(4,u_int32_t) 1115 CHIP_mem_read_region_N(8,u_int64_t) 1116 1117 inline void 1118 __C(CHIP,_mem_write_1)(v, memh, off, val) 1119 void *v; 1120 bus_space_handle_t memh; 1121 bus_size_t off; 1122 u_int8_t val; 1123 { 1124 register bus_space_handle_t tmpmemh; 1125 register u_int32_t *port, nval; 1126 register int offset; 1127 1128 #ifdef CHIP_D_MEM_W1_SYS_START 1129 if ((memh >> 63) != 0) 1130 (*(u_int8_t *)(memh + off)) = val; 1131 else 1132 #endif 1133 { 1134 tmpmemh = memh + off; 1135 offset = tmpmemh & 3; 1136 nval = val << (8 * offset); 1137 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1138 (0 << CHIP_SIZE_SHIFT)); 1139 *port = nval; 1140 } 1141 alpha_mb(); 1142 } 1143 1144 inline void 1145 __C(CHIP,_mem_write_2)(v, memh, off, val) 1146 void *v; 1147 bus_space_handle_t memh; 1148 bus_size_t off; 1149 u_int16_t val; 1150 { 1151 register bus_space_handle_t tmpmemh; 1152 register u_int32_t *port, nval; 1153 register int offset; 1154 1155 #ifdef CHIP_D_MEM_W1_SYS_START 1156 if ((memh >> 63) != 0) 1157 (*(u_int16_t *)(memh + off)) = val; 1158 else 1159 #endif 1160 { 1161 tmpmemh = memh + off; 1162 offset = tmpmemh & 3; 1163 nval = val << (8 * offset); 1164 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1165 (1 << CHIP_SIZE_SHIFT)); 1166 *port = nval; 1167 } 1168 alpha_mb(); 1169 } 1170 1171 inline void 1172 __C(CHIP,_mem_write_4)(v, memh, off, val) 1173 void *v; 1174 bus_space_handle_t memh; 1175 bus_size_t off; 1176 u_int32_t val; 1177 { 1178 register bus_space_handle_t tmpmemh; 1179 register u_int32_t *port, nval; 1180 register int offset; 1181 1182 #ifdef CHIP_D_MEM_W1_SYS_START 1183 if ((memh >> 63) != 0) 1184 (*(u_int32_t *)(memh + off)) = val; 1185 else 1186 #endif 1187 { 1188 tmpmemh = memh + off; 1189 offset = tmpmemh & 3; 1190 nval = val /*<< (8 * offset)*/; 1191 port = (u_int32_t *)((tmpmemh << CHIP_ADDR_SHIFT) | 1192 (3 << CHIP_SIZE_SHIFT)); 1193 *port = nval; 1194 } 1195 alpha_mb(); 1196 } 1197 1198 inline void 1199 __C(CHIP,_mem_write_8)(v, memh, off, val) 1200 void *v; 1201 bus_space_handle_t memh; 1202 bus_size_t off; 1203 u_int64_t val; 1204 { 1205 1206 #ifdef CHIP_D_MEM_W1_SYS_START 1207 if ((memh >> 63) != 0) 1208 (*(u_int64_t *)(memh + off)) = val; 1209 else 1210 #endif 1211 { 1212 /* XXX XXX XXX */ 1213 panic("%s not implemented", 1214 __S(__C(CHIP,_mem_write_8))); 1215 } 1216 alpha_mb(); 1217 } 1218 1219 #define CHIP_mem_write_multi_N(BYTES,TYPE) \ 1220 void \ 1221 __C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \ 1222 void *v; \ 1223 bus_space_handle_t h; \ 1224 bus_size_t o, c; \ 1225 const TYPE *a; \ 1226 { \ 1227 \ 1228 while (c-- > 0) { \ 1229 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 1230 __C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \ 1231 BUS_SPACE_BARRIER_WRITE); \ 1232 } \ 1233 } 1234 CHIP_mem_write_multi_N(1,u_int8_t) 1235 CHIP_mem_write_multi_N(2,u_int16_t) 1236 CHIP_mem_write_multi_N(4,u_int32_t) 1237 CHIP_mem_write_multi_N(8,u_int64_t) 1238 1239 #define CHIP_mem_write_region_N(BYTES,TYPE) \ 1240 void \ 1241 __C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \ 1242 void *v; \ 1243 bus_space_handle_t h; \ 1244 bus_size_t o, c; \ 1245 const TYPE *a; \ 1246 { \ 1247 \ 1248 while (c-- > 0) { \ 1249 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \ 1250 o += sizeof *a; \ 1251 } \ 1252 } 1253 CHIP_mem_write_region_N(1,u_int8_t) 1254 CHIP_mem_write_region_N(2,u_int16_t) 1255 CHIP_mem_write_region_N(4,u_int32_t) 1256 CHIP_mem_write_region_N(8,u_int64_t) 1257 1258 #define CHIP_mem_set_multi_N(BYTES,TYPE) \ 1259 void \ 1260 __C(__C(CHIP,_mem_set_multi_),BYTES)(v, h, o, val, c) \ 1261 void *v; \ 1262 bus_space_handle_t h; \ 1263 bus_size_t o, c; \ 1264 TYPE val; \ 1265 { \ 1266 \ 1267 while (c-- > 0) { \ 1268 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 1269 __C(CHIP,_mem_barrier)(v, h, o, sizeof val, \ 1270 BUS_SPACE_BARRIER_WRITE); \ 1271 } \ 1272 } 1273 CHIP_mem_set_multi_N(1,u_int8_t) 1274 CHIP_mem_set_multi_N(2,u_int16_t) 1275 CHIP_mem_set_multi_N(4,u_int32_t) 1276 CHIP_mem_set_multi_N(8,u_int64_t) 1277 1278 #define CHIP_mem_set_region_N(BYTES,TYPE) \ 1279 void \ 1280 __C(__C(CHIP,_mem_set_region_),BYTES)(v, h, o, val, c) \ 1281 void *v; \ 1282 bus_space_handle_t h; \ 1283 bus_size_t o, c; \ 1284 TYPE val; \ 1285 { \ 1286 \ 1287 while (c-- > 0) { \ 1288 __C(__C(CHIP,_mem_write_),BYTES)(v, h, o, val); \ 1289 o += sizeof val; \ 1290 } \ 1291 } 1292 CHIP_mem_set_region_N(1,u_int8_t) 1293 CHIP_mem_set_region_N(2,u_int16_t) 1294 CHIP_mem_set_region_N(4,u_int32_t) 1295 CHIP_mem_set_region_N(8,u_int64_t) 1296 1297 #define CHIP_mem_copy_region_N(BYTES) \ 1298 void \ 1299 __C(__C(CHIP,_mem_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 1300 void *v; \ 1301 bus_space_handle_t h1, h2; \ 1302 bus_size_t o1, o2, c; \ 1303 { \ 1304 bus_size_t o; \ 1305 \ 1306 if ((h1 >> 63) != 0 && (h2 >> 63) != 0) { \ 1307 memmove((void *)(h2 + o2), (void *)(h1 + o1), c * BYTES); \ 1308 return; \ 1309 } \ 1310 \ 1311 if ((h1 + o1) >= (h2 + o2)) { \ 1312 /* src after dest: copy forward */ \ 1313 for (o = 0; c != 0; c--, o += BYTES) \ 1314 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 1315 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 1316 } else { \ 1317 /* dest after src: copy backwards */ \ 1318 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) \ 1319 __C(__C(CHIP,_mem_write_),BYTES)(v, h2, o2 + o, \ 1320 __C(__C(CHIP,_mem_read_),BYTES)(v, h1, o1 + o)); \ 1321 } \ 1322 } 1323 CHIP_mem_copy_region_N(1) 1324 CHIP_mem_copy_region_N(2) 1325 CHIP_mem_copy_region_N(4) 1326 CHIP_mem_copy_region_N(8) 1327