1 /* $NetBSD: pci_bwx_bus_io_chipdep.c,v 1.11 2000/06/26 18:19:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 /* 68 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 69 * deal with only a single PCI interface chip in a machine. 70 * 71 * uses: 72 * CHIP name of the 'chip' it's being compiled for. 73 * CHIP_IO_BASE I/O space base to use. 74 * CHIP_IO_EX_STORE 75 * If defined, device-provided static storage area 76 * for the I/O space extent. If this is defined, 77 * CHIP_IO_EX_STORE_SIZE must also be defined. If 78 * this is not defined, a static area will be 79 * declared. 80 * CHIP_IO_EX_STORE_SIZE 81 * Size of the device-provided static storage area 82 * for the I/O memory space extent. 83 */ 84 85 #include <sys/extent.h> 86 87 #include <machine/bwx.h> 88 89 #define __C(A,B) __CONCAT(A,B) 90 #define __S(S) __STRING(S) 91 92 /* mapping/unmapping */ 93 int __C(CHIP,_io_map) __P((void *, bus_addr_t, bus_size_t, int, 94 bus_space_handle_t *, int)); 95 void __C(CHIP,_io_unmap) __P((void *, bus_space_handle_t, 96 bus_size_t, int)); 97 int __C(CHIP,_io_subregion) __P((void *, bus_space_handle_t, 98 bus_size_t, bus_size_t, bus_space_handle_t *)); 99 100 int __C(CHIP,_io_translate) __P((void *, bus_addr_t, bus_size_t, 101 int, struct alpha_bus_space_translation *)); 102 int __C(CHIP,_io_get_window) __P((void *, int, 103 struct alpha_bus_space_translation *)); 104 105 /* allocation/deallocation */ 106 int __C(CHIP,_io_alloc) __P((void *, bus_addr_t, bus_addr_t, 107 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 108 bus_space_handle_t *)); 109 void __C(CHIP,_io_free) __P((void *, bus_space_handle_t, 110 bus_size_t)); 111 112 /* get kernel virtual address */ 113 void * __C(CHIP,_io_vaddr) __P((void *, bus_space_handle_t)); 114 115 /* barrier */ 116 inline void __C(CHIP,_io_barrier) __P((void *, bus_space_handle_t, 117 bus_size_t, bus_size_t, int)); 118 119 /* read (single) */ 120 inline u_int8_t __C(CHIP,_io_read_1) __P((void *, bus_space_handle_t, 121 bus_size_t)); 122 inline u_int16_t __C(CHIP,_io_read_2) __P((void *, bus_space_handle_t, 123 bus_size_t)); 124 inline u_int32_t __C(CHIP,_io_read_4) __P((void *, bus_space_handle_t, 125 bus_size_t)); 126 inline u_int64_t __C(CHIP,_io_read_8) __P((void *, bus_space_handle_t, 127 bus_size_t)); 128 129 /* read multiple */ 130 void __C(CHIP,_io_read_multi_1) __P((void *, bus_space_handle_t, 131 bus_size_t, u_int8_t *, bus_size_t)); 132 void __C(CHIP,_io_read_multi_2) __P((void *, bus_space_handle_t, 133 bus_size_t, u_int16_t *, bus_size_t)); 134 void __C(CHIP,_io_read_multi_4) __P((void *, bus_space_handle_t, 135 bus_size_t, u_int32_t *, bus_size_t)); 136 void __C(CHIP,_io_read_multi_8) __P((void *, bus_space_handle_t, 137 bus_size_t, u_int64_t *, bus_size_t)); 138 139 /* read region */ 140 void __C(CHIP,_io_read_region_1) __P((void *, bus_space_handle_t, 141 bus_size_t, u_int8_t *, bus_size_t)); 142 void __C(CHIP,_io_read_region_2) __P((void *, bus_space_handle_t, 143 bus_size_t, u_int16_t *, bus_size_t)); 144 void __C(CHIP,_io_read_region_4) __P((void *, bus_space_handle_t, 145 bus_size_t, u_int32_t *, bus_size_t)); 146 void __C(CHIP,_io_read_region_8) __P((void *, bus_space_handle_t, 147 bus_size_t, u_int64_t *, bus_size_t)); 148 149 /* write (single) */ 150 inline void __C(CHIP,_io_write_1) __P((void *, bus_space_handle_t, 151 bus_size_t, u_int8_t)); 152 inline void __C(CHIP,_io_write_2) __P((void *, bus_space_handle_t, 153 bus_size_t, u_int16_t)); 154 inline void __C(CHIP,_io_write_4) __P((void *, bus_space_handle_t, 155 bus_size_t, u_int32_t)); 156 inline void __C(CHIP,_io_write_8) __P((void *, bus_space_handle_t, 157 bus_size_t, u_int64_t)); 158 159 /* write multiple */ 160 void __C(CHIP,_io_write_multi_1) __P((void *, bus_space_handle_t, 161 bus_size_t, const u_int8_t *, bus_size_t)); 162 void __C(CHIP,_io_write_multi_2) __P((void *, bus_space_handle_t, 163 bus_size_t, const u_int16_t *, bus_size_t)); 164 void __C(CHIP,_io_write_multi_4) __P((void *, bus_space_handle_t, 165 bus_size_t, const u_int32_t *, bus_size_t)); 166 void __C(CHIP,_io_write_multi_8) __P((void *, bus_space_handle_t, 167 bus_size_t, const u_int64_t *, bus_size_t)); 168 169 /* write region */ 170 void __C(CHIP,_io_write_region_1) __P((void *, bus_space_handle_t, 171 bus_size_t, const u_int8_t *, bus_size_t)); 172 void __C(CHIP,_io_write_region_2) __P((void *, bus_space_handle_t, 173 bus_size_t, const u_int16_t *, bus_size_t)); 174 void __C(CHIP,_io_write_region_4) __P((void *, bus_space_handle_t, 175 bus_size_t, const u_int32_t *, bus_size_t)); 176 void __C(CHIP,_io_write_region_8) __P((void *, bus_space_handle_t, 177 bus_size_t, const u_int64_t *, bus_size_t)); 178 179 /* set multiple */ 180 void __C(CHIP,_io_set_multi_1) __P((void *, bus_space_handle_t, 181 bus_size_t, u_int8_t, bus_size_t)); 182 void __C(CHIP,_io_set_multi_2) __P((void *, bus_space_handle_t, 183 bus_size_t, u_int16_t, bus_size_t)); 184 void __C(CHIP,_io_set_multi_4) __P((void *, bus_space_handle_t, 185 bus_size_t, u_int32_t, bus_size_t)); 186 void __C(CHIP,_io_set_multi_8) __P((void *, bus_space_handle_t, 187 bus_size_t, u_int64_t, bus_size_t)); 188 189 /* set region */ 190 void __C(CHIP,_io_set_region_1) __P((void *, bus_space_handle_t, 191 bus_size_t, u_int8_t, bus_size_t)); 192 void __C(CHIP,_io_set_region_2) __P((void *, bus_space_handle_t, 193 bus_size_t, u_int16_t, bus_size_t)); 194 void __C(CHIP,_io_set_region_4) __P((void *, bus_space_handle_t, 195 bus_size_t, u_int32_t, bus_size_t)); 196 void __C(CHIP,_io_set_region_8) __P((void *, bus_space_handle_t, 197 bus_size_t, u_int64_t, bus_size_t)); 198 199 /* copy */ 200 void __C(CHIP,_io_copy_region_1) __P((void *, bus_space_handle_t, 201 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 202 void __C(CHIP,_io_copy_region_2) __P((void *, bus_space_handle_t, 203 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 204 void __C(CHIP,_io_copy_region_4) __P((void *, bus_space_handle_t, 205 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 206 void __C(CHIP,_io_copy_region_8) __P((void *, bus_space_handle_t, 207 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t)); 208 209 #ifndef CHIP_IO_EX_STORE 210 static long 211 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 212 #define CHIP_IO_EX_STORE(v) (__C(CHIP, _io_ex_storage)) 213 #define CHIP_IO_EX_STORE_SIZE(v) (sizeof __C(CHIP, _io_ex_storage)) 214 #endif 215 216 void 217 __C(CHIP,_bus_io_init)(t, v) 218 bus_space_tag_t t; 219 void *v; 220 { 221 struct extent *ex; 222 223 /* 224 * Initialize the bus space tag. 225 */ 226 227 /* cookie */ 228 t->abs_cookie = v; 229 230 /* mapping/unmapping */ 231 t->abs_map = __C(CHIP,_io_map); 232 t->abs_unmap = __C(CHIP,_io_unmap); 233 t->abs_subregion = __C(CHIP,_io_subregion); 234 235 t->abs_translate = __C(CHIP,_io_translate); 236 t->abs_get_window = __C(CHIP,_io_get_window); 237 238 /* allocation/deallocation */ 239 t->abs_alloc = __C(CHIP,_io_alloc); 240 t->abs_free = __C(CHIP,_io_free); 241 242 /* get kernel virtual address */ 243 t->abs_vaddr = __C(CHIP,_io_vaddr); 244 245 /* barrier */ 246 t->abs_barrier = __C(CHIP,_io_barrier); 247 248 /* read (single) */ 249 t->abs_r_1 = __C(CHIP,_io_read_1); 250 t->abs_r_2 = __C(CHIP,_io_read_2); 251 t->abs_r_4 = __C(CHIP,_io_read_4); 252 t->abs_r_8 = __C(CHIP,_io_read_8); 253 254 /* read multiple */ 255 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 256 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 257 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 258 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 259 260 /* read region */ 261 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 262 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 263 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 264 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 265 266 /* write (single) */ 267 t->abs_w_1 = __C(CHIP,_io_write_1); 268 t->abs_w_2 = __C(CHIP,_io_write_2); 269 t->abs_w_4 = __C(CHIP,_io_write_4); 270 t->abs_w_8 = __C(CHIP,_io_write_8); 271 272 /* write multiple */ 273 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 274 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 275 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 276 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 277 278 /* write region */ 279 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 280 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 281 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 282 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 283 284 /* set multiple */ 285 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 286 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 287 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 288 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 289 290 /* set region */ 291 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 292 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 293 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 294 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 295 296 /* copy */ 297 t->abs_c_1 = __C(CHIP,_io_copy_region_1); 298 t->abs_c_2 = __C(CHIP,_io_copy_region_2); 299 t->abs_c_4 = __C(CHIP,_io_copy_region_4); 300 t->abs_c_8 = __C(CHIP,_io_copy_region_8); 301 302 ex = extent_create(__S(__C(CHIP,_bus_io)), 0x0UL, 0xffffffffUL, 303 M_DEVBUF, (caddr_t)CHIP_IO_EX_STORE(v), CHIP_IO_EX_STORE_SIZE(v), 304 EX_NOWAIT|EX_NOCOALESCE); 305 306 CHIP_IO_EXTENT(v) = ex; 307 } 308 309 int 310 __C(CHIP,_io_translate)(v, ioaddr, iolen, flags, abst) 311 void *v; 312 bus_addr_t ioaddr; 313 bus_size_t iolen; 314 int flags; 315 struct alpha_bus_space_translation *abst; 316 { 317 int linear = flags & BUS_SPACE_MAP_LINEAR; 318 319 /* 320 * Can't map i/o space linearly. 321 */ 322 if (linear) 323 return (EOPNOTSUPP); 324 325 return (__C(CHIP,_io_get_window)(v, 0, abst)); 326 } 327 328 int 329 __C(CHIP,_io_get_window)(v, window, abst) 330 void *v; 331 int window; 332 struct alpha_bus_space_translation *abst; 333 { 334 335 switch (window) { 336 case 0: 337 abst->abst_bus_start = 0; 338 abst->abst_bus_end = 0xffffffffUL; 339 abst->abst_sys_start = CHIP_IO_SYS_START(v); 340 abst->abst_sys_end = CHIP_IO_SYS_START(v) + abst->abst_bus_end; 341 abst->abst_addr_shift = 0; 342 abst->abst_size_shift = 0; 343 abst->abst_flags = ABST_DENSE|ABST_BWX; 344 break; 345 346 default: 347 panic(__S(__C(CHIP,_io_get_window)) ": invalid window %d", 348 window); 349 } 350 351 return (0); 352 } 353 354 int 355 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp, acct) 356 void *v; 357 bus_addr_t ioaddr; 358 bus_size_t iosize; 359 int flags; 360 bus_space_handle_t *iohp; 361 int acct; 362 { 363 struct alpha_bus_space_translation abst; 364 int error; 365 366 /* 367 * Get the translation for this address. 368 */ 369 error = __C(CHIP,_io_translate)(v, ioaddr, iosize, flags, &abst); 370 if (error) 371 return (error); 372 373 if (acct == 0) 374 goto mapit; 375 376 #ifdef EXTENT_DEBUG 377 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 378 #endif 379 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 380 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 381 if (error) { 382 #ifdef EXTENT_DEBUG 383 printf("io: allocation failed (%d)\n", error); 384 extent_print(CHIP_IO_EXTENT(v)); 385 #endif 386 return (error); 387 } 388 389 mapit: 390 *iohp = ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start + ioaddr); 391 392 return (0); 393 } 394 395 void 396 __C(CHIP,_io_unmap)(v, ioh, iosize, acct) 397 void *v; 398 bus_space_handle_t ioh; 399 bus_size_t iosize; 400 int acct; 401 { 402 bus_addr_t ioaddr; 403 int error; 404 405 if (acct == 0) 406 return; 407 408 #ifdef EXTENT_DEBUG 409 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 410 #endif 411 412 ioaddr = ioh - ALPHA_PHYS_TO_K0SEG(CHIP_IO_SYS_START(v)); 413 414 #ifdef EXTENT_DEBUG 415 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 416 #endif 417 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 418 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 419 if (error) { 420 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 421 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 422 error); 423 #ifdef EXTENT_DEBUG 424 extent_print(CHIP_IO_EXTENT(v)); 425 #endif 426 } 427 } 428 429 int 430 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 431 void *v; 432 bus_space_handle_t ioh, *nioh; 433 bus_size_t offset, size; 434 { 435 436 *nioh = ioh + offset; 437 return (0); 438 } 439 440 int 441 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 442 addrp, bshp) 443 void *v; 444 bus_addr_t rstart, rend, *addrp; 445 bus_size_t size, align, boundary; 446 int flags; 447 bus_space_handle_t *bshp; 448 { 449 struct alpha_bus_space_translation abst; 450 int linear = flags & BUS_SPACE_MAP_LINEAR; 451 bus_addr_t ioaddr; 452 int error; 453 454 /* 455 * Can't map i/o space linearly. 456 */ 457 if (linear) 458 return (EOPNOTSUPP); 459 460 /* 461 * Do the requested allocation. 462 */ 463 #ifdef EXTENT_DEBUG 464 printf("io: allocating from 0x%lx to 0x%lx\n", rstart, rend); 465 #endif 466 error = extent_alloc_subregion(CHIP_IO_EXTENT(v), rstart, rend, 467 size, align, boundary, 468 EX_FAST | EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0), 469 &ioaddr); 470 if (error) { 471 #ifdef EXTENT_DEBUG 472 printf("io: allocation failed (%d)\n", error); 473 extent_print(CHIP_IO_EXTENT(v)); 474 #endif 475 return (error); 476 } 477 478 #ifdef EXTENT_DEBUG 479 printf("io: allocated 0x%lx to 0x%lx\n", ioaddr, ioaddr + size - 1); 480 #endif 481 482 error = __C(CHIP,_io_translate)(v, ioaddr, size, flags, &abst); 483 if (error) { 484 (void) extent_free(CHIP_IO_EXTENT(v), ioaddr, size, 485 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 486 return (error); 487 } 488 489 *addrp = ioaddr; 490 *bshp = ALPHA_PHYS_TO_K0SEG(abst.abst_sys_start + ioaddr); 491 492 return (0); 493 } 494 495 void 496 __C(CHIP,_io_free)(v, bsh, size) 497 void *v; 498 bus_space_handle_t bsh; 499 bus_size_t size; 500 { 501 502 /* Unmap does all we need to do. */ 503 __C(CHIP,_io_unmap)(v, bsh, size, 1); 504 } 505 506 void * 507 __C(CHIP,_io_vaddr)(v, bsh) 508 void *v; 509 bus_space_handle_t bsh; 510 { 511 /* 512 * _io_translate() catches BUS_SPACE_MAP_LINEAR, 513 * so we shouldn't get here 514 */ 515 panic("_io_vaddr"); 516 } 517 518 inline void 519 __C(CHIP,_io_barrier)(v, h, o, l, f) 520 void *v; 521 bus_space_handle_t h; 522 bus_size_t o, l; 523 int f; 524 { 525 526 if ((f & BUS_SPACE_BARRIER_READ) != 0) 527 alpha_mb(); 528 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 529 alpha_wmb(); 530 } 531 532 inline u_int8_t 533 __C(CHIP,_io_read_1)(v, ioh, off) 534 void *v; 535 bus_space_handle_t ioh; 536 bus_size_t off; 537 { 538 bus_addr_t addr; 539 540 addr = ioh + off; 541 alpha_mb(); 542 return (alpha_ldbu((u_int8_t *)addr)); 543 } 544 545 inline u_int16_t 546 __C(CHIP,_io_read_2)(v, ioh, off) 547 void *v; 548 bus_space_handle_t ioh; 549 bus_size_t off; 550 { 551 bus_addr_t addr; 552 553 addr = ioh + off; 554 #ifdef DIAGNOSTIC 555 if (addr & 1) 556 panic(__S(__C(CHIP,_io_read_2)) ": addr 0x%lx not aligned", 557 addr); 558 #endif 559 alpha_mb(); 560 return (alpha_ldwu((u_int16_t *)addr)); 561 } 562 563 inline u_int32_t 564 __C(CHIP,_io_read_4)(v, ioh, off) 565 void *v; 566 bus_space_handle_t ioh; 567 bus_size_t off; 568 { 569 bus_addr_t addr; 570 571 addr = ioh + off; 572 #ifdef DIAGNOSTIC 573 if (addr & 3) 574 panic(__S(__C(CHIP,_io_read_4)) ": addr 0x%lx not aligned", 575 addr); 576 #endif 577 alpha_mb(); 578 return (*(u_int32_t *)addr); 579 } 580 581 inline u_int64_t 582 __C(CHIP,_io_read_8)(v, ioh, off) 583 void *v; 584 bus_space_handle_t ioh; 585 bus_size_t off; 586 { 587 588 /* XXX XXX XXX */ 589 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 590 } 591 592 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 593 void \ 594 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 595 void *v; \ 596 bus_space_handle_t h; \ 597 bus_size_t o, c; \ 598 TYPE *a; \ 599 { \ 600 \ 601 while (c-- > 0) { \ 602 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 603 BUS_SPACE_BARRIER_READ); \ 604 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 605 } \ 606 } 607 CHIP_io_read_multi_N(1,u_int8_t) 608 CHIP_io_read_multi_N(2,u_int16_t) 609 CHIP_io_read_multi_N(4,u_int32_t) 610 CHIP_io_read_multi_N(8,u_int64_t) 611 612 #define CHIP_io_read_region_N(BYTES,TYPE) \ 613 void \ 614 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 615 void *v; \ 616 bus_space_handle_t h; \ 617 bus_size_t o, c; \ 618 TYPE *a; \ 619 { \ 620 \ 621 while (c-- > 0) { \ 622 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 623 o += sizeof *a; \ 624 } \ 625 } 626 CHIP_io_read_region_N(1,u_int8_t) 627 CHIP_io_read_region_N(2,u_int16_t) 628 CHIP_io_read_region_N(4,u_int32_t) 629 CHIP_io_read_region_N(8,u_int64_t) 630 631 inline void 632 __C(CHIP,_io_write_1)(v, ioh, off, val) 633 void *v; 634 bus_space_handle_t ioh; 635 bus_size_t off; 636 u_int8_t val; 637 { 638 bus_addr_t addr; 639 640 addr = ioh + off; 641 alpha_stb((u_int8_t *)addr, val); 642 alpha_mb(); 643 } 644 645 inline void 646 __C(CHIP,_io_write_2)(v, ioh, off, val) 647 void *v; 648 bus_space_handle_t ioh; 649 bus_size_t off; 650 u_int16_t val; 651 { 652 bus_addr_t addr; 653 654 addr = ioh + off; 655 #ifdef DIAGNOSTIC 656 if (addr & 1) 657 panic(__S(__C(CHIP,_io_write_2)) ": addr 0x%lx not aligned", 658 addr); 659 #endif 660 alpha_stw((u_int16_t *)addr, val); 661 alpha_mb(); 662 } 663 664 inline void 665 __C(CHIP,_io_write_4)(v, ioh, off, val) 666 void *v; 667 bus_space_handle_t ioh; 668 bus_size_t off; 669 u_int32_t val; 670 { 671 bus_addr_t addr; 672 673 addr = ioh + off; 674 #ifdef DIAGNOSTIC 675 if (addr & 3) 676 panic(__S(__C(CHIP,_io_write_4)) ": addr 0x%lx not aligned", 677 addr); 678 #endif 679 *(u_int32_t *)addr = val; 680 alpha_mb(); 681 } 682 683 inline void 684 __C(CHIP,_io_write_8)(v, ioh, off, val) 685 void *v; 686 bus_space_handle_t ioh; 687 bus_size_t off; 688 u_int64_t val; 689 { 690 691 /* XXX XXX XXX */ 692 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 693 alpha_mb(); 694 } 695 696 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 697 void \ 698 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 699 void *v; \ 700 bus_space_handle_t h; \ 701 bus_size_t o, c; \ 702 const TYPE *a; \ 703 { \ 704 \ 705 while (c-- > 0) { \ 706 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 707 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 708 BUS_SPACE_BARRIER_WRITE); \ 709 } \ 710 } 711 CHIP_io_write_multi_N(1,u_int8_t) 712 CHIP_io_write_multi_N(2,u_int16_t) 713 CHIP_io_write_multi_N(4,u_int32_t) 714 CHIP_io_write_multi_N(8,u_int64_t) 715 716 #define CHIP_io_write_region_N(BYTES,TYPE) \ 717 void \ 718 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 719 void *v; \ 720 bus_space_handle_t h; \ 721 bus_size_t o, c; \ 722 const TYPE *a; \ 723 { \ 724 \ 725 while (c-- > 0) { \ 726 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 727 o += sizeof *a; \ 728 } \ 729 } 730 CHIP_io_write_region_N(1,u_int8_t) 731 CHIP_io_write_region_N(2,u_int16_t) 732 CHIP_io_write_region_N(4,u_int32_t) 733 CHIP_io_write_region_N(8,u_int64_t) 734 735 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 736 void \ 737 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 738 void *v; \ 739 bus_space_handle_t h; \ 740 bus_size_t o, c; \ 741 TYPE val; \ 742 { \ 743 \ 744 while (c-- > 0) { \ 745 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 746 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 747 BUS_SPACE_BARRIER_WRITE); \ 748 } \ 749 } 750 CHIP_io_set_multi_N(1,u_int8_t) 751 CHIP_io_set_multi_N(2,u_int16_t) 752 CHIP_io_set_multi_N(4,u_int32_t) 753 CHIP_io_set_multi_N(8,u_int64_t) 754 755 #define CHIP_io_set_region_N(BYTES,TYPE) \ 756 void \ 757 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 758 void *v; \ 759 bus_space_handle_t h; \ 760 bus_size_t o, c; \ 761 TYPE val; \ 762 { \ 763 \ 764 while (c-- > 0) { \ 765 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 766 o += sizeof val; \ 767 } \ 768 } 769 CHIP_io_set_region_N(1,u_int8_t) 770 CHIP_io_set_region_N(2,u_int16_t) 771 CHIP_io_set_region_N(4,u_int32_t) 772 CHIP_io_set_region_N(8,u_int64_t) 773 774 #define CHIP_io_copy_region_N(BYTES) \ 775 void \ 776 __C(__C(CHIP,_io_copy_region_),BYTES)(v, h1, o1, h2, o2, c) \ 777 void *v; \ 778 bus_space_handle_t h1, h2; \ 779 bus_size_t o1, o2, c; \ 780 { \ 781 bus_size_t o; \ 782 \ 783 if ((h1 + o1) >= (h2 + o2)) { \ 784 /* src after dest: copy forward */ \ 785 for (o = 0; c != 0; c--, o += BYTES) { \ 786 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 787 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 788 } \ 789 } else { \ 790 /* dest after src: copy backwards */ \ 791 for (o = (c - 1) * BYTES; c != 0; c--, o -= BYTES) { \ 792 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 793 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 794 } \ 795 } \ 796 } 797 CHIP_io_copy_region_N(1) 798 CHIP_io_copy_region_N(2) 799 CHIP_io_copy_region_N(4) 800 CHIP_io_copy_region_N(8) 801