1 /* $NetBSD: pci_6600.c,v 1.25 2014/03/21 16:39:29 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 by Ross Harvey. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Ross Harvey. 17 * 4. The name of Ross Harvey may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS 21 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE 23 * ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY 24 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.25 2014/03/21 16:39:29 christos Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <machine/autoconf.h> 45 #define _ALPHA_BUS_DMA_PRIVATE 46 #include <sys/bus.h> 47 #include <machine/rpb.h> 48 #include <machine/alpha.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pciidereg.h> 53 #include <dev/pci/pciidevar.h> 54 55 #include <alpha/pci/tsreg.h> 56 #include <alpha/pci/tsvar.h> 57 #include <alpha/pci/pci_6600.h> 58 59 #define pci_6600() { Generate ctags(1) key. } 60 61 #include "sio.h" 62 #if NSIO 63 #include <alpha/pci/siovar.h> 64 #endif 65 66 #define PCI_NIRQ 64 67 #define PCI_STRAY_MAX 5 68 69 /* 70 * Some Tsunami models have a PCI device (the USB controller) with interrupts 71 * tied to ISA IRQ lines. The IRQ is encoded as: 72 * 73 * line = 0xe0 | isa_irq; 74 */ 75 #define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 76 #define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f) 77 78 static const char *irqtype = "6600 irq"; 79 static struct tsp_config *sioprimary; 80 81 void dec_6600_intr_disestablish(void *, void *); 82 void *dec_6600_intr_establish( 83 void *, pci_intr_handle_t, int, int (*func)(void *), void *); 84 const char *dec_6600_intr_string(void *, pci_intr_handle_t, char *, size_t); 85 const struct evcnt *dec_6600_intr_evcnt(void *, pci_intr_handle_t); 86 int dec_6600_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 87 void *dec_6600_pciide_compat_intr_establish(void *, device_t, 88 const struct pci_attach_args *, int, int (*)(void *), void *); 89 90 struct alpha_shared_intr *dec_6600_pci_intr; 91 92 void dec_6600_iointr(void *arg, unsigned long vec); 93 extern void dec_6600_intr_enable(int irq); 94 extern void dec_6600_intr_disable(int irq); 95 96 void 97 pci_6600_pickintr(struct tsp_config *pcp) 98 { 99 bus_space_tag_t iot = &pcp->pc_iot; 100 pci_chipset_tag_t pc = &pcp->pc_pc; 101 char *cp; 102 int i; 103 104 pc->pc_intr_v = pcp; 105 pc->pc_intr_map = dec_6600_intr_map; 106 pc->pc_intr_string = dec_6600_intr_string; 107 pc->pc_intr_evcnt = dec_6600_intr_evcnt; 108 pc->pc_intr_establish = dec_6600_intr_establish; 109 pc->pc_intr_disestablish = dec_6600_intr_disestablish; 110 pc->pc_pciide_compat_intr_establish = NULL; 111 112 /* 113 * System-wide and Pchip-0-only logic... 114 */ 115 if (dec_6600_pci_intr == NULL) { 116 sioprimary = pcp; 117 pc->pc_pciide_compat_intr_establish = 118 dec_6600_pciide_compat_intr_establish; 119 #define PCI_6600_IRQ_STR 8 120 dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 121 PCI_6600_IRQ_STR); 122 for (i = 0; i < PCI_NIRQ; i++) { 123 alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i, 124 PCI_STRAY_MAX); 125 alpha_shared_intr_set_private(dec_6600_pci_intr, i, 126 sioprimary); 127 128 cp = alpha_shared_intr_string(dec_6600_pci_intr, i); 129 snprintf(cp, PCI_6600_IRQ_STR, "irq %d", i); 130 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 131 dec_6600_pci_intr, i), EVCNT_TYPE_INTR, NULL, 132 "dec_6600", cp); 133 } 134 #if NSIO 135 sio_intr_setup(pc, iot); 136 dec_6600_intr_enable(55); /* irq line for sio */ 137 #endif 138 } 139 } 140 141 int 142 dec_6600_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 143 { 144 pcitag_t bustag = pa->pa_intrtag; 145 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 146 pci_chipset_tag_t pc = pa->pa_pc; 147 int bus, device, function; 148 149 if (buspin == 0) { 150 /* No IRQ used. */ 151 return 1; 152 } 153 if (buspin > 4) { 154 printf("intr_map: bad interrupt pin %d\n", buspin); 155 return 1; 156 } 157 158 pci_decompose_tag(pc, bustag, &bus, &device, &function); 159 160 /* 161 * The console places the interrupt mapping in the "line" value. 162 * A value of (char)-1 indicates there is no mapping. 163 */ 164 if (line == 0xff) { 165 printf("dec_6600_intr_map: no mapping for %d/%d/%d\n", 166 bus, device, function); 167 return (1); 168 } 169 170 #if NSIO == 0 171 if (DEC_6600_LINE_IS_ISA(line)) { 172 printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n", 173 DEC_6600_LINE_ISA_IRQ(line), bus, device, function); 174 return (1); 175 } 176 #endif 177 178 if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ) 179 panic("dec_6600_intr_map: dec 6600 irq too large (%d)", 180 line); 181 182 *ihp = line; 183 return (0); 184 } 185 186 const char * 187 dec_6600_intr_string(void *acv, pci_intr_handle_t ih, char *buf, size_t len) 188 { 189 190 static const char irqfmt[] = "dec 6600 irq %ld"; 191 192 #if NSIO 193 if (DEC_6600_LINE_IS_ISA(ih)) 194 return (sio_intr_string(NULL /*XXX*/, 195 DEC_6600_LINE_ISA_IRQ(ih), buf, len)); 196 #endif 197 198 snprintf(buf, len, irqfmt, ih); 199 return buf; 200 } 201 202 const struct evcnt * 203 dec_6600_intr_evcnt(void *acv, pci_intr_handle_t ih) 204 { 205 206 #if NSIO 207 if (DEC_6600_LINE_IS_ISA(ih)) 208 return (sio_intr_evcnt(NULL /*XXX*/, 209 DEC_6600_LINE_ISA_IRQ(ih))); 210 #endif 211 212 return (alpha_shared_intr_evcnt(dec_6600_pci_intr, ih)); 213 } 214 215 void * 216 dec_6600_intr_establish(void *acv, pci_intr_handle_t ih, int level, int (*func)(void *), void *arg) 217 { 218 void *cookie; 219 220 #if NSIO 221 if (DEC_6600_LINE_IS_ISA(ih)) 222 return (sio_intr_establish(NULL /*XXX*/, 223 DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 224 #endif 225 226 if (ih >= PCI_NIRQ) 227 panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx", 228 ih); 229 230 cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL, 231 level, func, arg, irqtype); 232 233 if (cookie != NULL && 234 alpha_shared_intr_firstactive(dec_6600_pci_intr, ih)) { 235 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_6600_iointr, NULL, 236 level); 237 dec_6600_intr_enable(ih); 238 } 239 return (cookie); 240 } 241 242 void 243 dec_6600_intr_disestablish(void *acv, void *cookie) 244 { 245 struct alpha_shared_intrhand *ih = cookie; 246 unsigned int irq = ih->ih_num; 247 int s; 248 249 #if NSIO 250 /* 251 * We have to determine if this is an ISA IRQ or not! We do this 252 * by checking to see if the intrhand points back to an intrhead 253 * that points to the sioprimary TSP. If not, it's an ISA IRQ. 254 * Pretty disgusting, eh? 255 */ 256 if (ih->ih_intrhead->intr_private != sioprimary) { 257 sio_intr_disestablish(NULL /*XXX*/, cookie); 258 return; 259 } 260 #endif 261 262 s = splhigh(); 263 264 alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype); 265 if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) { 266 dec_6600_intr_disable(irq); 267 alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq, 268 IST_NONE); 269 scb_free(0x900 + SCB_IDXTOVEC(irq)); 270 } 271 272 splx(s); 273 } 274 275 void 276 dec_6600_iointr(void *arg, unsigned long vec) 277 { 278 int irq; 279 280 irq = SCB_VECTOIDX(vec - 0x900); 281 282 if (irq >= PCI_NIRQ) 283 panic("iointr: irq %d is too high", irq); 284 285 if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) { 286 alpha_shared_intr_stray(dec_6600_pci_intr, irq, 287 irqtype); 288 if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq)) 289 dec_6600_intr_disable(irq); 290 } else 291 alpha_shared_intr_reset_strays(dec_6600_pci_intr, irq); 292 } 293 294 void 295 dec_6600_intr_enable(int irq) 296 { 297 alpha_mb(); 298 STQP(TS_C_DIM0) |= 1UL << irq; 299 alpha_mb(); 300 } 301 302 void 303 dec_6600_intr_disable(int irq) 304 { 305 alpha_mb(); 306 STQP(TS_C_DIM0) &= ~(1UL << irq); 307 alpha_mb(); 308 } 309 310 void * 311 dec_6600_pciide_compat_intr_establish(void *v, device_t dev, 312 const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 313 { 314 pci_chipset_tag_t pc = pa->pa_pc; 315 void *cookie = NULL; 316 int bus, irq; 317 char buf[64]; 318 319 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 320 321 /* 322 * If this isn't PCI bus #0 on the TSP that holds the PCI-ISA 323 * bridge, all bets are off. 324 */ 325 if (bus != 0 || pc->pc_intr_v != sioprimary) 326 return (NULL); 327 328 irq = PCIIDE_COMPAT_IRQ(chan); 329 #if NSIO 330 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 331 func, arg); 332 if (cookie == NULL) 333 return (NULL); 334 aprint_normal_dev(dev, "%s channel interrupting at %s\n", 335 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq, 336 buf, sizeof(buf))); 337 #endif 338 return (cookie); 339 } 340